JP2974519B2 - Computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laptop or notebook type personal portable computer.

[0002]

2. Description of the Related Art In recent years, various portable personal computers of a laptop type or a notebook type have been developed.

[0003] A portable computer of this type is a CP.
U, a memory, and a plurality of various peripheral controllers, and the CPU and the peripheral controllers are interconnected via a system bus. In this case, various commands are transmitted and received between the CPU and each peripheral controller, but all of the commands are transferred via the system bus.

Communication between the CPU and the peripheral controller via the system bus is realized by a so-called handshake method, and every time a command is transferred, it is necessary to exchange various control signals for communication. Therefore, there is no problem when the number of times of command transmission / reception between the CPU and the peripheral controller is relatively small. As a result, a disadvantage that the processing performance of the entire system is reduced is caused.

[0005] The number of times of command transmission / reception is increased when a specific peripheral controller is provided with a special function in order to extend the functions of a portable computer. That is, when the peripheral controller has a special function, a command for realizing the special function is also added. The added command is transferred via the system bus in the same manner as a conventional command for realizing existing functions. As a result, when the function is extended, the number of times of command transmission / reception increases by that amount.

Therefore, although the function expansion can be achieved by adding a special function, the occupation time of the system bus and the CPU due to the command transfer between the CPU and the specific peripheral controller is increased, and as a result, the entire system is increased. There is a problem that the operation performance is reduced.

The data transfer between the CPU and the peripheral controller is performed when the CPU writes a command in an I / O register in the peripheral controller or reads a command set in the I / O register by the peripheral controller. It is done by. For this reason, when a special function is added to a specific peripheral controller, transmission and reception of commands necessary for realizing the special function are executed via the I / O register of the peripheral controller, similarly to other existing commands. Will be.

Therefore, when a function that is requested to be activated during the execution of the application program is added as a special function, the read / write of the I / O register conflicts between the application program and the command of the special function. This may cause a problem that execution of the application program is hindered. This is because, for example, when a command is set in an I / O register by an application program being executed, execution of a special function is requested, and a command for executing the special function is overwritten by an application command. It occurs at times.

[0009] The influence on the application program due to such factors can be obtained by performing a process of temporarily saving the contents of the I / O register set by the application program being executed when the execution of the special function is requested. Can be avoided. However, when such a process is performed, the processing procedure for executing the special function becomes complicated, so that it takes a lot of time from when the execution of the special function is requested by the user until the actual execution of the special function. It takes time.

[0010]

In a conventional portable computer, all control information exchanged between a CPU and a peripheral controller is transferred via a system bus, so that a special function is added to extend the function. And CP
There is a disadvantage that the exclusive time of the system bus and the CPU due to command transfer between the U and the peripheral controller is increased, and as a result, the operation performance of the entire system is reduced. In addition, there is a drawback that the execution of the extended function hinders the execution of the application program.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a portable computer capable of efficiently realizing a function expansion of a system without deteriorating system performance.

[0012]

SUMMARY OF THE INVENTION The present invention provides
CPU, memory, system bus, and system bus
Peripheral controllers connected to the CPU via
Computer system having the system
Between the CPU and the peripheral controller, and
Various types of control information exchanged between the peripheral controllers
Special registers that are set occasionally and this special register
Provided between the group and the peripheral controller, multiple bits wide
And a controller bus in which the data lines are defined,
The peripheral controller includes the controller bus and
First and second connected respectively to the system bus
And the first communication port and the
The CPU via a controller bus and a dedicated register group
And the first control information, and the second communication port,
And second control with the CPU via the system bus
It is characterized by sending and receiving information.

In this computer system , a dedicated register group is provided between the system bus and the peripheral controller, and the dedicated register group and the peripheral controller are connected via a controller bus. Therefore, the CPU reads / writes the dedicated register group via the system bus, and the peripheral controller reads / writes the dedicated register group via the controller bus, so that transmission / reception of control information between the CPU and the peripheral controller is executed. Is done.

In this case, in the transfer from the CPU to the peripheral controller, the peripheral controller can execute other processing while the CPU is writing the control information to the dedicated register group via the system bus. After writing the control information to the dedicated register group, the CPU and the system bus are released from the transfer of the control information. Similarly, in the transfer from the peripheral controller to the CPU,
While the peripheral controller is writing control information to the dedicated register group via the controller bus, the CPU and the system bus are released from the transfer of the control information, and can execute other processing. Therefore, even if CP
Even if the number of transfers of the control information between the U and the peripheral controller is increased, the occupation time of the system bus and the CPU due to the transfer can be reduced, so that the function of the system can be efficiently expanded without lowering the system performance. be able to.

Further, according to the present invention, the peripheral controller has first and second communication ports respectively connected to the controller bus and the system bus, and the first control information is used for the first communication port. ,
The second control information is transmitted to and received from the CPU via the controller bus and the dedicated register group.
Through the communication port and the system bus.
It is configured to exchange with U.

According to this configuration, for example, an additional command accompanying the function expansion is transmitted / received as first control information to / from the CPU via the controller bus and the dedicated register group, and other existing commands used by the application program or the like are transmitted. Can be exchanged with the CPU via the system bus. Therefore, the extended function can be executed while maintaining the compatibility with the conventional system and without affecting the execution of the application program.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration of a portable computer according to an embodiment of the present invention.

This portable computer is a laptop or notebook type personal portable computer, and is an ISA (Industry Stand).
ardArchitecture) system bus (ISA-B)
US) 11, peripheral interface bus (PI-BUS; Peripheral Interface) for high-speed graphic transfer
BUS) 12, keyboard interface bus (KB)
C-BUS 13 and a power supply interface bus (PSC-BUS) 14.

A CPU 21 and an I / O controller 22 are connected to a system bus (ISA-BUS) 11. CPU 21 and I / O controller 22
For example, a microprocessor 80386SL manufactured and sold by Intel Corporation in the United States and a family chip 82360SL are used.

The CPU 21 controls the entire system and executes a program to be processed stored in the system memory 23. Also, this CPU 21
Has a power management function for low power consumption, such as powering down various I / Os at idle. This power management function includes a system management interrupt (SMI;
This is executed by an interrupt process called (System Management Interrupt). The interrupts of the CPU 21 include non-maskable interrupts (NM
I: Non-Maskable Interrupter, and a maskable interrupt (INTR: Maskable Interrupter).
The SMI, which is a kind of non-maskable interrupt, is a hardware interrupt of the highest priority, which has a higher priority than the above-mentioned NMI and INTR, and is activated by activating the interrupt request input SMI of the CPU 21.
Similarly, the non-maskable interrupt and the maskable interrupt also correspond to an interrupt request input NM (not shown) of the CPU 21.
Activated by activating I and INTR, respectively.

The interrupt processing by the SMI is used not only for a function for power management but also for executing an extended function such as a hot key processing described later.

The I / O controller 22 is a dedicated logic for realizing the CPU and memory support functions, and controls an I / O device connected to the serial port 41 and a printer port (EPP: Enhanced Print).
erPort) 43 to control an external printer. The I / O controller 22 includes two DMA controllers for direct memory access control, and an interrupt controller (PIC; Programmable Interter).
rupt Controller), two timers (PIT; Progr)
ammable Interval (Timer) 2 pieces, serial I / O
Controller (SIO; Serial Input / Output Con)
troller), real-time clock (RTC; R)
eal Time Clock). The real-time clock is a clock module having a unique operation battery, and has a static RAM (hereinafter, referred to as a CMOS memory) having a CMOS configuration to which power is constantly supplied from the battery. This CMOS memory is used for storing setup information indicating the system configuration.

CPU 21 and I / O controller 22
Communication between them is executed via a system bus (ISA-BUS) 11 or a dedicated interface line provided between the CPU 21 and the I / O controller 22. CP
The interface signal between the U 21 and the I / O controller 22 includes, for example, a signal for controlling the SMI function of the CPU 21 and the like.

That is, an active-low SMI signal output from the I / O controller 22 or the status LCD control gate array (SLCDC GA) 26 is supplied to the interrupt request input SMI of the CPU 21 via the AND gate G1. . The SMI signal from the status LCD control gate array (SLLCD GA) 26 is generated when requesting the CPU 21 for a hot key process and other special processes accompanying the function expansion, which will be described later, and the I / O controller 22. The SMI signal is generated when the necessity of power-down of the I / O is detected by time monitoring by a timer or the like.

Here, the hot key is a key for directly requesting the CPU 21 to execute a special function such as setting / changing of the system operating environment to the CPU 21.
The specific keys above are assigned as the hotkeys. When this hot key is operated, the CPU
Some functions related to setting / changing the system operating environment provided by 21 are directly called and executed.
In this hot key processing, the system bus (ISA)
An SMI is issued to the CPU 21 without performing normal key data transmission via the (BUS) 11 and the key data of the hot key is transmitted through the keyboard interface bus (KBC-BUS) 13 and the status LCD control gate array (SLCDGA). Sent to CPU 21.

C which can be called by hot key
The functions of the PU 21 include an instant security function, a power save mode switching function, a resume / boot mode switching function, an LCD / CRT display switching function, and an LCD panel black / white inverted display function. These functions are provided by a program stored in the BIOS-ROM 25, which will be described later. Which program is executed is determined by an SMI processing program started by the SMI. Since the SMI processing program is a memory-resident termination type program, a function corresponding to the pressed hot key can be immediately called even during the execution of the application program.

The functions which can be called by the hot keys include functions directly executed and controlled by hardware instead of the CPU 21. This feature includes
Some are executed by a keyboard controller (KBC) 30 described later, and others are executed by a power supply controller (PSC) 46. Provided by the keyboard controller (KBC) 30 is the keyboard 5
"Arrow" mode setting function in which some keys on the keyboard 1 are overlaid on arrow keys, and "Nu" on which some keys on the keyboard 51 are overlaid on numeric keys.
setting function of “meric” mode, “S” of the keyboard 51
A function of setting a “lock lock” mode is provided by a power supply controller (PSC) 46.
A function of adjusting the contrast / brightness of the LCD panel 49 and a function of adjusting the volume of a speaker (not shown).

A system memory 23 and an optional DRAM card 24 are connected to a local bus of the CPU 21. The system memory 23 is used as a main memory of the system, and stores programs and data to be processed. The system memory 23 has a storage capacity of 4 Mbytes as standard. The DRAM card 24 is used as an extension memory of the computer system, and is optionally connected to a dedicated card slot of 88 pins provided in the computer body. This DRAM card 24 has 2
There are types such as M bytes, 4 M bytes, 8 M bytes, and 16 M bytes.

A system bus (ISA-BUS) 1
1 is connected to a BIOS-ROM 25. The BIOS-ROM 25 stores a basic input / output program (BI
The OS is for storing a basic I / O system, and is constituted by a flash memory (FLASH MEM) so that a program can be rewritten. The basic input / output program includes a program for initialization processing at power-on, a driver program for controlling various input / output devices, and a program for performing processing related to hot key operations. ing.

The system bus (ISA-BUS) 11 further includes a status LCD control gate array (SL).
CDC GA) 26, floppy disk controller (FDC) 27, PCMCIA gate array (PCMC
IA GA) 28, keyboard controller (KBC)
30, an expansion connector 31 to which an expansion unit (Desk Station) can be attached, and a hard disk drive (H
DD) 42 is connected.

The status LCD control gate array (SL
The CDC GA) 26 controls display of the status LCD 44, communicates with the keyboard controller (KBC) 30,
And a power supply controller (PSC) 46. In the display control of the status LCD 44, the status LCD control gate array (SLCDC GA) 2
Reference numeral 6 denotes a status L indicating the remaining battery operation time and various operating environment states which can be set / changed by operating a hot key.
Display on CD44. In this case, the remaining battery operation time is indicated by a numeral, and the other operating environment states are indicated by icons. Also, the remaining battery capacity can be displayed in percentage instead of the remaining battery operation time. Whether to display the remaining operation time or the remaining capacity as a percentage can be selected by changing the setup information of the CMOS memory.

The status LCD 44 is a liquid crystal sub-display dedicated to state display provided for displaying various operation states of the portable computer, that is, the above-mentioned remaining battery operation time and various operation mode setting states. Specific display contents of the status LCD 44 will be described later with reference to FIG.

Status LCD control gate array (SL
CDC GA) 26 and keyboard controller (KB)
The communication between the CPU 30 and the keyboard controller (KBC) 30 is performed for high-speed transfer of various control information between the CPU 21 and the keyboard controller (KBC) 30. A dedicated keyboard interface bus (KBC-BUS) 1 is used for the communication.
3 is used. That is, the status LCD control gate array (SLCDCGA) 26 has a plurality of register groups for temporarily holding control information exchanged between the CPU 21 and the keyboard controller (KBC) 30, and the keyboard controller (KBC) 30. Reads / writes the registers via a keyboard interface bus (KBC-BUS) 13, and the CPU 21 reads / writes these registers via the system bus 11. In this register group, the aforementioned SMI signal is
A register (Fn) used to supply the data to the ND gate G1 and a key (Fn) holding the key data of the hot key transmitted from the keyboard controller (KBC) 30
Status register).

Status LCD control gate array (SL
CDC GA) 26 and Power Supply Controller (PSC) 46
Communication with the CPU 21 and the power supply controller (PSC)
The transfer is performed for high-speed transfer of various kinds of control information between 46 and the dedicated power supply interface bus (PSC-BUS) 14 is used for the communication. That is, the status LCD control gate array (SLCDC)
GA) 26 includes a CPU 21 and a power controller (PS).
C) I that temporarily holds control information exchanged between 46
/ O register group, and the power supply controller (PS
C) 46 is a power supply interface bus (PSC-BU).
S) Read / write the corresponding register group via 14. The CPU 21 reads / writes these register groups via the system bus 11. The function of the hot key processing by the power supply controller (PSC) 46 is a status LCD control gate array (SLCDC GA) 26
This is executed by reading key data of the Fn status register through the power supply interface bus (PSC-BUS) 14.

Floppy disk controller (FD)
C) 27 is a 3.5-inch, 750K / 1.44 Mbyte 2-mode floppy disk drive (FDD)
45, and has a built-in variable frequency oscillator (VFO).

PCMCIA gate array (PCMCIA
GA) 28 is a PCMCIA slot 48a, 48b.
68-pin PCMCIA (Per
sonal Computer Memory Card International Ass
ociatuon) performs card read / write control and communicates with a keyboard controller (KBC) 30. In addition, this PCMCIA gate array (PCMCIA G
A) 28 includes logic for interfacing with the EEPROM 29 and logic for implementing the security function.

Two PCMCIA slots 48a, 48
b, the slot 48a is for all types of cards, ie, 1
It supports four types of PCMCIA cards, 8 mm thick Thick type, 10.5 mm thick type 3, 5.0 mm thick type 2 and 3.3 mm thick type 1, and the slot 48b is 5.0 mm thick or 3 mm thick. It supports two types of PCMCIA cards, type 2 and type 1 with a thickness of 0.3 mm. Here, a small PCMCIA card having a thickness of 5.0 mm or 3.3 mm is used as a security card. PCMCIA gate array (P
The security function of the CMCIA GA) 28 is based on the security code read from the security card and the EEPROM 2
Verification of the security code No. 9 is performed, and a process of permitting the system to be started only when the passwords match is performed.

Further, the security function includes a function called instant security. This instant security function is supported by a keyboard controller (KB
C) In response to a predetermined hot key processing instruction from 30, the display screen of the LCD panel 49 is turned off or the keyboard 5 is turned off.
1 is for performing a process such as key lock, and is restored to the original state when a predetermined password is input by a key operation of the keyboard 51 by the user. The password verification at this time is performed by the keyboard controller (KBC).
30 is a PCMCIA gate array (PCMCIA G
A) It is performed by reading the password from the register at 28 and comparing it to the keyed-in password. The verification results were obtained from the PCMCIA gate array (PC
MCIA GA) 28, for example, SMI
Is sent to the CPU 21.

Keyboard controller (KBC) 30
Is for controlling a standard built-in keyboard 51 built in the computer main body, scans a key matrix of the built-in keyboard 51, receives a signal corresponding to a pressed key, and converts the signal into a predetermined key code ( Scan code). In this case, the key code corresponding to the hot key provided on the built-in keyboard 51 is a keyboard interface bus (KBC).
BUS) 13 to the status LCD control gate array (SLDC GA) 26 and transmitted to the CPU 21 by SMI. On the other hand, other key codes other than the hot keys are used as usual in the system bus (ISA-
BUS) 11 and transmitted to the CPU 21 by the INTR. Also, a keyboard controller (KBC) 3
0 also has a function of controlling a mouse 42 and an external keyboard 53 which are optionally connected.

The extension connector 31 has an extension unit (D
(esk Station) can be connected, and the functions can be expanded by mounting various expansion boards such as a communication board to the expansion unit. Hard disk drive (H
The DD 42 is an IDE (Integrated Drive Electro).
nics) interface, and the access is directly controlled by the CPU 21. This hard disk drive (HDD) 42 is 2.5 inches, 120M / 200
It has a storage capacity of M bytes.

Peripheral interface bus (PI-BU)
The S) 12 is connected to a display controller (hereinafter, referred to as a VGA controller) 32 conforming to the VGA (Video Graphics Array) specification. The VGA controller 32 is provided with an LCD panel 4 having a backlight of monochrome gradation display or color display, which is provided as standard.
9, for controlling display of the color CRT 50 which is optionally connected, receives image data from the CPU 21 via the peripheral interface bus (PI-BUS) 12, and renders the image data in the image memory (VRAM) 33. In this case, the system bus (ISA-BUS)
Since 11 is not used, the transfer of image data does not lower the system performance. LCD panel 49
Is configured to be adjusted by a hot key operation from the keyboard 51.

Further, this system is provided with a power supply controller (PSC) 46 and a power supply circuit (PS) 47. The power supply controller (PSC) 46
This is for controlling the supply of the power supply voltage from the power supply circuit 47 to each unit in accordance with an instruction from the PU 21.
Communication with U21 is performed by the power supply interface bus (PSC).
-BUS) 14 and a register of the status LCD control gate array (SLCDC GA) 26. The power supply controller (PSC) 46 includes a status LCD control gate array (SLCDC GA).
According to the key data input to the Fn status register 26, hot key processing such as brightness / contrast adjustment of the LCD panel 49 and speaker volume adjustment is also performed. The power supply circuit 47 generates an internal power supply having a predetermined voltage value to be supplied to each unit from a battery built in the computer main body or an external power supply supplied via an AC adapter. The power supply circuit 47 also generates a backup power supply BK and supplies it to each unit even when the power switch of the computer is turned off.

FIG. 2 shows an appearance of the computer and an example of a display screen of the status LCD 44.

As shown in the figure, a keyboard 51 is incorporated in the main body of the computer and a status LCD 44 is provided. The LCD panel 49 is provided rotatably between a release position and a closed position with respect to the main body. The status LCD 44 has a display area R1 for numerically displaying the remaining usage time of the battery and the like, and ten icon display areas R2 to R11.

In the display area R1, a three-digit number segment for displaying a residual battery capacity is displayed. In this case, the residual image capacity is numerically displayed as the remaining use time or the percentage of the remaining capacity. In the case of time display, a mark icon of ":" is lit, and in the case of percentage display, a mark icon of "%" is lit. In the icon display area R2, an icon indicating whether the battery is driven by the AC adapter or the battery is displayed. In this case, when the AC adapter is driven, the icon of the jack plug is lit as shown in the figure,
The jack plug icon is turned off during battery operation. In the icon display area R3, a water tap icon indicating the setting state of the battery save mode is displayed according to the number of lighting of the water drops. The battery save mode includes three modes (full power mode, economy mode) including a combination of CPU clock frequency, CPU sleep mode setting, and display / HDD auto-off function setting. , Low power mode) and a user setting mode in which the operation modes can be set arbitrarily. The power consumption is highest in the full power mode, second in the economy mode, and lowest in the low power mode. The number of lighted water droplets of the tap is also changed according to the power consumption. At the time of the full power mode, all the water droplets are lighted, and the number of lighted water droplets decreases in the order of the economy mode and the low power mode. The number of lighting of water droplets in the user setting mode is determined according to the setting state of each operation mode at that time. In the user setting mode, a hand icon as shown in the figure is constantly lit. The hand icon is turned off in modes other than the user setting mode, that is, in the full power mode, economy mode, and low power mode. Switching between the full power mode, the economy mode, the low power mode, and the user setting mode is executed by a hot key process provided by the CPU 21.

In the icon display area R4, a book icon as shown in the figure indicating whether the mode is the resume mode or the boot mode is displayed. In this case, the book icon is turned on in the resume mode, and turned off in the boot mode. The switching between the resume mode and the boot mode is also executed by a hot key process provided by the CPU 21.

In the icon display areas R5 and R6, a hard disk icon and a floppy disk icon which are turned on when a hard disk and a floppy disk are used, respectively, are displayed. In the icon display area R7, a mail icon indicating reception of an electronic mail is displayed. In the icon display areas R8, R9, R10, and R11, an alphabet icon, an arrow icon, a numeric keypad icon, and a scroll icon for indicating the key input mode of the keyboard are displayed, respectively. In this case, in the normal key input mode, the alphabet icon in the display area R8 is lit, and Arrow using the overlay arrow keys is used.
In the mode, the arrow icon in the display area R9 is turned on, in the Numeric mode using the numeric keypad of the overlay, the numeric keypad icon in the display area R10 is turned on, and in the scroll lock mode, the scroll icon in the display area R11 is turned on. The switching of these key input modes is performed by hot key processing provided by a keyed controller (KBC) 30.

FIG. 3 shows an extracted hardware configuration related to the communication between the CPU 21 and the keyboard controller (KBC) 30, and the communication between the CPU 21 and the power supply controller (PSC) 46.

As described above, communication of control information between the CPU 21 and the keyboard controller (KBC) 30 is performed by the status LCD control gate array (SLDCGA).
Keyboard controller (KBC) 3 provided in 26
The CPU 21 transmits a register group for communication with the
1, and the registers are read / written by a keyboard controller (KBC) 30 via a keyboard interface bus (KBCBUS) 13. In this case, CPU2
In the transfer from 1 to the keyboard controller (KBC) 30, the keyboard controller (KBC) 30 may execute other processing while the CPU 21 is writing control information to the register group via the system bus 11. When the control information is written to the registers, the status LCD control gate array (SLCDC)
GA) 26 to keyboard controller (KBC) 30
The request signal is sent to
Communication is performed between a D-control gate array (SLCDC GA) 26 and a keyboard controller (KBC) 30. During this period, the CPU 21 and the system bus 11 are released from the transfer of the control information. Similarly, in the transfer from the keyboard controller (KBC) 30 to the CPU 21, the keyboard controller (KBC) 30 uses the keyboard interface bus (KBC BUS) 1
While the control information is being written to the register group via the register 3, the CPU 21 and the system bus 11 are released from the transfer of the control information. An SMI signal is transmitted from the array (SLCDC GA) 26 to the CPU 21, and thereafter, communication is performed between the status LCD control gate array (SLCDC GA) 26 and the CPU 21. During this period, the keyboard controller (KB
C) 30 is released from the transfer of the control information.

Therefore, even if the number of data transfers between the CPU 21 and the keyboard controller (KBC) 30 is increased, the system bus 11 or C
Since the increase in the time in which the PU 21 is occupied is small, the keyboard controller (KBC) 30 can be provided with a special function related to a function expansion of the system, such as a hot key or security, without deteriorating the system performance.

The CPU 21 and the power supply controller (P
The CPU 21 reads / writes a register group for communication with the power supply controller (PSC) 46 provided in the status LCD control gate array (SDLCD GA) 26 via the system bus 21 for communication of control information between the SC 46. , And the register group as a power controller (PSC) 4
6 is a power interface bus (PSC BUS) 14
This is realized by reading / writing via the.
In this case, the CPU 21 and the keyboard controller (KB
Similarly to the communication between C) 30, a request signal is transmitted to the power supply controller (PSC) 46 when transferring from the CPU 21 to the power supply controller (PSC) 46, and an SMI is transmitted to the CPU 21 when transferring from the power supply controller (PSC) 46 to the CPU 21. A signal is transmitted.

Next, transmission of key data of a hot key will be described as an example of communication between the CPU 21 and the keyboard controller (KBC) 30.

Transmission of the key data of the hot key is performed by Fn assigned as a hot key register in a register group for communication with the keyboard controller (KBC) 30.
This is performed using the status register 101 and the SMI transmission register 102.

As described above, the hot key process is started by operating a specific key assigned as a hot key on the keyboard 51. Specifically, by simultaneously pressing the [Fn] key and specific keys such as [F1], [F2},..., ([Fn] +
(A specific key), and several hot key processes predefined for each specific key can be selectively called.

[Fn] + When a specific key is pressed, the keyed controller (KBC) 30 sends a status via the keyboard interface bus (KBC BUS) 13 to notify the CPU 21 of key data of the hot key. LCD control gate array (SLCDC GA)
26, key data is written to the Fn status register 101, and then bit 7 of the SMI transmission register 102
Is written with data "1" for SMI issuance. As key data set in the Fn status register 101, a scan code (make code / break code) of a key pressed simultaneously with the [Fn] key is used.

When "1" is set to bit7 of the SMI transmission register 102, a low level SM is sent from the status LCD control gate array (SLLCD GA) 26.
I signal is generated, which is coupled to C through AND gate G1.
It is supplied to the PU 21.

The CPU 21 starts the SMI processing program resident in the memory 23 in response to the SMI signal, and performs the following processing.

That is, the CPU 21 first reads the Fn status register 101 of the status LCD control gate array (SLLCD GA) 26 to determine whether or not the SMI is caused by a hot key operation. If key data is set in the Fn status register 101, C
The PU 21 detects that it is a hot key process, and according to the contents of the key data, instant security,
Switching of battery save mode, switching of resume / boot mode, switching of LCD / CRT display, L
The function of various hot keys such as switching of the black and white inverted display of the CD panel 49 is executed.

In this case, when executing a function that requires changing the icon display of the status LCD 44, that is, a function of switching the battery save mode or a function of switching the resume / boot mode, the CPU 21 sets the status LCD control gate array ( SLCDC GA) 2
The control data is written in the icon display control register provided in the control LCD 6 so that the ON / OFF state of the icon of the status LCD 44 is controlled in accordance with the contents of the mode switching.

When the function of the hot key processing designated by [Fn] + specific key is the keyboard overlay or scroll lock function, the corresponding processing is executed by the keyboard controller (KBC) 30 itself. Therefore, the CPU 21 returns from the hot key processing routine without executing anything.

On the other hand, a power supply controller (PSC) 46
Power supply interface bus (PSC BUS) 14
Via the status LCD control gate array (SLCD)
CGA) 26, and polls Fn
The contents of the status register 101 are read. If the key data set in the Fn status register 101 indicates volume switching of the speaker or brightness / contrast adjustment of the LCD panel 49, the power supply controller (PSC) 46 executes a corresponding process. Also in this case, the CPU 21 returns from the hot key processing routine without performing any processing.

A power supply controller (PSC) 46
Is the ON / OFF of the power switch of this computer,
When the attachment / detachment of the AC adapter, the low battery state, and the like are detected, the detection information is notified via the power supply interface bus (PSC BUS) 14 to notify the CPU 21 of the detection information.
A) Write to a predetermined register of 26. At this time, similarly to the case of the above-mentioned hot key, the SMI signal
This is generated in U21, and the interrupt processing of the CPU 21 is started.

Next, referring to FIG.
An example of a specific configuration of the control gate array (SLLCD GA) 26 will be described.

As shown in FIG. 4, the status L
The CD control gate array (SLCDCGA) 26 includes a dedicated register group 201, a system bus (ISA BUS) 1
ISA-BUS interface logic 202, keyboard interface bus (KBC B
US) 13 coupled to a KBC-BUS interface logic 203, a power supply interface bus (PSC).
BUS) 14 coupled to the PSC-BUS interface logic 204, and outputs the SMI signal to an AND gate G1.
And a status LCD interface logic 206 for controlling the status LCD 44.

The dedicated register group 201 is composed of 48 8-bit registers, and includes a register group for communication with the keyboard controller (KBC) 30, a register group for communication with the power supply controller (PSC) 46, and a register for the status LCD 44. A display control register group is included. Different addresses are assigned to these registers.

The ISA-BUS interface logic 202 manages an interface with the system bus (ISA-BUS) 11, and performs read / write control of the dedicated register group 201 in response to a request from the CPU 21. CPU 2 via system bus 11
1, an address enable signal (AEN) supplied from
Address signal (SA), I / O read signal (IOR
D), an I / O write signal (IOWR), and 8-bit data in a system data bus (SD). In this case, which register is accessed is determined by decoding the address signal (SA).

The KBC-BUS interface logic 203 reads / writes the dedicated register group 201 in response to a request from the keyboard controller (KBC) 30, and controls the keyboard interface bus (K
The read / write signal R / supplied from the keyboard controller (KBC) 30 via the BC BUS 13
W #, a strobe signal (STROB #), and an address / data on an 8-bit KBC data line (KBS-DATA) in the keyboard interface bus (KBC BUS) 13 are used. Further, the KBC-BUS interface logic 203 is connected to a predetermined bit position of a predetermined register used for communication with the keyboard controller (KBC) 30, and data “1” set by the CPU 21 in the bit position. , A request signal (REQUEST) is output to the keyboard controller (KBC) 30. The request signal (REQUEST) is used to read the data content of the register set by the CPU 21 into the keyboard controller (KBC) 30. The actual communication procedure between the keyboard controller (KBC) 30 and the status LCD control gate array (SLDCGA) 26 using such interface signals will be described later with reference to FIGS.

The PSC-BUS interface logic 204 controls the power supply interface bus (PSC BU) to read / write the dedicated registers 201 in response to a request from the power supply controller (PSC) 46.
S) Read / write signal (R / W #), strobe signal (STROB #), and 8-bit PSC data in power supply interface bus (PSC BUS) 14 supplied from power supply controller (PSC) 46 via S) 14 The address / data on the line (PSC-DATA) is used. Further, the PSC-BUS interface logic 204 is connected to a predetermined bit position of a predetermined register used for communication with the power supply controller (PSC) 46, and data “1” set by the CPU 21 in the bit position. Power controller (P
SC) 46 to output a request signal (REQUEST). An actual communication procedure between the power supply controller (PSC) 46 and the status LCD control gate array (SLDCGA) 26 using such an interface signal will be described later with reference to FIGS.

The SMI signal output logic 205 is a bit of the SMI transmission register 102 provided in a register group for communication with the keyboard controller (KBC) 30.
7, and the SMI transmission register bi provided in the register group for communication with the power supply controller (PSC) 46
The low-level SMI signal is generated when one is set to "1". This SMI signal is supplied to the SMI input of the CPU 21 via the AND gate G1.

The status LCD interface logic 206 operates according to the contents of the display control register group provided in the dedicated register group 201.
The status LCD 44 is controlled by a combination of five common signals and twelve segment signals. In this case, status L
Lighting / extinguishing of the number segments and icons in each display area of the CD 44 is determined by the contents (“1” / “0”) of the display control data set in the corresponding register. The display control data is set in the display control register group by the CPU 21 and the keyboard controller (KBC) 3.
0 and a power supply controller (PSC) 46 respectively. The display control data set by the CPU 21 includes a water icon in the display area R3 of the status LCD 44, a book icon in the display area R4,
Hard disk icon in display area R5, display area R6
Of the floppy disk icon and the mail icon in the display area R7. The display control data set by the keyboard controller (KBC) 30 includes the display areas R8 to R8 of the status LCD 44.
R11 is instructed to turn on / off each icon. The display control data set by the power supply controller (PSC) 46 instructs turning on / off of a three-digit number segment in the display area R1 and a power icon in the display area R2.

Next, a communication procedure between the keyboard controller (KBC) 30 and the status LCD control gate array (SLDCGA) 26 using the keyboard interface bus (KBCBUS) 13 will be described with reference to FIGS. .

FIG. 5 shows a keyboard controller (KB)
C) 30 and status LCD control gate array (SLC
The interface between the DC GAs 26 is shown. As shown, the keyboard interface bus (KBC BUS) 13 has eight KBC data lines (K
BC-DATA) 131, read / write signal (R / W)
￣) line 132, strobe signal (STROB￣) line 13
3, and the request signal (REQUEST) line 134
And 11 lines in total. In this case, eight KBC data lines (KBC-DATA) 131
Is also used to send the address. As the KBC data lines (KBC-DATA) 131, eight out of 11 scan lines are used.

That is, the keyboard controller (KB
C) The scanout I / O port 30 is connected to eleven scan lines for transmitting a scan signal for scanning the key matrix of the keyboard 51 to the keyboard 51, and a keyboard controller (KBC). 8) Return lines for receiving return signals from the keyboard 51 are connected to the 30 scan-in I / O ports. Eight of the 11 scan-out I / O ports are also connected to the KBC data line (KBC-DATA) 131, and the status LCD control gate array (SLCDC GA) 2
6 for data transmission and reception. in this case,
Status LCD control gate array (SLCDCG)
A) During the data transmission / reception with 26, the signal on the return line is invalidated by the control logic in the keyboard controller (KBC) 30, and the conversion to the scan code is not executed.

As described above, in this embodiment, eight of the eleven scan lines are used as the data lines of the keyboard interface bus (KBC BUS) 13 so that the I / O of the keyboard controller (KBC) 30 is performed. The number of ports is being reduced. Further, as described above, the scan line and the KBC data line (KBC-DATA)
By adopting a configuration in which the I / O port is shared with the 131, the existing keyboard controller chip can be used only by changing the program.

FIG. 6 shows a keyboard controller (KB)
C) 30 is a status LCD control gate array (SLC)
A timing chart when data is written to the register of the DC GA) 26 is shown.

As shown in the figure, the keyboard controller (KBC) 30 normally sends a scan signal to the keyboard 5.
1 except during the period of communication with the status LCD control gate array (SLLCD GA) 26.
A scan signal is transmitted on the KBC data line (KBC-DATA) 131. When writing data to the register of the status LCD control gate array (SLLCD GA) 26, first, the keyboard controller (K
BC) 30 to KBC data line (KBC-DATA) 1
The address designating the register is output on the address 31 and then the write data is transferred to the KBC data line (KBC-DAT).
A) Output on 131. While the address or the data is being output, the return signal from the keyboard 51 is invalidated. Also, a read / write signal (R / W￣) from the keyboard controller (KBC) 30
Are maintained at a low level.

When the strobe signal (STROB #) from the keyboard controller (KBC) 30 falls,
The address on the KBC data line (KBC-DATA) 131 corresponds to the status LCD control gate array (SLCDC).
GA) 26, and the register specified by that address is selected. Then, the strobe signal (STR)
OB #) rises and the KBC data line (K
The data on the (BC-DATA) 131 is written to the selected register.

By such a write operation, for example,
Writing of hot key data to the Fn status register 101 and data writing to the SMI transmission register 102 are executed.

FIG. 7 shows a keyboard controller (KB)
C) 30 is a status LCD control gate array (SLC)
A timing chart when data is read from the register of the DC GA) 26 is shown.

Status LCD control gate array (SL
When reading data from the register of the CDC GA) 26, first, the keyboard controller (KBC) 3
From 0, an address designating a register is output on the KBC data line (KBC-DATA) 131. The strobe signal (S) from the keyboard controller (KBC) 30
TROB #) falls, the KBC data line (KBC
-DATA) 131 is taken into the status LCD control gate array (SLLCD GA) 26. When the read / write signal (R / W #) from the keyboard controller (KBC) 30 changes from low to high, a read operation of the register specified by the address is executed, and the status LCD control gate array (SLCDC GA) ) 26 outputs read data to the KBC data line (KBC-DATA) 131. Then, this KBC data line (KBC-DAT
A) When the read data on 131 is taken into the keyboard controller (KBC) 30, the read / write signal (R / W #) returns to low level, and the read operation ends.

Such a read operation is performed, for example, by the CPU 2
This is executed when the control information from No. 1 is transmitted to the keyboard controller (KBC) 30 as a command. In this case, the read operation is executed in response to a request signal (REQUEST) from the status LCD control gate array (SLLCD GA) 26.

Status LCD control gate array (SL
Keyboard controller (KB)
C) Since a plurality of registers for data communication with 30 are prepared, once the control information is set in these registers by the CPU 21, the above-mentioned read operation is repeatedly executed to continuously execute the plurality of control information. The keyboard controller (KBC) 30 can read the information. In this case, only a dedicated keyboard interface bus (KBC BUS) 13 is used for communication between the status LCD control gate array (SLCDC GA) 26 and the keyboard controller (KBC) 30, and the system bus (ISA BUS) 11 is not used. Therefore, much control information can be passed to the keyboard controller (KBC) 30 without affecting the performance of the entire system.

The control information transmitted from the CPU 21 to the keyboard controller (KBC) 30 includes, for example,
When the external keyboard 53 is used, there is hot key definition information for assigning a specific key on the external keyboard 53 as a hot key. That is, when the internal keyboard 51 is used, the hot key is defined as “Fn + any key”, but the external keyboard 53 displays [Fn + any key].
Since there is no special key such as the [n] key, it is necessary to substitute some key combinations on the external keyboard 53 for the [Fn] key. In this case, key patterns of some keys are transmitted from the CPU 21 to the keyboard controller (KBC) 3 as the hot key definition information.
Sent to 0. Keyboard controller (KBC) 3
The transmission of the hot key definition information to 0 is performed, for example, in an initialization routine executed by the CPU 21 when the power switch of the computer is turned on. The details of the process of transmitting the hot key definition information to the keyboard controller (KBC) 30 will be described later with reference to FIG.

Next, a communication procedure between the power supply controller (PSC) 46 and the status LCD control gate array (SLCDC GA) 26 using the power supply interface bus (PSC BUS) 14 will be described with reference to FIGS. I do.

FIG. 8 shows a power supply controller (PSC) 3
0 and status LCD control gate array (SLCDC
The interface between GA 26 is shown. As shown, the power supply interface bus (PSC BU)
S) 14 has eight PSC data lines (PSC-DAT).
A) 141, read / write signal (R / W￣) line 14
2, a total of 11 lines including a strobe signal (STROB #) line 143 and a request signal (REQUEST) line 144. In this case, the eight PSC data lines (PSC-DATA) 141 are shared for transmitting and receiving data and addresses.

FIG. 9 shows a power supply controller (KBC) 4
6 is a status LCD control gate array (SLCDC)
A timing chart when data is written to the register GA) 26 is shown.

As shown, when data is written to the register of the status LCD control gate array (SLLCD GA) 26, the power supply controller (PSC) 4
6 outputs an address designating a register on the PSC data line (PSC-DATA) 141, and then writes the write data to the PSC data line (PSC-DATA) 14
1 is output. Power supply controller (PSC)
The read / write signal (R / W #) from 46 is maintained at a low level.

When a strobe signal (STROB #) from power supply controller (PSC) 46 falls, PSC
The address on the data line (PSC-DATA) 141 is the status LCD control gate array (SLDC GA)
26, and the register specified by the address is selected. Then, a strobe signal (STROB)
￣) rises and the PSC data line (PSC data at that time)
-DATA) 141 is written to the selected register.

By such a write operation, for example,
Writing of ON / OFF detection information of the power switch, ON / OFF detection information of the AC adapter, detection information of the low battery state, and the like are executed.

FIG. 10 shows a power supply controller (PSC).
46 is a status LCD control gate array (SLCDC).
A timing chart when data is read from the register GA) 26 is shown.

Status LCD control gate array (SL
When data is read from the register of the CDC GA) 26, first, the power supply controller (PSC) 30 outputs an address specifying the register to the PSC data line (PSC-DATA) 141. Strobe signal (STROB #) from power supply controller (PSC) 46
Falls, the PSC data line (PSC-DATA)
The address on 141 is taken into the status LCD control gate array (SLLCD GA) 26. And
When the read / write signal (R / W #) from the power supply controller (PSC) 46 changes from low to high level,
The read operation of the register specified by the address is executed, and the status LCD control gate array (SLCD)
CGA) 26 to the PSC data line (PSC-DAT)
A) Read data is output on 141. Then, the read data on the PSC data line (PSC-DATA) 141 is taken into the power supply controller (PSC) 46, and the read operation is terminated when the read / write signal (R / W #) returns to a low level. .

Such a read operation is performed, for example, by the CPU 2
1 is transmitted to the power supply controller (PSC) 46 as a command. In this case, the read operation is executed in response to a request signal (REQUEST) from the status LCD control gate array (SLLCD GA) 26.

Status LCD control gate array (SL
The power supply controller (PSC) 4
6, a plurality of data communication registers are prepared, and once the control information is set in these registers by the CPU 21, the above-described read operation is repeatedly executed to continuously store the plurality of control information. The power controller (PSC) 30 can read. In this case, the status LCD control gate array (SLLCD GA) 26 and the power supply controller (PS
C) Only a dedicated power supply interface bus (PSC BUS) 14 is used for communication with 46 and the system bus (ISA BUS) 11 is not used, so that much control information can be transferred without affecting the performance of the entire system. It can be passed to a power supply controller (PSC) 46.

Next, an example of the specific configuration of the keyboard controller (KBC) 30 will be described with reference to FIGS.

FIG. 11 shows a keyboard controller (KB)
C) shows how signals are allocated to a plurality of I / O ports of 30. FIGS. 12 and 13 illustrate the functions of signals transmitted and received by these I / O ports.

Keyboard controller (KBC) 30
Is composed of a one-chip microcomputer including a CPU, a ROM, a RAM, and a plurality of I / O ports. As shown in FIG. 11, these I / O ports are connected to a system bus (ISA BUS) 11. , Status LCD
As shown in FIG. 12 and FIG. 13, they are allocated to interfaces with the control gate array (SLLCD GA) 26, the internal keyboard 51, the mouse 52, the external keyboard 53, and the numeric keypad 54, respectively.

That is, as can be seen from FIGS. 12 and 13, the interface with the system bus (ISA BUS) 11 has eight ports DB0 to DB7, a reset signal input terminal (R), and an I / O write port. Signal input terminal (W
R), I / O read signal input terminal (RE), chip select signal input terminal (CS), lower 3 of system address signal
The address input terminal (C / D) to which the bit (SA02) is input and the clock input terminals (X1, X2) are used. The eight ports DB0 to DB7 are provided with an 8-bit register in the keyboard controller (KBC) 30 and a CP.
It is for transmitting and receiving data to and from the U21, and is connected to the lower 8 bits (SD7-0) of the 16-bit data bus of the system bus (ISA BUS) 11.

The interfaces with the internal keyboard 51 include ports P00 to P07, P30 to P32, and P40.
To P47 are used. Of these, ports P00 to P0
7, P30 to P32 are respectively connected to the 11 scan lines of the internal keyboard 51, and the ports P40 to P4
7 is connected to eight return lines of the internal keyboard 51. Ports P00-P connected to scan lines
07, P30 to P32, eight ports P00 to P0
7 is a status LCD control gate array (SL
The ports P00 to P07 are also connected to the 8-bit data line of the keyboard interface bus (KBC BUS) 13 as described with reference to FIG. As an interface with the status LCD control gate array (SLLCD GA) 26, ports P60 to P62 are used in addition to the ports P00 to P07. Port P60, P61
Is a status LCD control gate array (SLCDC).
GA) 26 for transmitting a read / write signal (R / W #) and a strobe signal (STROB #), and P62 receives a request signal from the status LCD control gate array (SLCDC GA) 26. It is for. Ports P26 and P27 are used as an interface with the external keyboard 53. These ports P26 and P27 are connected to an external keyboard 5
3 for transmitting and receiving data and a clock to and from the scan code controller built in the CPU 3.

As described above, the keyboard controller (K
The BC) 30 has two types of ports for communicating with the CPU 21. One is the system bus (ISA B)
US) 11 and a port for communicating with the CPU 21 via the keyboard interface bus (KBC BUS) 13 and the status LCD control gate array (SLCDC GA) 26.
1 is a port for communicating with

In this case, the system bus (ISA BU)
S) A port for communicating with the CPU 21 via the port 11 is used to transmit and receive existing commands related to keyboard control and the like necessary for execution of application programs and the like in order to maintain compatibility with conventional systems. Used for normal key data transmission for passing data to application programs and the like. On the other hand, a port for communicating with the CPU 21 via the keyboard interface bus (KBCBUS) 13 and the status LCD control gate array (SDLCD GA) 26 is provided with an extended function provided in this computer, that is, a hot key processing and a security function. It is used exclusively for transmitting and receiving commands related to execution and for transmitting key data of the hot key.

As described above, the keyboard controller (K
The BC) 30 is configured to transmit and receive an existing command used by an application program or the like and another command added according to the function extension via different command path routes. Even if execution of a special function is requested while a command from an application program is set in an I / O register for communication with the system bus in the (KBC) 30, the contents of the I / O register are temporarily saved. A command for executing a requested special function can be transmitted and received without performing a process such as performing a special function.
Therefore, while maintaining compatibility with legacy systems,
Moreover, the extended function can be efficiently executed without affecting the execution of the application program.

FIG. 14 shows a keyboard controller (K
The flowchart of the key data transmission process by the BC) 30 is shown.

At the time of transmitting key data, the keyboard controller (KBC) 30 determines whether or not the pressed key of the internal keyboard 51 is a hot key (Fn + another key) (step S11). This determination is made by comparing the scan code corresponding to the pressed key with the scan code of the Fn key, and examining whether there is a match.

When the pressed key is a hot key, the keyboard controller (KBC) 30 sends the status LCD control gate array (SLDC GA) 26 from the ports P 00 to P 07 connected to the keyboard interface bus (KBC BUS) 13. The key data is transmitted (step S12). In this case, the transmitted key data is the scan code of the key pressed at the same time as the Fn key (make code during the pressed period / break code when released), and this scan code is the status L.
Fn of CD control gate array (SLCDC GA) 26
It is set in the status register 101. Also, in step S12 of this key data transmission, the keyboard controller (KBC) 30 sends the status LCD control gate array (SL) so that the SMI signal is issued.
Bi of the SMI transmission register 102 of the CDC GA) 26
"1" is set to t7.

On the other hand, when the pressed key is other than the hot key, the keyboard controller (KBC) 30
Transmits key data from the ports DB0 to DB7 connected to the system bus (ISA BUS) 11 (step S13). In this key data transmission process, first, the key data is set in a register provided in the keyboard controller (KBC) 30 for communication with the system bus (ISA BUS) 11, and the key input interrupt signal IRQ 1 Is generated.
The key input interrupt signal IRQ1 is supplied to the CPU 21 via the I / O controller 21 as a maskable interrupt.

FIG. 15 shows a keyboard controller (K
BC) 30 shows a flowchart of a command process.

The command processing functions of the keyboard controller (KBC) 30 are broadly classified into the existing command processing functions released to the application programs and the like as described above, and the other extended command processing functions. . The existing command processing function is for normal key input control such as control of the repeat speed, for example.
The extended command processing function is for realizing a hot key function and a security function. In the extended command process, for example, a password verification process at the time of power-on, a password verification process in instant security, and a registration process of hot key definition information for an external keyboard are performed.

An existing command processing function for normal key input control and the like is provided by a system bus (ISA BUS) 11.
CPU through ports DB0 to DB7 connected to
21 is executed in response to a command received from the system bus (ISA BUS) 1.
1 is notified to the CPU 21. Extended command processing functions such as password verification processing and hot key definition information registration processing are provided by the keyboard interface bus (KBC
BUS) 13 connected to ports P00 to P07
The command is executed in response to a command received from the CPU 21 through the keyboard interface bus (KBC BUS) 13.
1 is notified.

As described above, the normal command processing and the extended command processing differ not only in the functions executed by the processing but also in the processing format of command reception and processing result notification. Therefore, the keyboard controller (KBC) 3
Command processing by 0 is executed as follows.

That is, the keyboard controller (KB)
C) 30 determines whether the command is supplied via the system bus (ISABUS) 11 or a command supplied via the keyboard interface bus (KBC BUS) 13. This determination is made by detecting which of the I / O write signal (IOWR) supplied to the port WR and the request signal supplied to the port P62 is enabled (step S2).
1, S22).

When the I / O write signal (IOWR) is enabled, since the command supplied at that time is supplied via the system bus (ISA BUS) 11, the sequence is composed of steps S23 to S25. A routine for normal processing is executed. In this case, the keyboard controller (KBC) 30 is connected to the port DB0 connected to the system bus (ISA BUS) 11.
To receive a command from DB7 (step S23).
Next, in accordance with the command, the keyboard controller (KBC) 30 performs command processing for normal key input control including control of a repeat speed required from an application program or the like (step S24). When the command processing is completed, the keyboard controller (KBC) 30 sets a processing result and data indicating the processing end in an I / O register for communication with the system bus (ISA BUS) 11, and sets it in the port D
B0 to DB7 to the CPU 21 (step S2
5).

On the other hand, a request signal (REQUEST)
Is enabled, the command supplied at that time is the keyboard interface bus (KBC BU).
S), the routine for the expansion process composed of steps S26 to S28 is executed. In this case, the keyboard controller (KBC) 30 is connected to the port P00 connected to the keyboard interface bus (KBC BUS) 13.
ＰP07 are received (step S26).
This receiving process is performed by the keyboard controller (KBC) 3
0 is a status LCD control gate array (SLCDCGA) 26 in response to a request signal (REQUEST).
This is performed by reading a predetermined register in the memory. Next, according to the command, the keyboard controller (KBC) 30 performs an extended command process (step S27). When the command processing ends, the keyboard controller (KBC) 30 sends the port P00 to the port P00 to notify the CPU 21 of the processing result or the processing end.
P07 to status LCD control gate array (SLC
The data indicating the processing result or the processing end is written to a predetermined register of the DC GA) 26 (step S28).

As described above, the keyboard controller (K
The BC) 30 receives a command for the extension processing and transmits a processing result of the processing by a system bus (ISA BU).
S) is performed using the keyboard interface bus (KBC BUS) 13 instead of S11. Therefore, hot key processing and other extended processing can be performed using the keyboard controller (KBC) 30 without increasing the occupation time of the system bus (ISA BUS) 11, thereby improving the performance of the entire computer system. Can be achieved.

Here, as an example of the extended command processing,
The hot key definition information registration processing will be described.

That is, the external keyboard 53 outputs [F
Since there is no [n] key, it is necessary to realize a hot key function by a combination of keys. However, if a hot key is assigned to a specific key of the external keyboard 53, the key assignment may be duplicated depending on the application program to be executed. The user is allowed to freely select with up to three key combinations. This hot key pattern is specified, for example, by activating a setup program. The specified key pattern is stored in the CMOS memory of the real-time clock (RTC) in the I / O controller 22 described with reference to FIG. You.

The CPU 21 executes initialization of various controllers in accordance with the system configuration information of the CMOS memory in an initialization routine executed when the power switch is turned on. When the keyboard controller (KBC) 30 is initialized, the hot key definition information registration processing command and the key pattern of the hot key stored in the CMOS memory are transmitted from the CPU 21 to the register of the status LCD control gate array (SLLCD GA) 26. Are set respectively. Then, a request signal (REQU) is sent from the status LCD control gate array (SLCDC GA) 26 to the keyboard controller (KBC) 30.
EST) is sent.

Keyboard controller (KBC) 30
Is a status LCD control gate array (SLDC GA) 2 in response to a request signal (REQUEST).
6 is read, and if the read data is a hot key definition information registration processing command, the status LCD control gate array (SLLCD GA) 2
The key pattern of the hot key is read from the register No. 6 and registered in the internal RAM or the like. In this manner, the key pattern of the hot key specified by the user is registered in the keyboard controller (KBC) 30 as hot key definition information.

The key pattern of the hot key is used only when the external keyboard 53 is used.
At the time of use, the Fn key is used. External keyboard 53
Is attached to the computer main body as needed by the user as described above, and the presence or absence of the attachment is detected by the keyboard controller (KBC) 30 at the time of initial setting. This detection processing is performed, for example, by setting the clock to the ports P26 and P27 to which the external keyboard 53 is connected.
It is possible to transmit the data and check whether there is a response from the external keyboard 53 to the data or to check a voltage drop of a connector to which the external keyboard 53 is attached, using a known technique.

When the power switch is turned on with the external keyboard 53 mounted, the external keyboard 53
Only key input from the internal keyboard 5
Key input from 1 is invalidated.

Therefore, the keyboard controller (K
The actual key data transmission processing by the BC) 30 is shown in FIG.
become that way.

That is, when transmitting key data,
First, the keyboard controller (KBC) 30 checks whether or not the external keyboard 53 is attached (step S3).
1). This can be performed, for example, by referring to the presence / absence information of the external keyboard 53 detected at the time of the initial setting. When the external keyboard 53 is not attached, the scan code corresponding to the pressed key is compared with the scan code of the Fn key, as in the case described with reference to FIG.
It is determined whether it is another key) (step S32). When the pressed key is a hot key, the keyboard controller (KBC) 30 sends a key from the ports P00 to P07 connected to the keyboard interface bus (KBC BUS) 13 to the status LCD control gate array (SLLCD GA) 26. The data is transmitted (step S34). When the pressed key is other than the hot key, the keyboard controller (KB
C) 30 transmits key data from the ports DB0 to DB7 connected to the system bus (ISA BUS) 11 (step S35).

On the other hand, when the external keyboard 53 is mounted, the scan code corresponding to the pressed key is compared with the scan code of the hot key pattern registered at the time of the initial setting. It is determined whether it is a hot key pattern + another key) (step S33). If the pressed key is a hot key, the process of step S34 is executed. If the pressed key is any key other than the hot key, the process of step S35 is executed.

Here, an example of a specific key data transmission process when the external keyboard 53 is attached will be described. Here, for example, the hot key pattern has two keys, [C
[Ctrl] key and [Alt] key are sequentially pressed when defined by [trl] key + [Alt] key,
It is assumed that the [F1] key is pressed while these keys are being pressed. In this case, the keyboard controller (K
BC) 30 transmits the key data as follows.

(1) The scan code of the [Ctrl] key is transmitted from the ports DB0 to DB7 connected to the system bus (ISABUS) 11 as usual.

(2) When the [Alt] key is pressed, a hot key state is established, so that the scan code of the [Alt] key is not transmitted. At this time, [Ct
rl] key to the system bus (ISA
BUS) 11 from the ports DB0 to DB7.

(3) When the next [F1] key is pressed,
Keyboard interface bus (KBC BUS) 1
The scan code of the [F1] key is transmitted from the ports P00 to P07 connected to 3 to the status LCD control gate array (SLLCD GA) 26, and the CPU 21 is notified of the input of the hot key by the SMI.

Next, hockey processing executed by the power supply controller (PSC) 46 will be described.

The power supply controller (PSC) 46 has a status LCD control gate array (SLDC GA) 2
6 is transmitted and received to and from the CPU 21 using the register of the status LCD control gate array (SL).
In accordance with the hot key data set in the Fn status register 101 of the CDC GA) 26, speaker volume adjustment and brightness / contrast adjustment of the LCD panel 49 are performed.

FIG. 17 shows an example of a hardware circuit for adjusting the speaker volume.

The function of adjusting the speaker volume is performed by a hot key operation of the [Fn] key + [F4] key. Each time the hot key operation is performed, “small volume” and “medium volume” are set. , "Loud volume" and "Off" are rotated, and at the same time a beep sounds. In this case, the beep sound is [Fn] key + [F
4] It is controlled so as to sound continuously while the hot key of the key is pressed.

Such a function is provided by the power controller (P
SC) 46 and hardware logic as shown. That is, the driving circuit 61 of the speaker 60
Has two ports A and B, and four kinds of speaker power supply voltages (SPK VCC) are selectively supplied to the port A from a power supply controller (PSC) 46.
These four types of speaker power supply voltage (SPK VCC)
This corresponds to four states of "low volume", "medium volume", "high volume", and "off". Further, a pulse signal for generating a beep sound is supplied from the speaker 60 to the port B of the drive circuit 61. This pulse signal is PCM
It is generated by an AND gate 62 and an OR gate 63 provided in the CIA gate array (PCMCIA GA) 28.

One input of AND gate 62 has an I / O
A clock signal having a beep frequency is supplied from a timer of the controller 22, and an OR gate 6 is connected to the other input.
3 outputs are provided. One input of the OR gate 63 is supplied with a speaker ON signal from a power supply controller (PSC) 46, and the other input is supplied with an alarm signal for notifying various abnormal states. This alarm signal
For example, this occurs when the LCD panel 49 is closed or the AC adapter is disconnected while the power is on.

The power supply controller (PSC) 46 is
The status register 101 is read periodically, and [F
4] The speaker ON signal is set to "1" when a key scan code (make code) is received, and the speaker ON signal is reset to "0" when a break code is received. The power supply controller (PSC) 46
Four types of speaker power supply voltages (SPK) corresponding to four states of “low volume”, “medium volume”, “high volume”, and “off”
VCC). This rotation is executed every time a scan code (make code) of the [F4] key is received.

Next, the operation of switching the speaker volume by the hot key will be described with reference to the timing chart of FIG.

[Fn] key on the internal keyboard 51 +
When the [F4] key is pressed, the scan code (make code) of the [F4] key is set in the Fn status register 101 of the status LCD control gate array (SLLCD GA) 26. Power supply controller (PS
C) 46 periodically reads the Fn status register 101 by polling. If the read content is the scan code (make code) of the [F4] key, the speaker ON signal is set to “1”. set.
The power supply controller (PSC) 46 rotates the current state of the speaker power supply voltage (SPK VCC) by one step. For example, if the current speaker power supply voltage (SPK VCC) corresponds to “low volume”, the speaker power supply voltage (SPK VCC) is switched to a value corresponding to “medium volume”. This causes the speaker 60 to emit a beep sound corresponding to “medium volume”. Thereafter, when the [F4] key is released, the status L
Fn of CD control gate array (SLCDC GA) 26
The break code of the [F4] key is set in the status register 101, and this is the power supply controller (PSC).
Leaded by 46. When the break code of the [F4] key is read, the status LCD control gate array (SLLCD GA) 26 resets the speaker ON signal to “0”. As a result, the generation of the "medium volume" beep sound from the speaker 60 is stopped.

In this state, the [Fn] key +
When the [F4] key is pressed, the speaker power supply voltage (SPK VCC) is switched from a value corresponding to "medium volume" to a value corresponding to "high volume". Until the [F4] key is released, a "high volume" beep sound is continuously output. Thereafter, when the [Fn] key + [F4] key is pressed again, the speaker power supply voltage (S
PK VCC) is switched from a value corresponding to “loud volume” to a value corresponding to “off” (power supply is stopped). In this case, no beep is emitted from the speaker 60.

As described above, in the function of switching the speaker volume by the hot key processing, the [Fn] key +
A beep sound is emitted continuously while the [F4] key is pressed. For this reason, the user can press the [Fn] key +
The beep sound generation period can be arbitrarily adjusted by the user himself / herself according to the time during which the [F4] key is kept pressed.

As described above, in the portable computer of this embodiment, the system bus (ISA BU)
A dedicated register group for communication with a keyboard controller (KBC) 30 is provided in a status LCD control gate array (SLCD GA) 26 connected to the S) 11, and the dedicated register group and the keyboard controller (KBC) 30 are provided. Are connected via a dedicated keyboard interface bus (KBC BUS) 13. Therefore, the CPU 21 reads / writes a dedicated register group of the status LCD control gate array (SLCD GA) 26 via the system bus 11, and the keyboard controller (KBC) 30 uses the keyboard interface bus (KBC BUS) 13 By reading / writing the register group, transmission / reception of various control information such as commands between the CPU 21 and the keyboard controller (KBC) 30 is executed.

In this case, in the transfer from the CPU 21 to the keyboard controller (KBC) 30, the CPU 2
1 is writing control information to a group of registers via the system bus 11 while the keyboard controller (KB
C) 30 can execute other processing, and when the control information is written to the register group, a request signal is transmitted from the status LCD control gate array (SLDC GA) 26 to the keyboard controller (KBC) 30. , And thereafter, the status LCD control gate array (S
LCDC GA) 26 and keyboard controller (KB)
C) Communication is performed between 30. During this period, CPU2
1 and the system bus 11 are released from the transfer of the control information. Similarly, a keyboard controller (KBC)
Also in the transfer from the CPU 30 to the CPU 21, while the keyboard controller (KBC) 30 is writing control information to the register group via the keyboard interface bus (KBC BUS) 13, the CPU 21 and the system bus 11 use the control information. When the control information is written into the register group, an SMI signal is transmitted from the status LCD control gate array (SLCDC GA) 26 to the CPU 21, and thereafter, the status LCD control gate array (SLCDCGA) 26 And communication between the CPU 21 and the CPU 21. During this period, the keyboard controller (KBC) 30 is released from transferring the control information.

Therefore, even if the number of data transfers between the CPU 21 and the keyboard controller (KBC) 30 is increased, the system bus 11 or C
Since the increase in the time in which the PU 21 is occupied is small, the keyboard controller (KBC) 30 can be provided with a special function related to a function expansion of the system, such as a hot key or security, without deteriorating the system performance.

The CPU 21 and the power supply controller (P
The communication of control information between the SC (SC) 46 and the dedicated register group for communication with the power supply controller (PSC) 46 provided in the status LCD control gate array (SDLCD GA) 26 is also performed by the CPU 21 via the system bus 21. Write and write the registers to the power controller (PS
C) 46 is a power supply interface bus (PSC BU)
S) It is realized by reading / writing via (14). Therefore, communication between the CPU 21 and the power supply controller (PSC) 46 can also be performed efficiently.

Further, in this embodiment, the keyboard controller (KBC) 30 has two types of ports for communicating with the CPU 21. One is a port for communicating with the CPU 21 via the system bus (ISA BUS) 11, and the other is a keyboard interface bus (KBC BUS) 13 and a status LCD control gate array (SLCDC GA) 2.
6 is a port for communicating with the CPU 21 via the CPU 6.
In this case, a port for communicating with the CPU 21 via the system bus (ISA BUS) 11 has an existing port related to keyboard control and the like necessary for executing an application program and the like in order to maintain compatibility with a conventional system. Command transmission and transmission of key data for passing data to an application program or the like. On the other hand, via the keyboard interface bus (KBC BUS) 13 and the status LCD control gate array (SLCDC GA) 26, the CPU 2
A port for communicating with the server 1 is used exclusively for an extended function provided in the computer, that is, for sending and receiving commands related to execution of hot key processing and security functions, and for transmitting key data of the hot key.

As described above, the keyboard controller (K
The BC) 30 is configured to transmit and receive an existing command used by an application program or the like and another command added according to the function extension via different command path routes. Even if execution of a special function is requested while a command from an application program is set in an I / O register for communication with the system bus in the (KBC) 30, the contents of the I / O register are temporarily saved. A command for executing a requested special function can be transmitted and received without performing a process such as performing a special function.
Therefore, while maintaining compatibility with legacy systems,
Moreover, the extended function can be efficiently executed without affecting the execution of the application program.

In this embodiment, the control information is transmitted to the CPU 21 by using the SMI signal. However, when a CPU having no interrupt such as the SMI is used,
NMI can be used instead of SMI.

[0145]

As described in detail above, according to the present invention,
Even if the number of transfers of control information between the CPU and the peripheral controller is increased due to the function expansion, the exclusive time of the system bus and the CPU due to the transfer can be reduced, so that the system function can be efficiently performed without lowering the system performance. Expansion can be achieved. In addition, since additional commands accompanying the function expansion and other existing commands used by the application program and the like are transferred through separate command path routes, compatibility with the conventional system is maintained, and The extension function can be executed without affecting the execution of the application program.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing the overall system configuration of a portable computer according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing an appearance of the portable computer of the embodiment and an example of a display screen of a status LCD provided in the portable computer.

FIG. 3 is a diagram showing a C in the portable computer according to the embodiment.
FIG. 3 is a diagram extracting and showing a hardware configuration related to communication between a PU and a keyboard controller, and communication between a CPU and a power supply controller.

FIG. 4 is an exemplary block diagram showing an example of a specific configuration of a status LCD control gate array provided in the portable computer of the embodiment.

FIG. 5 is an exemplary view showing a keyboard interface bus provided between a keyboard controller and a status LCD control gate array of the portable computer of the embodiment.

6 is a timing chart when a keyboard controller writes data to a register of a status LCD control gate array via the keyboard interface bus shown in FIG. 5;

7 is a timing chart when a keyboard controller reads data to a register of a status LCD control gate array via the keyboard interface bus shown in FIG. 5;

FIG. 8 is an exemplary view showing a power interface bus provided between a power controller and a status LCD control gate array of the portable computer of the embodiment.

9 is a timing chart when the power controller writes data to a register of the status LCD control gate array via the power interface bus shown in FIG. 8;

10 is a timing chart when a power controller reads data to a register of a status LCD control gate array via the power interface bus shown in FIG. 8;

FIG. 11 is an exemplary view showing a state of signal assignment of a plurality of I / O ports of a keyboard controller provided in the portable computer of the embodiment.

FIG. 12 is a first diagram showing functions of signals transmitted and received at each I / O port of the keyboard controller shown in FIG. 11;

13 is a second diagram showing functions of signals transmitted and received at each I / O port of the keyboard controller shown in FIG. 11;

FIG. 14 is a flowchart for explaining the key data transmission operation of the keyboard controller shown in FIG. 11;

FIG. 15 is a flowchart illustrating a command processing operation of the keyboard controller shown in FIG. 11;

FIG. 16 is a flowchart for explaining key data transmission operation when the external keyboard is used by the keyboard controller shown in FIG. 11;

FIG. 17 is an exemplary view showing an example of a hardware circuit for executing speaker volume switching required in hot key processing of the portable computer of the embodiment.

FIG. 18 is a timing chart illustrating the operation of switching the speaker volume by the circuit of FIG. 17;

[Explanation of symbols]

11: System bus, 12: Peripheral interface bus, 13: Keyboard interface bus, 14: Power supply interface bus, 21: CPU, 26: Status LCD control gate array, 30: Keyboard controller, 44: Status LCD, 46: Power supply controller, 51: internal keyboard, 53: external keyboard,
201: dedicated register group, 202: ISABUS interface logic, 203: KBC bus interface logic, 204: PSC bus interface logic, 205: SMI output logic, 206: status LCD interface logic.

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 13/10-13/14

Claims (7)

(57) [Claims] 1. A CPU, a memory, a system bus, and
Various peripherals connected to the CPU via the system bus
In a computer system having a controller, provided between the system bus and the peripheral controller.
Is transmitted and received between the CPU and the peripheral controller.
A dedicated register group in which various control information is temporarily set, and a dedicated register group provided between the dedicated register group and the peripheral controller.
Controller with multiple bit-width data lines defined
And the peripheral controller includes the controller bus and
First and second connected respectively to the system bus
And the first communication port and the
The CPU via a controller bus and a dedicated register group
And the first control information, and the second communication port,
And second control with the CPU via the system bus
Computer system for transmitting and receiving information
M 2. The peripheral controller includes a keyboard.
The key data corresponding to the pressed key is controlled by the CP.
It is a keyboard controller that sends to U
The computer system according to claim 1, wherein 3. The keyboard controller according to claim 2 , wherein
Scan to scan the keyboard key matrix
Scan output port to output scan signals and scan signals
Indicates the pressed key returned from the keyboard in response to
Scan input port for inputting return signal
And a part of the scan output port is connected to the first communication port.
The scan signal so that it can be used as
Scan lines to communicate to the
Connected to both of the roller buses, and when exchanging the first control information with the CPU,
Invalidates the return signal supplied to the scan input port
3. The apparatus according to claim 2, wherein:
Computer system as described. 4. The keyboard controller according to claim 1 , wherein:
Operating mode of the computer system in the data
For information on the key data of the hot key to set / change its
To the dedicated register group via the controller bus.
And write the other key data to the above register.
Transmission to the CPU via a stem bus.
3. The computer system according to claim 2, wherein: 5. A connection to a specific register of the dedicated register group.
And the registration is performed by the keyboard controller.
The CPU responds to predetermined data set in the
An interrupt signal supply unit for supplying an interrupt signal;
And the CPU is configured to execute the hot written in the dedicated register group.
Before executing the process according to the key data of the
In response to the interrupt signal,
Read key data of a key
Item 6. The computer system according to Item 4. 6. A special register of the dedicated register group is connected to a specific register.
Are set in the register by the CPU.
In response to predetermined data, the keyboard controller
Request signal supply means for supplying a request signal
And the keyboard controller is provided in the dedicated register group.
Before executing the process according to the written control information
Control from the dedicated registers in response to the request signal.
3. The method according to claim 2, wherein the control information is read.
Computer system. 7. Key data of the hot key is set.
Connected to a predetermined register of the dedicated register group
Turn off the volume of the speaker provided in the computer system.
When the hot key for specifying the replacement is pressed,
Switch the volume to the volume specified by the hotkey,
Switched while the hot key was pressed
A speaker volume control circuit that sounds the speaker at a volume
5. The computer according to claim 4, further comprising:
Data system.