JP3446366B2 - Board mounting position detection method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board newly mounted on a mother board in a device comprising a plurality of boards mounted on the mother board and connected via signal bus lines wired on the mother board. It relates to a method of detecting a position on a motherboard.

[0002]

2. Description of the Related Art FIG. 5 shows a device A as an example of a device composed of a plurality of boards connected via a signal bus on a mother board. In the device A shown in the figure, 1 is a motherboard made by wiring a signal bus bar on a printed wiring board, and Bj (j is a number, B0, B1, B2 are shown in the figure) are respectively A board (abbreviated as a board in the following description) which is a unit device including a circuit mounted on a printed wiring board for inputting / outputting a signal via a signal bus of the mother board 1 and processing data. The board Bj is connected to the motherboard 1 via removable connection terminals CN1j and CN2j. In the figure, the terminal CN10 on board B0
And CN20 are shown. The position where the board Bj is mounted is called a slot SLj (j is a number indicating the position of the slot on the motherboard 1, and the board mounted in the slot SLj is the board Bj having the number j in the slot SLj). When the board Bj is mounted on the mother board 1, the board Bj is mounted along the rail SLj provided in the slot SLj (the same reference numeral is used for the slot code and the rail code). In the figure, only rail SL0 in slot SL0 of board B0 is shown. The board Bj executes a program corresponding to the mounting position on the motherboard 1 by a control signal including a signal indicating the position on the motherboard 1 from a device mounting a main program (not shown). Therefore, motherboard 1
The position occupied by the board Bj above is an important condition for determining the function of the device A.

FIG. 6 shows a connection diagram between the mother board 1 and the board Bj of the device A shown in FIG. In the following description, the terminals, the signal lines connected to the terminals, and the signals transmitted by the signal lines are denoted by the same reference numerals.
In FIG. 6, 1 is a motherboard, Bj is a board, and CN1j
CN2j is a connection terminal and is the same as the one having the same reference numeral shown in FIG. The board Bj includes a control calculation unit, a program executed by the control calculation unit, a storage unit that stores data referred to by the control calculation unit when executing the program, data generated by the control calculation unit, a control calculation unit, and an external unit. The control calculation unit 21 including an input / output circuit that relays the signal of is mounted. The control calculation unit 21 uses the address / data terminal AD0,
AD1 ～, control signal terminal and terminal RDY which is one of control signal terminals are provided, and address / data terminals AD0, AD2 ～ are connected under the control of the signal via control bus CB to which the control signal terminal is connected. Input / output addresses and data with other boards via the address / data bus ADB. An address / data bus ADB and a control bus CB are wired on the mother board 1, and the address / data bus AD
B is connected to the board Bi via the connection terminal CN1i, and the control bus CB is connected to the board Bj via the connection terminal CN2j.

A slot position circuit CTj for detecting the position of the board Bj on the motherboard 1 is provided on the motherboard 1 at the position of the slot SLj in which the board Bj is mounted. In the figure, one of the slots SLj is a slot
SL1 slot position circuit CT1 is shown. The slot position circuit CTj represents the number of the slot SLj by a binary number 2
This is a circuit that generates the value signals S0, S1, S2. The signal value 0 is the voltage that refers to the negative electrode GND of the power supply of the control calculation unit 21, and the signal value 1 is the positive voltage Vcc of the control calculation unit 21. And the voltage. In the slot position circuit CT1, as shown in the figure, the value of the signal S0 is the voltage of the circuit connected to the positive electrode Vcc via the resistor R0, and therefore becomes 1 of the binary signal and the signals S1, S
Since the value of 2 is the value represented by the voltage directly connected to the negative GND, it becomes 0 of the binary signal. Therefore, the slot position circuit CT
The value represented by the signals S0, S1, S2 output by 1 is the binary number "001" with the signal S0 as the least significant digit, and this value is controlled by mounting the board Bj in the slot SL1 of the motherboard 1. After being input to and stored in the arithmetic unit, the board Bj becomes the board B1. Since the slot position circuit CTj is a circuit which gives the number of the slot SLj by the 3-bit binary signals S0, S1, S2, eight slots 0 to 7 can be identified. If the number of slots SLj increases to 8 or more,
To deal with this, increase the number of signals Sj.

FIG. 7 shows a timing chart of signals when the board Bj shown in FIG. 6 communicates with an external circuit.
In the figure, ADB represents a signal on the address / data bus ADB (see FIG. 6), and RDY represents a signal RDY transmitted by the control signal line RDY. The horizontal axis of the figure represents the passage of time, the vertical axis represents the magnitude of the binary signal, the lower line represents that the signal value is 0, and the upper line represents that the signal value is 1. When calling another board from the board Bj, first, the signal showing the address of the other party is sent to the address / data terminals AD0, AD.
Output from 1 to. In the following description, the period during which the address signal is output is referred to as the request phase QP. When the time set as the necessary and sufficient time for the reception of the address signal between the boards Bj has elapsed, the board Bj is in the request phase.
Ends QP, stops the output of the address signal, and waits for the signal from the partner board to be transmitted via the address / data bus ADB. In the board Bj waiting for transmission, the address / data terminals AD0, AD1 ... and the terminal RDY are in the state of signal input, so the signal values of the signal lines connected to these terminals are It is determined by the voltage of the terminal of the other board that outputs. The other board outputs the data to the address / data bus ADB, outputs the signal value 0 to the control signal terminal RDY at the same time, and is the time set as the time required to receive the data between the boards Bj. When is passed, signal RDY is set to 1. The board Bj finishes inputting data while the signal RDY is 0, and after the signal RDY becomes 1, the address / address for the next data communication
Clear the data bus ADB. In the following explanation, the response phase is defined as the range of the time when the data exists on the address / data bus ADB and the signal RDY changes from 0 to 1.
Notated as RP. As is clear from the above explanation, the signal RDY
Is a control signal for synchronization that indicates the output time point of the data given to the other party receiving the data by the data output source.

On the other hand, when the board Bj receives the address of the data mounted on the board Bj itself, the board Bj outputs the data of the received address from the terminals AD0 and AD1 in the response phase RP, and further outputs the signal value from the terminal RDY. 0 is output and the output from the terminal RDY is set to 1 at the end of the response phase. As explained above, between boards Bj or boards Bj
Data is sent and received between the receiver and other circuits by the request phase QP that calls the receiver and the response phase RP that outputs data according to the contents of the request phase QP.
The data bus ADB functions as an address bus for transmitting an address signal in the request phase QP and as a data bus for transmitting data in the response phase.

[0007]

As described above, in a device consisting of a plurality of boards connected via a mother board, when it is necessary to know the mounting position of the board on the mother board, the conventional method has been used. A method is provided in which a slot position circuit is provided at a position where each board is mounted, and when the board is mounted, a signal from the slot position circuit is read by the board to detect the position of the mounted board. However, according to this method, it is necessary to provide a slot position circuit corresponding to each slot, and the slot position circuit needs to increase the number of bits of the output signal according to the number of slots. For example, if the number of slots is 2, it is 1 bit, if the number of slots is 4, it is 2 bits,
Up to 8 slots must be 3 bits, and up to 16 slots must be 4 bits. Therefore, in a device with a large number of slots, it is necessary to increase both the number of slot position circuits and the number of signal lines for the purpose of only detecting the slot position on the board, resulting in a substantial reduction in packaging density.
Further, it is necessary to consider the decrease in reliability due to the increase in the number of connection terminals.

In view of the above circumstances, it is an object of the present invention to provide a board mounting position detecting method which requires only a small number of circuits as compared with the prior art.

[0009]

In order to achieve the above-mentioned object, in the invention of claim 1, a plurality of boards mounted on a mother board and connected via signal bus lines wired on the mother board are provided. In the method of detecting the mounting position, one end is connected to one of signal lines forming an address / data bus of a signal bus and the other end is a connection terminal at a position where each board is mounted on a motherboard. A board position line connected to the board mounted at this position is provided via, and each board position line is not connected to the same signal line, and the board outputs to the signal line via the board position line. It is characterized by detecting the mounting position of the board on the motherboard by inputting the signal.

According to the second aspect of the invention,
In a method of detecting the mounting positions of a plurality of boards mounted on a motherboard and connected via signal bus lines wired on the motherboard, one board is mounted at a position on the motherboard where each board is mounted. A board position line is provided in which the conductor wire is branched into n lines, and the signal lines forming signal bus lines are different from each other through a diode that passes a signal current in only one direction through the line end of the board position line that is branched into n lines. To the board mounted at this position via the connection terminal, and output from each board to the signal bus line via the board position line. It is characterized in that the wirings are such that the values obtained by decoding the value signals do not match.

In addition, in the board mounting position detecting method according to the first or second aspect, the board detects the time when the data on the signal line is input in synchronization with the signal output via the board position line. It is characterized in that a given control signal is output. Further, in the board mounting position detecting method according to any one of claims 1 to 3,
It is preferable that the board position line or the signal line is connected to a positive electrode of a power supply that supplies electric power having a voltage representing one value of the binary signal via a resistor.

In the board mounting position detecting method according to any one of claims 1 to 4,
When a signal that deviates from the range of the signal output from the board via the board position line is input to the board, it is preferable to perform processing when the board position detection is not normally performed. Furthermore, in the board mounting position detecting method according to any one of claims 1 to 5,
It is preferable that the signal output from the board via the board position line is one signal output when the board is mounted when power is supplied to the motherboard.

[0013]

In the invention of claim 1, the board position line is
At the position where each board is mounted on the motherboard, one end is connected to one of the signal lines that is different from the signal line to which the other board position lines are connected, and the other end is connected to this position via the connection terminal. Connect to the board installed in. Therefore,
The signal lines connected to the board position line differ from each other depending on the mounting position of the board.Therefore, when the board outputs a signal to the signal line via the board position line and reads this output data, it is input to the board. The signal that is output is a unique value that represents the mounting position of the board that output the signal.

Further, in the invention described in claim 2,
On the motherboard, at the position where the individual boards are mounted,
A board position line in which one conductor is branched into n is provided, and the signal lines forming the signal bus are mutually connected through a diode that passes a signal current only in one direction through a line end of the board position line branched into n. A binary value that is connected to different signal lines, the line end on the non-branching side is connected to the board mounted at this position via the connection terminal, and is output from each board to the signal bus line via the board position line. The wiring is such that the values obtained by decoding the signals do not match. Therefore, the decoded value of the signal output from the board via the board position line and read into the output board is a unique value representing the mounting position of the board that has output the signal.

Further, in the board mounting position detecting method according to claim 1 or 2, the board synchronizes the data on the address / data bus with the signal output via the board position line. By outputting a control signal that gives the time of input, the signal output via the board position line can be input. Further, in the invention according to claim 4, since the board position line or the signal line is connected to the positive electrode of the power supply for supplying the power of the voltage representing one value of the binary signal through the resistor, the board position line If a signal based on the negative pole of the power supply is not input to, a signal based on the positive pole of the power supply is always input.

According to the invention of claim 5,
When a signal that deviates from the range of signals output to the board position line is input to the board, that is, in the invention of claim 1,
When two or more signals having the same value as the signal output by the board are included in the input signals, the value obtained by decoding the input signal deviates from the pre-registered value. If so, the board position is processed as if it was not detected normally.

Further, in the invention described in claim 6, the signal output from the board to the board position line is once output when the board is attached when the power is supplied to the motherboard. Since the signal is used to detect the board mounting position, the operation to detect the mounting position of the board is performed only once when the board is mounted, and the mounting position of the board remains the state of the live line where power is supplied to the device. Detected.

[0018]

【Example】

(Embodiment 1) FIG. 1 shows a main part of an apparatus B as an embodiment to which the method of the present invention is applied. The device B is the same as the device A shown in FIG. 5 except for the circuit related to the board position detection, and the other parts are the same, so the overall description of the device B will be omitted and the circuit related to the board position detection will be omitted. Parts other than will be described with reference to FIGS. 5 and 6.
Further, in the following description, the terminals and the signal lines connected to the terminals and the signals transmitted by the signal lines are denoted by the same reference numerals, and the binary signal is abbreviated as the signal.

FIG. 1A shows the mother board 1A of the device B,
FIG. 3 is a diagram showing a connection relationship between the board 2 and the motherboard 1A and the board 2. Motherboard 1A is a circuit board consisting of a board on which a signal bus is laid on a printed wiring board and a slot SLj (j is a slot number) of a mechanism for mounting board 2, and board 2 is a board of mother board 1. It is a device that includes a circuit mounted on a printed wiring board that inputs and outputs signals via a signal bus and performs data processing.

The board 2 has a control operation unit 21A, a monostable multivibrator RG (abbreviated as monostable circuit RG in the following description), and a logic circuit ND. The control calculation unit 21A is
A circuit portion having the same control calculation means as the control calculation portion 21 shown in FIG. 6 except that the signal RDYO is output.
Address / data terminals AD0, AD1 ~, control signal terminals and one of the control signal terminals, RDY, are provided under the control of signals via the control bus CB to which the control signal terminals are connected. Addresses and data are exchanged with other boards via the address / data bus ADB connected to pins AD0 and AD2. The signal RDYO is output by the control calculation unit 21A in the response phase RP (see FIG. 7).
The signal becomes 0 only during the period of 1 and becomes 1 at other time points. The monostable circuit RG is a monostable circuit RG that turns the output to 0 for a set time longer than the time from when the power supply voltage supplied from the mother board 1 is mounted to when the response phase RP is completed. It is a stable circuit, and the logic circuit ND is a signal output from the control calculation unit 21A.
This is a circuit that outputs 0 when the contents of both RDYO and the monostable circuit RG are 0, and the signal output from the logic circuit ND is output from the terminal SIDRD of the board 2. Therefore, when the voltage is applied to the mother board 1 (in the following description, it is described as a hot line state), when the board 2 is mounted on the mother board 1, from the terminal SIDRD, in the response phase RP,
The signal value 0 is output. In addition, the signal output from the terminal SIDRD is the address / data bus by the control calculation unit 21A.
It is given to the terminal RDY as a control signal RDY that gives the time to input the data on ADB.

An address / data bus ADB and a control bus CB are wired on the mother board 1A, and the address / data bus ADB is connected to the board 2 via a connection terminal CN1j.
The control bus CB is connected to the board 2 via the connection terminal CN2j. Further, the mother board 1A is provided with the board position lines Lj (j is the number 0, 1 etc. of the board position lines), and the slot position circuit CTj is not provided.
It has the same configuration as the motherboard 1 shown in FIG.

FIG. 1B shows the relationship between the detailed portion of the board position line and the board 2 connected to the board position line. In the figure, AD0, AD1, AD2 to AD19 are the address / data bus ADB.
, L0, L1, L2 to L19 are board position lines, and SL0, SL1, SL2 to SL19 are slots that are a mechanism for mounting the board 2 at a predetermined position on the motherboard 1A. One end of the board position line Lj is a signal line ADi (i is an address /
Connect to the signal line number that makes up the data bus ADB,
The other end has the terminal SI of the board 2 mounted in the slot SLj (j is the slot number and represents the mounting position of the board 2).
Connect to DRD Connect to one of the terminals of CN2j.
In the figure, one end is connected to each of the signal lines AD0, AD1, AD2, AD19, and the other end is connected to the terminal SIDRD of the board 2 to be installed in each of the slots SL0, SL1, SL2, SL19. Board 2 is installed in slot SL1,
The case where the terminal SIDRD of the board 2 is connected to the signal line AD1 via the board position line L1 is shown.

FIG. 2 shows an example of the operation of the board 2 when the board 2 is mounted on the motherboard 1A while the power is supplied to the device B. When the board 2 is mounted on the slot SL1 of the motherboard 1A. The timing chart showing the operation of is shown. When the board 2 is mounted on the motherboard 1A and the voltage supplied to the control calculation unit 21A (see (a) in FIG. 1) rises, the control calculation unit 21A does not exist in the device B in the request phase QP. The address of is output. Therefore, this request phase QP is followed by the response phase RP
In, the signals from other boards are not output. On the other hand, when the power supplied to the board 2 rises, the value of the output signal RG of the monostable circuit RG (see (a) in Fig. 1) becomes 0, and remains 0 until the response phase ends. , In the response phase RP, the value of the signal RDY0 output from the control calculation unit 21A becomes 0, so the mounted board 2
Sets the signal output from the terminal SIDRD in the response phase RP to the L level which represents 0 of the binary signal. The signal output from the terminal SIDRD is output to the address / data bus ADB via the board position line L1 (see (b) in Fig. 1), and at the same time, the address / data is output to the terminal RDY of the control calculation means 21A. It is input as a control signal that prompts the input of data on the bus ADB.

The signal line ADi is binary-coded through a resistor Ri (i is a resistor number, only the symbol of resistor R0 is added in the figure) at a board position line Lj or another portion as shown in the diagram. Positive polarity Vcc of the power supply of the device 1A, which is the reference for the signal 1
Connect to. Therefore, the signal lines that make up the address / data bus ADB other than the signal line ADi connected to the board position line Lj that outputs the signal value 0 are used when the signal value 0 is not output from other circuits. , A signal value of 1 is shown. Note that the resistance value of the resistor Ri is selected such that the current value flowing when the power supply voltage of the device 1A is applied to this resistor is equal to or less than the current value allowed to flow into the terminal that outputs 0 of the signal value. .

Since there are no signals output from other boards on the address / data bus ADB as described above, the data on the address / data bus ADB is the same as the terminal SI of the board 2.
The L level voltage corresponding to 0 of the signal value output from the DRD and the signal value input via the resistors R0 to R19 (only the sign of the resistor R0 is shown in the figure) excluding the resistor R1 1
Since it is the data represented by the H level voltage corresponding to, the data input to the board 2 is 0 in the second lowest digit.
Then all other digits are binary numbers of 1. The control calculation unit 21A is
Invert each bit of the input data, obtain 1 which is the inverted value of the second lowest digit and 0 which is the inverted value of the other digits, and assign the slot number 1 in which the board 2 is installed. Detect.

FIG. 3 shows the operation until the board 2 detects the mounting position when the board 2 is mounted on the mother board 1 in the hot-line state in which power is supplied to the device B as described above. It is a flowchart. When the board 2 is mounted on the mother board 1, the control calculation unit 21A enters the process F1, the control calculation unit 21A determines that it is in a hot line state by the signal for detecting the rising of the power supply, enters the process F2, and the Output the address signal. Response phase RP (see Figure 2)
When it enters, the process goes to F3 and the signal output from the terminal SIDRD is changed to L
Set to level and proceed to process F4 Address / Data bus ADB
(See (a) in Fig. 1) Input the above data, proceed to process F5, and set the signal SIDRD to H level.
To H level. Next, the process proceeds to the process F6, the input data is inverted, and the bit in which 1 is set in the data inverted in the process F7 is inspected, and the bit in which 1 is set is 1
If it is a value other than two, the process proceeds to the abnormal process F10, and if the bit in which 1 is set is 1, the process proceeds to process F8, and in the process F8, 1
It is determined whether or not the position of the bit for which is set is within a predetermined range. For example, the number of signal lines that make up the address / data bus ADB is 32, and the board position line is AD0-
If it is connected to AD19 and the data input from the signal line AD25 is 1, it means that there is an abnormality, so the processing proceeds to abnormality processing F10. When both the processes F7 and F8 are determined to be normal, the process proceeds to a process F9, and the data obtained up to the process F6 is stored in the storage means in the control calculation unit 21A as a number indicating the mounting position of the board 2 on the motherboard 1. (Embodiment 2) FIG. 4 shows a circuit portion for detecting a mounting position of a board of a device C having a mother board 1B according to another embodiment to which the method of the present invention is applied. Device C is a motherboard
The configuration is the same as that of the device B shown in FIG. 1 except that the 1B is mounted.

As shown in the figure, an address / data bus ADB made up of signal lines ADi (i is a signal line number forming the address / data bus ADB) and a control bus CB (not shown) are wired on the motherboard 1B. These wirings are signal lines having the same functions as the wirings with the same reference numerals shown in FIG. SL0 to SL3 are slots, 2 is a board, which is the same as the one shown in FIG.
Is the same signal as the signal of the same sign shown in FIG. 1, which has a value of 0 when the board 2 is mounted on the mother board 1B in a live state. LA1 to LA4 are board position lines, and the side not connected to the board is branched. Board position line LA0 is divided into signal lines AD0 and AD1 via the respective diode ends via diodes.
The board position line LA1 is connected to the signal lines AD0 and AD2 through the diodes at the branched line ends, and the board position line LA2 is connected to the signal lines AD0 and AD3 at the branched line ends through the diodes. Connect to and board position line LA3
The branched line ends are connected to the signal lines AD1 and AD2 via diodes.
The board position line LA4 is connected to the signal lines AD1 and AD3 through the respective diode ends of the board position line LA4. The polarity of the diodes connected to the board position lines LA0 to LA4 is from signal lines AD0 to AD3 to slots LA0 to LA3.
This is the direction in which the current flows, and prohibits signal leakage between the signal line lines AD0 to AD4. Further, the signal line ADi (i is the number of the signal line forming the address / data bus) is a resistor
It is connected to the positive pole Vcc of the power source of the device C, which is the reference of the voltage representing 1 of the signal, through Ri (i is the resistance number, only the resistance "0" is shown in the figure).

The operation when the board 2 is mounted in the slot SLj is performed as shown in the flow chart of FIG. That is, when the board 2 is mounted in the slot SL1, the signal having the value 0 is sent to the signal lines AD0 and AD2 via the board position line LA1.
SIDRD is output. The signal lines that compose the address / data bus ADB other than the one that outputs the signal SIDRD are resistors.
Since it is connected to the positive pole Vcc of the power source via Ri, the signal value transmitted by these signal lines is 1. Therefore, in the response phase RP (see FIG. 2) where the signal SIDRD becomes 0, the data read and inverted by the control operation unit 21A (see (a) in FIG. 1) is binary "0101" ( Signal line AD0
The value of is the least significant digit). The following table lists the data generated as board positions when boards are sequentially inserted from slot SL0. That is, the slot
"0011" when inserted in SL0, "0" when inserted in slot SL1
101 ", if inserted in slot SL2" 1001 ", slot SL3
"0110" for insertion into slot, "101" for insertion into slot SL4
0 ". As in the example explained above, the combination of the board position line LAj and the signal line ADi is selected so that the data generated on the signal line ADi by the signal SIDRD have different values. To do.

The board 2 mounted on the motherboard 1B is
When the data generated by the signal SIDRD described above is input, the input data becomes a code unique to the mounting position having a different value depending on the mounting position of the board 2.

[0030]

As described above, according to the first aspect of the present invention, the signal lines of which one end constitutes the address / data bus are provided on the motherboard at the positions where the individual boards are mounted. Provide a board position line that connects to one and the other end connects to the board mounted at this position, and
Each board position line shall not be connected to the same signal line. Then, the board detects the mounting position of the board on the motherboard by inputting the signal output to the board position line.

Therefore, according to the first aspect of the present invention, since the signal line for inputting the position detection data is used together with the signal line necessary for the original operation, the signal line dedicated for the board position detection is Only one board position line is required per slot. Further, in the second invention described in claim 2, the line end connected to the signal line of the board position line is branched into n lines, and the branched n line ends are provided with the signal current only in one direction. The wirings are connected to different signal lines via passing diodes and the values obtained by decoding the binary signals output from the boards via the board position lines do not match.

Therefore, according to the second invention, the number of signal lines is four.
In the case of more than the number of lines, it is possible to set the positions on the motherboard more than the number of signal lines. Further, according to the invention described in claim 3, the board outputs a control signal which gives a time point at which the data on the data bus is input, in synchronization with the signal output via the board position line. Therefore, since the control for generating the signal for detecting the position on the mounted board by the mounted board and the control for reading the generated signal are performed, the mounted board does not require any support operation from others. The position can be detected.

According to the fourth aspect of the present invention, the board position line or the signal line is connected to the positive electrode of the power supply for supplying the electric power of the voltage representing one value of the binary signal via the resistor. . Therefore, all the signal lines on which the signal output from the board via the board position line does not flow carry the binary signal 1 through the resistor, so that the address / data bus read by the control arithmetic unit at the time of board position detection. In the above data, the signal output from the board via the board position line is reliably distinguished from other signals, and high reliability is obtained for detecting the board position.

According to the invention described in claim 5, when the board receives a signal that deviates from the range of the signal output to the board position line, the board position is not normally detected. Process. Therefore, even if there is an error in the signal for detecting the board position, it is possible to prevent loss due to an error in the signal in advance. Further, according to the invention described in claim 6, the signal output from the board to the board position line is one time output when the board is mounted when the mother board is in a state where power is supplied. Since it is a signal, the board mounting position is detected
The board position can be detected without stopping the device because it is detected only once when the board is mounted on the motherboard and when the device is in a hot line state. The position detection operation can be performed with almost no influence on the communication of other boards.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an apparatus to which the method according to the present invention is applied, (a) showing a mother board and a board of the apparatus,
Figure (b) shows the relationship between the board mounting position detection circuit on the motherboard and the board mounting position.

FIG. 2 is a timing chart showing the operation of board mounting position detection.

FIG. 3 is a flowchart showing the operation of detecting the mounting position of the board.

FIG. 4 is an explanatory diagram of another device to which the method according to the present invention is applied.

FIG. 5 is a diagram showing an example of a device having a structure for mounting a board on a mother board.

6 is an explanatory view of a conventional method for detecting the board position on a motherboard in the device shown in FIG.

FIG. 7 is a timing chart of signals when the board communicates with an external circuit.

[Explanation of symbols]

1A motherboard ADB address / data bus CB control bus L0, L1, L2, L19 Board position line 2 boards AD0, AD1 address / data pins RDY Response phase control signal terminal SIDRD Output signal terminal for board position detection SL0, SL1, SL2, SL19 Board positioning slot

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Motoaki Sugimoto 1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Electric Co., Ltd. (56) References: Fukukaihei 6-51931 (JP, U) ( 58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 13/14

Claims (6)

(57) [Claims] 1. A method for detecting a mounting position of a plurality of boards mounted on a mother board and connected via a signal bus line wired on the mother board, wherein each board is mounted on the mother board. To
One end is connected to one of the signal lines forming the address / data bus of the signal bus, and the other end is provided with a board position line connected to the board mounted at this position via a connection terminal. The board position line is not connected to the same signal line, and the board detects the mounting position of the board on the motherboard by inputting the signal output to the signal line via the board position line. Board mounting position detection method. 2. A method for detecting a mounting position of a plurality of boards mounted on a mother board and connected via a signal bus line wired on the mother board, wherein positions of individual boards mounted on the mother board are detected. To
A board position line in which one conductor is branched into n is provided, and the signal lines forming the signal bus are mutually connected through a diode that passes a signal current only in one direction through a line end of the board position line branched into n. Connect to different signal lines, connect the line ends on the non-branching side of the board position line to the board mounted at this position via the connection terminal, and output from each board to the signal bus line via the board position line. The method for detecting the mounting position of a board is characterized in that the wirings of the combinations are such that the decoded values of the binary signals are not matched. 3. The board mounting position detecting method according to claim 1 or 2, wherein the board detects a time point at which data on the signal line is input in synchronization with a signal output via the board position line. A board mounting position detection method characterized by outputting a given control signal. 4. The board mounting position detecting method according to any one of claims 1 to 3, wherein the board position line or the signal line is a power of a voltage representing one value of a binary signal. A method for detecting the mounting position of a board, which is characterized in that it is connected to a positive electrode of a power supply for supplying power via a resistor. 5. The board mounting position detecting method according to claim 1, wherein the board is out of the range of signals output from the board via the board position line. A board mounting position detection method, characterized in that when a signal is input, processing is performed when board position detection is not performed normally. 6. The board mounting position detecting method according to claim 1, wherein a signal output from the board via the board position line is supplied to the mother board. A method for detecting the board mounting position, wherein the signal is one signal output when the board is mounted when the board is mounted.