CA1087746A - Method and apparatus for effecting inter-bus communications in a multi-bus data processing system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
In order to carry out communications among the subsystems of a multiple-bus data processing system without the necessity for providing destination decoding means capable of handling the full addresses of the maximum possible configuration, the destination decoder associated with each message originating Subsystem is provided with the capability for addressing only the ports on its immediate bus. If a destination code from the originating subsystem indicates that the destination subsystem is located on another bus, a comparator senses this condition and manipulates the lower order field of the destination code to steer the message to a port reserved for direct communication with the specified remote bus. The entire original destination code is also transmitted to the remote bus for checking for proper bus destination and for directing the message to the designated destination subsystem on the remote bus. The corres-ponding method for achieving the communication link in the multiple-bus data processing system is inherent in the logic of the apparatus.

Description

This invention relates to a method and apparatus for effect-ing inter-bus communications in a multi-bus data processing system ant, more particularly, to the art of information transfer among the subsystems of a bus-oriented data processing system emplOying multiple busses.
This invention may be employed in a data processing system such as that disclosed in U. S. patent application Serial No.
633,345, entitled 'kigh Speed Destination Selection Means For A
Bus Oriented Computer System", by Jack R. Duke, Philip W. Brooks and Robert R. Elzer, now U. S. Patent No. 4,038,644 and assigned to the same assignee as the present application.
Among the recognized architectures for data processing systems i9 the well-known bus-oriented system in which the various subsystems communicate with one another through a common bus. The maximum number of "ports" by which subsystems may be coupled to a single bus is limited by both hardware and software considerations. A "port" for purposes of this invention is de-fined as: "A place of access to a system or circuit. Through it, energy can be selectively supplied or withdrawn ...."
(Modern Dictionary of ELECTRONICS, by R. F. Graf, Howard W. Sams & Co. Inc. 1972, pp 438.) However, it is manifestly desirable to have the capability, in a bus-oriented system, for accommo-dating more subsystems than can be coupled to a single bus.
Thus, bus-oriented data processing systems intended for large scale use must provide some means for employing multiple busses and handling the attendant bus-to-bus communications. In the prior art, this function has typically been carried our by de-signing into the processing unit the capability for itself com-municating with two or more busses. This approach, however, creates a "bottleneck" which somewhat constrains the very flex-ibility which is a fundamental advantage of the bus-oriented architecture.

. ~, -- 1 --10~7~46 Those skilled in the art will appreciate that it would be highly desirable to afford means for carrying out inter-bus communications in a multiple bus system without the necessity for tying up the processing element. It would be further ad-vantageous to provide such means in which communications from one bus to another could be carried out "transparently" insofar as the transmitting and receiving subsystems are concerned.
It is therefore a broad object of our invention to provide an improved means and method for carrying out inter-bus communi-10 cations in a bus-oriented system employing multiple busses. ' It is another object of our invention to provide such means and method which is simple and completely reliable in operation.
It is yet another object of our invention to provide such means and method by which the transfer is carried out extremely quickly and reliably.
It is a still further object of our invention to provide such means and method in which information is transferred be-tween communicating subsystems completely transparently insofar as the subsystems are concerned.
Briefly, in a multiple-bus data processing system having a plurality of subsystems, these and other objects of the inven-tion are achieved by providing a local bus adapter disposed be-tween each bus and each subsystem. Each subsystem is coupled by an associated adapter to an associated bus at a unique port with each port identified by a port address, and with each bus identi-fied by a bus address. The local bus adapter operates to effect communications between an originating subsystem and a destina-tion subsystem. The originating subsystem issues a message which includes a destination code of a destination subsystem, the destination code containing a bus address portion and a port address portion. Each bus is coupled to an adjacent bus thru at least one common port. The adapter includes a destination code analyzer which operates to connect an associated subsystem in order to receive the destination code emanating from the as-sociated subsystem. Also, the destination code analyzer oper-ates to provide at its output a signal indicative of the port address portion of the destination code if the bus address portion of the destination code corresponds to the bus address of the originating subsystem or to provide a signal indicative of the common port address if the bus address portion of the destination code does not correspond to the bus address of the originating subsystem, the signal indicative of the common port address having been modified by the destination code analyzer means. The adapter also includes logic for connecting the originating subsystem to a destination subsystem by enabling a destination adapter coupled to the port identified by the port address at the output of the destination code analyzer ef-fecting intra-bus communications with the subsystem coupled to the enabled adapter, and effecting inter-bus communication when the enabled adapter is coupled to the common port, the destina-tion adapter receiving the message unmodified.
The invention further includes the corresponding method of communicating between originating and destination subsystems situated on different busses in which each bus contains multiple ports with at least one port of each of the different busses interconnected to a port of another bus and each subsystem is connected to its associated bus port thru an adapter. The steps of the method are first issuing a destination code from the originating subsystem, the destination code having a first field designating one of the system busses and a second field designat-ing a particular port, and second providing a first standard field identifying the bus to which the originating subsystem is directly coupled. The third step performs the comparing of the first field of the destination code to the first standard field to sense compare and no-compare states. The fourth step includes modifying the second field of the destination code to a port n ~ er cor~e.p~r-din~l tc~ tOe ~

_ - 3a -108774~;
to a port of another bus, only for the no-compare state. The last step performs the decoding of the second field of the desti-nation code resulting from the fourth step to select the adapter specified by the second field. The selected adapter enables its associated subsystem to effect intra-bus communication or, if the selected adapter is interconnected to a port of another bus rather than to a subsystem, transmit to the other bus to effect inter-bus communication.
The sub~ect matter of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, may best be understood by reference to the following description taken in connection with the sub~oined claims and the accompanying drawings of which:
Figure 1 i8 a major block diagram of a bus-oriented, mul-tiple-bus data processing system comprising an exemplary environ-ment in which our invention finds use;
Figures 2A and 2B, taken together, are a logic block dia-gram of a local bus adapter module from the system of Figure l;
Figure 3 is a block diagram of an exemplary destination code analyzer included in each of the local bus adapters of all the busses of the system; and Figure 4 is a tabulation of the output signals of the bus selection switch corresponding to the switch setting.
The logic diagrams are presented in slightly simplified form in order that the inventive concept may be more readily understood. For example, instantaneous response times are as-sumed such that no special circuitry is shown for overcoming logic race conditions which may occur as the speed of operation is increased until the circuits cannot be assumed to respond immediately. The changes and additions required to overcome logic race conditions and other problems associated with ex-~87746 tremely high speed operation are known to all gkilled in the artand are of no consequence to an understanding of the invention.
To further clarify the inventive concepts, the logic is present-ed using the most basic types of AND-gates, OR-gates, flip-flops, etc. It is apparent that the inventive concepts can be realized and practiced utilizing the more complex types of logic elements which are now generally incorporated into contemporary data pro-cessing systems because of the availability and general use of integrated circuits directly realizing such complex logic ele-ments. Further, the operation of the apparatus is presented ina strictly sequential form. Of course, conventional timing practice in data processing apparatus utilizes, to the fullest extent possible, overlapping and simultaneous logic operations to increase overall speed.
Attention is now directed to Figure 1 which illustrates, in a block diagram, an exemplary data processing system in which the present invention finds use. The data processing system of Figure 1 is bus-oriented in that all the immediate subsystems, including the processor subsystem 1, are coupled to one another by means of an internal transfer bus 2. The internal transfer bus is incorporated into an internal transfer bus subsystem 3 which also includes a plurality of local bus adapters 4, an inter-bus communication adapter 5, bug control logic 6, and timing logic 7. In the internal transfer bus subsystem, up to 16 local bus adapters may be coupled to the internal transfer bus 2. Typically, only one inter-bus communication adapter 5 is provided. Undesignated subsystem 8 may constitute any of the typical subsystems usually found in a bus oriented data processing system: e.gO: core memory, tape units, disc units, printers, v~deo displays, etc. The service subsystem 9 may in-clude a system console to effect two-way communication between an operator and the data processing system.

The function of the internal transfer bus 2 is to transmit information from one local bus adapter to another local bus adapter. It defines the paths and procedures to be used by the local bus adapters to communicate with each other. All infor-mation is passed over the internal transfer bus sequentially following the common procedure defined by the internal transfer bus protocol. The identical local bus adapters 4 interface each subsystem to the internal transfer bus. Each local bus adapter performs all the logic operations necessary to insure that the internal transfer bus discipline is maintained at all times.
The bus control logic 6 performs several func~ions. It arbitrates all local bus adapter requests to use the internal transfer bus on a fixed priority basis in the exemplary embodi-ment. The bus control logic also checks the parity of all mes-sages sent over the internal transfer bus and reflects the re-sult of the parity check onto the internal transfer bus for analy8is by the communicating local bus adapters. The bus con-trol logic can communicate with the service subsystem 9 and the processor subsystem 1 by means of the serial serv~ce bus 10 in order to provide certain system condition history and status in-formation and configuring sign~ls of no direct consequence to the present invention.
The internal transfer subsystems are synchronous logic machines in that all operations in the internal transfer sub-systems are synchronized with clock and phase signals emanating from the timing logic 7.
The inter-bus communications adapter 5 facilitates communi-cations between the system components associated with the internal transfer bus subsystem 3 and the subsystems associated with a second internal transfer bus subsystem 3' from which additional subsystems 8' depend.
Referring now to Figures 2A and 2B, the apparatus comprising . ~
. ~ ~

an exemplary local bus adapter will be discussed. The local bus adapter is disposed between a subsystem interface 11 and an in-ternal transfer bus interface 120 The local bus adapter receives requests, data, destination, and status information from its as-sociatet subsystem at the interface 11. Those skilled in the art will appreciate that such information is routinely available from typical subgystems used in bus-oriented data processing syætems.
The local bus adapter receives data, opcode, busy line, request-granted, and parity error information from the bus interface 12.
The data and opcode information is selectively passed on to the subsystem at the interface 11. Similarly, the data and destina-tion information received from the subsystem is selectively is-sued to the bus interface 120 In addition, the local bus adapt-er issues a request signal to the bus and also can affect the status of any one of the busy lines brought into the local bus adapter.
A request signal received from the subsystem interface 11 passes through a time controlled AND-gate 98, the output from which is used to set the request flip-flop 19. The Q output from the request flip-flop 19 is applied as one input to an AND-gate 20, and to the in-clock input to the output buffer 13. The other input to the AND-gate 20, which serves to issue a priority request signal from the local bus adapter to the bus interface 12, is received from the busy line selection logic 17.
Data and destination information from the subsyætem inter-face 11 is clocked into an output buffer 13 when the subsystem request flip-flop 19 is setO The destination information from the subsystem interface 11 is then applied, in 6-bit form, to a destination code analyzer 100, and also to an output AND-gate array 14 along with the data. Transfer of this information through the output AND-gate array 14 is controlled by the state of a request-granted flip-flop 15 which has its Q output con-nected to each of the gates in the arrayO
The analyzed destination code from the destination code analyzer 100, which in the exemplary embodiment constitutes a 4-bit code designating ports 0000 through 1111 (i~e., O through 15), is applied to a one-of-sixteen decoder 16. One-of-sixteen decoder 16 issues an enabling signal from a single one of its sixteen outputs according to the binary configuration of the analyzed destination codeO The sixteen output lines from the one-of-sixteen decoder 16 are applied to busy line selection logic 17 which also receives an input from the Q output of the request-granted flip-flop 15. The busy lines 18 of all the sub-systems in the instant internal transfer bus subsystems are available for monitering by the busy line selection logic 17, and the busy line selection logic 17 includes means for selec-tively forcing any one of the busy lines 18 to the busy state.
Information received from the bus interface 12 is gated to an input buffer 22 through an input AND-gate array 23 when a busy flip-flop 21 is in the set state because the Q output there-from is coupled to enable the gates in the array 230 The Q out-put from the busy flip-flop is also applied to the set input of a busy line latch flip-flop 96, and the Q output from the busy line latch flip-flop is connected to the immediate local bus adapter's own busy line 97. Thus, once set, the busy line latch flip-flop 96 holds the corresponding busy line in the busy state until the busy line lstch flip-flop is subsequently resetO
At the end of a message transmission cycle, a status check is carried out to determine the validity of the received messageO
If the message is unacceptable tG the receiving subsystem (such as including the opcode of a command which the particular sub-system is incapable of executing), the subsystem provides acorresponding signal to the status logic 24. Similarly, if a parity error is detected by the bus control logic 6 (Figure 1), a parity error signal is applied to the status logic 24. Thus, either type of error will be sensed by the status logic which also has the facility for determining whether the immediate error is the first which has occurred during the present cycle.
The means by which the busy lines are employed to select destination ports in the internal transfer bus subsystem and detailed exemplary logic for the various logic blocks illustrat-ed in Figures 2A and 2B are presented and explained in U. S.
Patent No. 4,038,644 issued 26 July 1977, entitled "Destination Selection Apparatus For A Bus Oriented Computer System", by Jack R. Duke, Philip W. Brooks, and Robert R. Elzer, and as-signed to the same assignee as the present invention.
Exemplary logic for the destination code analyzer 100 is illustrated in Figure 3. The 6-bit destination code, as receiv-ed from the subsystem after passing through the output buffer 13, is methodically applied to an array of AND-gates. Bit 1 is ap-plied to a first input to an AND-gate 102. Similarly, bits 2-6 are applied to one input each of AND-gates 104, 106, 108, 110, and 112, respectively. In addition, bit 5 is applied to input of AND-gate 114, and bit 6 is applied to one input of an AND-gate 116. First inputs to each of a pair of AND-gates 118 and 120 are directly connected to a source of logic "0" voltage and are held permanently at the logic level. Bit 5 is also inverted through an inverter 126, and the resultant signal is applied to a first input to an AND-gate 122. Bit 6 is similarly inverted through inverter 128, and the resultant signal is applied to a first input to an AND-gate 124.
The output signals from the AND-gates 102 and 114 are ap-plied as separate inputs to an OR-gate 130. Similarly, the output signals from the AND-gates 104 and 116 drive OR-gate 132;

.~ .,, _ _ the output signals from AND-gates 106 and 118 drive OR-gate 134;
and the output signals from AND-gates 108 and 120 drive the OR-gate 136. As will be explained more fully below, the output Signals from the OR-gates 130-136 are utilized as the 4-bit ad-dress code applied to the one-of-sixteen decoder 16 (Figure 2B) and therefore determines which one of the busy lines of the im-mediate bus subsystem will be forced to the busy state to select the corresponding port as the destination.
Each of the AND-gates 110, 122, 112 and 124 receive respec-tive second inputs from a switch 138. Signal A from the switch 138 i8 applied to the AND-gate 110. Similarly, signal B from the switch 138 is applied to the AND-gate 122; signal C is ap-plied to the AND-gate 112; and signal D is applied to the AND-gate 124. The switch 138 receives "1" and "O" logic voltage levels from any suitable source and is internally wired to pro-vide the outputs tabulated in Figure 40 Thus, by way of example, if the local bus adapter ~s disposed in bus subsystem number 1, the switch 138 will be set such that output A will always be at a logic "1" level, output B will always be at a logic "O", out-put C will always be at a logic "O", and output D will always be at a logic "1".
The output signals from the AND-gates 110 and 122 are ap-plied as separate inputs to an OR-gate 140, and the output sig-nals from AND-gates 112 and 124 are applied as separate inputs to an OR-gate 142. The output signals from the OR-gates 140 and 142 are coupled to separate inputs to an AND-gate 144. The AND-gate 144 drives second inputs to each of the AND-gates 102, 104, 106, and 1080 In addition, the output from the AND-gate 144 is passed through an inverter 146 and the inverter drives second inputs to each of the AND-gates 114, 116, 118, and 1200 In operation, if bits 5 and 6 define a destination sub -system, bits 1-4 should be passed in their original form to the ~ - 10 -one-of-sixteen decoder 16 (Figure 2B)o However, if bits 5 and 6 define a subsystem situated on a remote internal transfer bus subsystem, the four lower order bits are manipulated by setting bits 3 and 4 to logic "O" and transferring bits 5 and 6 to bit positions 1 and 2, respectively.
By way of example, suppose that the destination subsystem is coupled to bus number O and the originating subsystem is also on bus O. The destination code analyzer 100, which will be in the local bus adapter associated with the originating subsystem, 10 will be identified as associated with bus O by signals A and C
being logic "0'8" and signals B and D being logic ~ s~o When bits 5 and 6, which will both be logic "O's", are presented to the destination code analyzer, they completely disable AND-gates 110 and 112. However, after being inverted through the inverters 126 and 128, the resultant signals will fully enable AND-gates 122 and 124 which have already been partially enabled by the signals B and D from the switch 138. Thus, AND-gates 122 and 124 issue signals which enable both the OR-gates 140 and 142.
The OR-gates 140 and 142 drive snd fully enable the Al~-gate 144 20 to indicate a "compare" condition. As a result, AND-gates 102, 104, 106, and 108, which directly receive the la~7er four ord~r bits, are enabled, and their outputs drive, respectively, the OR-gates 130-136 to pass on the unaltered four lower order bits to the one-of-sixteen decoder 16 (Figure 2B) for selecting the destination subsystem port in the normal manner.
Consider now the circumstance in which the originating sub-system, as in the previous example, is disposed on bus number 0, but the destination subsystem is on bus number 2 as specified by bit 6 being a logic "1" and bit 5 a logic "0"0 Since bit S is a 30 logic "O", the output of the inverter 126 and the signal B are logic ~ s~9 AND-gate 122 will be enabled to enable OR-gate 140 which brings up one input to the AND-gate 144. However, since bit 6 is now a logic "1", the inversions through the inverter 128 will serve to disable the AND-gate 1240 In addition, the AND-gate 112 is disabled even though it receives, at one input, the logic "1" from bit 6, because signal C is a "O". As a result, neither the AND-gate 112 nor the AND-gate 124 is enabled, and the OR-gate 142 is therefore not enabled. The output from the OR-gate 142 serves toprevent the AND-gate 144 from becoming en-abled. Thug, a "no compare" condition is sensed.
The "O" logic level which is present at the output of the AND-gate 144 is inverted through the inverter 146, and the re-sultant logic "1" is employed to partially enable the AND-gates 114, 116, 118, and 120. As previously ted, the other inputs to the AND-gates 118 and 120 are directly tied to a source of logic "O" voltage such that a logic "O" appears at the output of the AND-gates 118 and 1200 Since the second inputs to the AND-gates 106 and 108, driven by the AND-gate 144, are also at a logic "O" level, the OR-gates 134 and 136 will issue logic "O's".
The inverter 146 also partially enables AND-gates 114 and 116 which permits gating, respectively, bits 5 and 6 into destination code bit positions 1 and 2~ In the example, bit 5 is a "O" such that the OR-gate 130 will issue a IIOIID Similarly, bit 6 is a logic "1", and the OR-gate 132 will issue a logic "1". There-fore, the 4-bit address issued to the one-of-sixteen decoder 16 (Figure 2B) will specify port two which is specifically employed to communicate with bus number 2. However, the full six bit ad-dress, in its original form, is also transmitted through port two to bus number 2 where it is received into a local bus adapter having its switch 138 set to identify the local bus subsystem as bus number 2. At that local bus adapter, the switch 138 will have been set with signal A being a logic "O", signal B being a logic "1", signal C being a logic "1" and signal D being a logic "O". As a result, at the receiving local bus adapter, the AND-10~7746 gates 122 and 124 will be fully enabled by the incoming destina-tion code to create a full compare and thereupon permits the four lower order bits, in their original form, to pass to that local bus adapter's one-of-sixteen decoder 16. Consequently, the destination subsystem on the remote bus is selected in the usual manner employing manipulation of the busy lines.
Thus, while the principles of the invention have now been made clear in an illustrative embodiment, there will be immedi-ately obvious to those skilled in the art many modifications of structure, arrangement, proportions, elements, and components used in the practice of the invention which are particularly adapted for specific environments and operating requirements without departing from those principles.

Claims (8)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a multiple bus data processing system having a plu-rality of subsystems, each subsystem coupled by an associated adapter means to an associated bus at a unique port with each port identified by a port address, and with each bus identified by a bus address, said adapter means operative for effecting communication between an originating subsystem and a destination subsystem wherein said originating subsystem issues a message which includes a destination code of a destination subsystem, said destination code containing a bus address portion and a port address portion, and wherein each bus is coupled to an adjacent bus thru at least one common port, said adapter means comprised of a buffer means for receiving the destination code from its associated subsystem; a destination code analyzer means, having a plurality of input leads and a plurality of output leads, said plurality of input leads operatively connected to said buffer means for receiving the destination code and said plurality of output leads for outputting an analyzed destination port address, i) for comparing the bus address portion of said destination code against the bus address of its associated subsystem, and ii) upon a compare result from the comparing operation, for transferring the port address portion of said destination code to said plu-rality of output leads for effecting intra-bus communications, or upon a no-compare result from the comparing operation, for modi-fying the port address portion of said destination code to a fix-ed port address as determined by the bus address portion of said destination code, transferring said fixed port address to said plurality of output leads, said fixed port address being the common port which is coupled to said adjacent bus for effecting inter-bus communications; and means responsive to the analyzed destination port address at the plurality of said output leads 1 (concluded) of said destination code analyzer means for selecting a destina-tion adapter means thereby operatively connecting the originat-ing subsystem to the subsystem connected to the port designated by the analyzed destination port address, the destination adapt-er means receiving the message unmodified.

2. The system according to claim 1 wherein said destina-tion code analyzer means is comprised of: switch means for pro-viding a bus address corresponding to the address of the bus associated with said adapter means; first logic means for re-ceiving the bus address portion of the destination code from said buffer means and the bus address from said switch means for providing a logic output of a first state when the received bus addresses are the same and a logic output of a second state when the received bus addresses are of a differing state; and second logic means operatively connected to receive the port address portion of the destination code from said buffer means and re-sponsive to a first state logic output for passing the port address portion unchanged to its output and responsive to a second state logic output for generating a common port address signal at its output to effect selection of said common port used to interconnect adjacent busses.

3. The system according to claim 2 wherein said means responsive to the output of said destination code analyzer means is comprised in part of: a decoder means responsive to the an-alyzed destination port addresses provided by said destination analyzer means for providing a signal to the adapter means as-sociated with the selected port address for purposes of effect-ing communication between the originating subsystem and the destination subsystem.

4. In a multiple bus data processing system having a 4 (concluded) plurality of subsystems, each subsystem coupled by an associat-ed adapter means to an associated bus at a unique port with each port identified by a port address, and with each bus identified by a bus address, said adapter means operative for effecting communication between an originating subsystem and a destination subsystem wherein said originating subsystem issues a message which includes a destination code of a destination subsystem, said destination code containing a bus address portion and a port address portion, and wherein each bus is coupled to an adjacent bus thru at least one common port, said adapter means comprised of: destination code analyzer means operatively connected to an associated subsystem for receiving the destination code emanating from said associated subsystem and for providing at its output a signal indicative of the port address portion of the destination code if the bus address portion of the destination code corres-ponds to the bus address of the originating subsystem or a signal indicative of the common port address if the bus address portion of the destination code does not correspond to the bus address of the originating subsystem, said signal indicative of the com-mon port address having been modified by said destination code analyzer means; and means for operatively connecting the origi-nating subsystem to a destination subsystem by enabling a des-tination adapter means coupled to the port identified by the port address at the output of the destination code analyzer means effecting intra-bus communications with the subsystem coupled to the enabled adapter, and effecting inter-bus communication when the enabled adapter is coupled to the common port, the destina-tion adapter means receiving the message unmodified.

5. The system according to claim 4 wherein said destina-tion code analyzer means is comprised of: switch means for pro-viding a bus address corresponding to the address of the bus 5 (concluded) associated with said adapter means; first logic means for re-ceiving the bus address portion of the destination code from said buffer means and the bus address from said switch means for providing a logic output of a first state when the received bus addresses are the same and a logic output of a second state when the received bus addresses are of a differing state; and second logic means operatively connected to receive the port address portion of the destination code from said buffer means and responsive to a first state logic output for passing the port address portion unchanged to its output and responsive to a second state logic output for generating a common port address signal at its output to effect selection of said common port used to interconnect adjacent busses.

6. The system according to claim 4 wherein said means for operatively connecting the originating subsystem to a desti-nation subsystem is comprised in part of: a decoder means re-sponsive to the port address provided by said destination code analyzer means for converting said port address portion of the destination code into a selection signal operably connected to the one adapter means connected to the selected addressed port.

7. In a multiple bus data processing system, the method of communicating between originating and destination subsystems situated on different busses wherein each bus contains a plu-rality of ports with at least one port of each of said different busses interconnected to a port of another bus and each subsystem is connected to its associated bus port thru an adapter means, comprising the steps of: A) issuing a destination code from the originating subsystem, said destination code having a first field designating one of the system busses and a second field designating a particular port; B) providing a first standard 7 (concluded) field identifying the bus to which the originating subsystem is directly coupled; C) comparing the first field of said destina-tion code to the first standard field to sense compare and no-compare states; D) modifying the second field of said destina-tion code to a port number corresponding to the port number which is interconnected to a port of another bus, only for the no-compare state; and E) decoding the second field of said des-tination code resulting from step D to select the adapter specified by the second field, the selected adapter enabling its associated subsystem to effect intra-bus communication or, if the selected adapter is interconnected to a port of another bus rather than to a subsystem, transmit to the other bus to effect inter-bus communication.

8. The method according to claim 7 and further comprising the step of: gating the destination code from the originating subsystem to the designated adapter upon enabling of the select-ed port.