FR2366630A1 - DATA PROCESSING SYSTEM INCLUDING A TRANSFER SUBSYSTEM - Google Patents

DATA PROCESSING SYSTEM INCLUDING A TRANSFER SUBSYSTEM

Info

Publication number
FR2366630A1
FR2366630A1 FR7712927A FR7712927A FR2366630A1 FR 2366630 A1 FR2366630 A1 FR 2366630A1 FR 7712927 A FR7712927 A FR 7712927A FR 7712927 A FR7712927 A FR 7712927A FR 2366630 A1 FR2366630 A1 FR 2366630A1
Authority
FR
France
Prior art keywords
address
bus
destination
channel
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7712927A
Other languages
French (fr)
Other versions
FR2366630B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of FR2366630A1 publication Critical patent/FR2366630A1/en
Application granted granted Critical
Publication of FR2366630B1 publication Critical patent/FR2366630B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

Un système de traitement de données comprend un ensemble de bus auquel sont connectés des sous-systèmes par l'intermédiaire d'adaptateurs de bus locaux, les divers bus étant couplés l'un à l'autre par l'intermédiaire d'autres adaptateurs de bus locaux. Un sous-système émetteur émet une adresse de destination de 6 bits sur les lignes 158 en vue d'un stockage dans un tampon 13. L'adresse est analysée dans un analyseur 100 pour fournir une adresse de canal de 4 bits concernant un canal du bus émetteur, adresse qui est soit l'adresse du sous-système destinataire soit l'adresse d'un canal de communication inter-bus selon que le sous-système destinataire est couplé au même bus ou à un bus différent Le canal est sélectionné sous le contrôle d'une logique d'occupation de lignes 17. Si le sous-système de destination se trouve sur un bus différent, le code de destination de 6 bits lui est transmis par l'intermédiaire des lignes 164.A data processing system includes a set of buses to which subsystems are connected via local bus adapters, the various buses being coupled to each other via other bus adapters. local buses. A sender subsystem transmits a 6-bit destination address on lines 158 for storage in buffer 13. The address is analyzed in analyzer 100 to provide a 4-bit channel address relating to a channel of the. sender bus, address which is either the address of the destination sub-system or the address of an inter-bus communication channel depending on whether the destination sub-system is coupled to the same bus or to a different bus The channel is selected under controlling row occupancy logic 17. If the destination subsystem is on a different bus, the 6-bit destination code is passed to it through lines 164.

FR7712927A 1976-04-29 1977-04-29 DATA PROCESSING SYSTEM INCLUDING A TRANSFER SUBSYSTEM Granted FR2366630A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US68167376A 1976-04-29 1976-04-29

Publications (2)

Publication Number Publication Date
FR2366630A1 true FR2366630A1 (en) 1978-04-28
FR2366630B1 FR2366630B1 (en) 1981-10-16

Family

ID=24736262

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7712927A Granted FR2366630A1 (en) 1976-04-29 1977-04-29 DATA PROCESSING SYSTEM INCLUDING A TRANSFER SUBSYSTEM

Country Status (5)

Country Link
JP (1) JPS52141532A (en)
CA (1) CA1087746A (en)
DE (1) DE2719282C3 (en)
FR (1) FR2366630A1 (en)
GB (1) GB1538023A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2062912B (en) * 1979-09-29 1983-09-14 Plessey Co Ltd Data processing system including internal register addressing arrangements
NL8500571A (en) * 1985-03-01 1986-10-01 Hollandse Signaalapparaten Bv LOCAL DATA COMMUNICATION NETWORK ACCORDING TO THE MULTIPLE BUS SYSTEM.
JP2782683B2 (en) * 1989-10-19 1998-08-06 三菱電機株式会社 Communication method and node device in LAN

Also Published As

Publication number Publication date
GB1538023A (en) 1979-01-10
DE2719282B2 (en) 1979-05-10
JPS52141532A (en) 1977-11-25
DE2719282A1 (en) 1977-11-10
CA1087746A (en) 1980-10-14
DE2719282C3 (en) 1980-01-10
FR2366630B1 (en) 1981-10-16

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Legal Events

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