KR880008159A - 16-bit write data buffer control circuit of computer system - Google Patents

16-bit write data buffer control circuit of computer system Download PDF

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Publication number
KR880008159A
KR880008159A KR860011497A KR860011497A KR880008159A KR 880008159 A KR880008159 A KR 880008159A KR 860011497 A KR860011497 A KR 860011497A KR 860011497 A KR860011497 A KR 860011497A KR 880008159 A KR880008159 A KR 880008159A
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KR
South Korea
Prior art keywords
control circuit
computer system
data buffer
write data
buffer control
Prior art date
Application number
KR860011497A
Other languages
Korean (ko)
Other versions
KR890005053B1 (en
Inventor
유관섭
권춘우
문우춘
Original Assignee
구자학
주식회사 금성사
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Priority to KR1019860011497A priority Critical patent/KR890005053B1/en
Publication of KR880008159A publication Critical patent/KR880008159A/en
Application granted granted Critical
Publication of KR890005053B1 publication Critical patent/KR890005053B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

내용 없음.No content.

Description

컴퓨터 시스템의 16비트 기입 데이타 버퍼 제어회로16-bit write data buffer control circuit of computer system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 전체 블럭 계통도.1 is a complete block diagram.

제2도는 본 발명의 16비트 기입 데이타 버퍼 제어 회로의 상세도.2 is a detailed diagram of a 16-bit write data buffer control circuit of the present invention.

제3도는 Scc의 채널 A와 B에서 DMA요구에 따른 A/신호 발생회로의 상세도.3 shows A / According to DMA request in channels A and B of Scc. Detailed diagram of the signal generator circuit.

Claims (1)

카운터(21) 및 플립플롭(22내지 25 및 28)해독/기입 동작의 비동기적인 버스 사이클의 완료는 알려주는신호 발생회로(26), 한칩에 연속으로 해독, 또는 기입동작을 할 수 없고, 적어도 최소 지연시간(1.7μSec)를 지난후에 동작할 수 있는 Z8530Scc(11)의 특성을 제어하는 Scc재생 시간 제어 회로(27), 및 기입 DMA를 요구한 채널에 따른 2번째 기입 동작할때에 채널 신호 A/를 적절히 발생시키는 Scc(11)의 채널 A와 B에서의 DMA요구에 따른 A/신호 발생회로(29)로 구성된 것을 특징으로 하는 컴퓨터 시스템의 16비트 기입 데이타 버퍼 제어 회로.The completion of the asynchronous bus cycle of the counter 21 and flip-flops 22 to 25 and 28 read / write operations is indicated. Scc regeneration time control circuit for controlling the characteristics of the Z8530Scc (11) which cannot perform the decoding or writing operation continuously on the signal generation circuit 26, one chip, and can operate after at least the minimum delay time (1.7 µSec). (27), and the channel signal A / during the second write operation in accordance with the channel requesting the write DMA. A / according to the DMA requirement in channels A and B of Scc (11) which generates 16-bit write data buffer control circuit of a computer system, comprising a signal generation circuit (29). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860011497A 1986-12-30 1986-12-30 Data buffer control circuit using 16-bit data in computer system KR890005053B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860011497A KR890005053B1 (en) 1986-12-30 1986-12-30 Data buffer control circuit using 16-bit data in computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860011497A KR890005053B1 (en) 1986-12-30 1986-12-30 Data buffer control circuit using 16-bit data in computer system

Publications (2)

Publication Number Publication Date
KR880008159A true KR880008159A (en) 1988-08-30
KR890005053B1 KR890005053B1 (en) 1989-12-08

Family

ID=19254504

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860011497A KR890005053B1 (en) 1986-12-30 1986-12-30 Data buffer control circuit using 16-bit data in computer system

Country Status (1)

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KR (1) KR890005053B1 (en)

Also Published As

Publication number Publication date
KR890005053B1 (en) 1989-12-08

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