JP3444667B2 - Variable gain amplifier circuit - Google Patents
Variable gain amplifier circuitInfo
- Publication number
- JP3444667B2 JP3444667B2 JP20561394A JP20561394A JP3444667B2 JP 3444667 B2 JP3444667 B2 JP 3444667B2 JP 20561394 A JP20561394 A JP 20561394A JP 20561394 A JP20561394 A JP 20561394A JP 3444667 B2 JP3444667 B2 JP 3444667B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- signal
- differential
- circuit
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、光通信の信号伝送にお
ける信号受信回路等で用いられるゲイン可変増幅回路に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier circuit used in a signal receiving circuit in signal transmission of optical communication.
【０００２】[0002]
【従来の技術】図２は、従来のゲイン可変増幅回路を示
す回路図である。従来、光通信の信号伝送における信号
受信回路等では、加算型或いは掛算型の回路で代表され
る縦積み２段型の増幅回路が用いられている。図２のゲ
イン可変増幅回路は加算型の回路の例であり、２つの差
動増幅部Ａ１，Ａ２とを、備えている。差動増幅部Ａ１
は、１対の差動信号入力端子ＤＩＰ，ＤＩＮに各ベース
が接続されたｎｐｎ型のバイポーラトランジスタ（以
下、Ｔｒという）１１，１２を有し、各Ｔｒ１１，１２
のコレクタは負荷抵抗１３，１４をそれぞれ介して電源
電位Ｖｃｃに接続されている。各Ｔｒ１１，１２のエミ
ッタはエミッタ抵抗１５，１６を介して互いに接続さ
れ、それらの抵抗１５，１６の接続ノードは差動増幅部
Ａ１に流れる電流を制御するＴｒ１７のコレクタに接続
されている。Ｔｒ１７のエミッタは抵抗１８の一方の端
子に接続されている。同様に、差動増幅部Ａ１は、１対
の差動信号入力端子ＤＩＰ，ＤＩＮに各ベースが接続さ
れたＴｒ２１，２２を有し、各Ｔｒ２１，２２のコレク
タは負荷抵抗１３，１４をそれぞれ介して電源電位Ｖｃ
ｃに接続されている。即ち、抵抗１３，１４はＴｒ１
１，１２及びＴｒ２１，２２の共用された負荷抵抗とな
っている。各Ｔｒ２１，２２のエミッタはエミッタ抵抗
２３，２４を介して互いに接続され、それらの抵抗２
３，２５の接続ノードは差動増幅部Ａ２に流れる電流を
制御するＴｒ２５のコレクタに接続されている。Ｔｒ２
５のエミッタは抵抗２６の一方の端子に接続されてい
る。抵抗１８の他方の端子と抵抗２６の他方の端子は互
いに接続され、その接続ノードが電流源３０を介して接
地電位Ｖｅｅに接続されている。Ｔｒ１７，２５には、
ゲイン制御信号を入力する１対のゲイン制御端子ＶＡ
Ｐ，ＶＡＮがそれぞれ接続され、ゲイン制御端子ＶＡ
Ｐ，ＶＡＮの電位に応じて、差動増幅部Ａ１，Ａ２に流
れる電流が制御される構成である。また、このゲイン可
変増幅回路の１対の差動出力端子ＤＯＰ，ＤＯＮは、各
抵抗１３，１４とＴｒ１１，１２のコレクタの接続ノー
ドＮ１１，Ｎ１２に接続されている。2. Description of the Related Art FIG. 2 is a circuit diagram showing a conventional variable gain amplifier circuit. Conventionally, in the signal receiving circuit and the like in the signal transmission of the optical communication, the amplifier circuit of the vertically stacked two-stage represented by the circuit of the addition type or multiplicative is found using. The variable gain amplifier circuit of FIG. 2 is an example of an addition type circuit, and includes two differential amplifier units A1 and A2. Differential amplifier A1
Has npn-type bipolar transistors (hereinafter referred to as Tr) 11 and 12 whose bases are connected to a pair of differential signal input terminals DIP and DIN, respectively.
Is connected to the power supply potential Vcc via the load resistors 13 and 14, respectively. The emitters of the Trs 11 and 12 are connected to each other via emitter resistors 15 and 16, and the connection node of the resistors 15 and 16 is connected to the collector of Tr 17 which controls the current flowing in the differential amplifier A1. The emitter of Tr17 is connected to one end <br/> terminal of resistor 18. Similarly, the differential amplifier A1 has Tr21 and 22 whose bases are connected to a pair of differential signal input terminals DIP and DIN, respectively, and the collectors of the Tr21 and 22 are connected via load resistors 13 and 14, respectively. Power supply potential Vc
connected to c. That is, the resistors 13 and 14 are Tr1
1, 12 and Tr 21, 22 are shared load resistors. The emitters of the Trs 21 and 22 are connected to each other via the emitter resistors 23 and 24, and the resistors 2 and
The connection nodes of 3, 25 are connected to the collector of Tr25 which controls the current flowing through the differential amplifier A2. Tr2
5 of the emitter is connected to one terminal of the resistor 26. The other terminal of the other terminal of the resistor 18 and the resistor 26 are connected to each other, and the connection node is connected via a current source 30 to the ground potential Vee. For Tr17 and 25,
A pair of gain control terminals VA for inputting gain control signals
P and VAN are connected to each other, and gain control terminal VA
The current flowing through the differential amplifiers A1 and A2 is controlled according to the potentials of P and VAN. The pair of differential output terminals DOP and DON of this variable gain amplifier circuit are connected to the connection nodes N11 and N12 of the resistors 13 and 14 and the collectors of the Trs 11 and 12, respectively.
【０００３】次に、図２のゲイン可変増幅回路の動作を
説明する。入力信号の振幅に相当する電位が差動信号入
力端子ＤＩＰ，ＤＩＮに与えられると、Ｔｒ１１，１
２，２１，２２の導通状態が変化し、また、ゲイン制御
信号がゲイン制御端子ＶＡＰ，ＶＡＮに与えられること
によって、２個のＴｒ１７，２５の導通状態が変化す
る。図３は、図２におけるゲイン特性を示す図である。
ここで、各抵抗１５，１６，２３，２４の抵抗値Ｒ15，
Ｒ16，Ｒ23，Ｒ24を
Ｒ15＝Ｒ16＜＜Ｒ23＝Ｒ24
とすると、ゲイン制御端子ＶＡＰ，ＶＡＮの電位に応じ
て差動増幅部Ａ１，Ａ２に流れる電流が変化すること
で、ゲインが変化する。例えば、ゲイン制御端子ＶＡＰ
の電位によってゲインは、図３のように変化する。その
ため、入力端子ＤＩＰ，ＤＩＮから入力された信号は、
このときのゲインに応じた振幅電圧で差動出力端子ＤＯ
Ｐ，ＤＯＮから出力される。Next, the operation of the variable gain amplifier circuit of FIG. 2 will be described. When a potential corresponding to the amplitude of the input signal is applied to the differential signal input terminals DIP, DIN, Tr11, 1
The conduction states of 2, 21, 22 change, and the gain control signal is applied to the gain control terminals VAP, VAN, whereby the conduction states of the two Trs 17, 25 change. FIG. 3 is a diagram showing the gain characteristic in FIG.
Here, the resistance value R 15 , of each resistor 15 , 16 , 23, 24,
When R 16 , R 23 and R 24 are set to R 15 = R 16 << R 23 = R 24 , the currents flowing through the differential amplifiers A 1 and A 2 change according to the potentials of the gain control terminals VAP and VAN. , The gain changes. For example, the gain control terminal VAP
The gain changes as shown in FIG. Therefore, the signals input from the input terminals DIP and DIN are
A differential output terminal DO with an amplitude voltage corresponding to the gain at this time
Output from P and DON.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
ゲイン可変増幅回路では、次のような課題があった。図
２におけるＴｒ１７，２５及び抵抗１８，２６が、差動
増幅部Ａ１，Ａ２の下側に、縦積型の差動増幅部を構成
することになる。ここで、抵抗１３，１５，１８の抵抗
値をＲ13，Ｒ15，Ｒ18、Ｔｒ１１のベース・エミッタ間
電圧をＶBE、電流源３０に流れる電流をＩ30、及び電流
源３０の基準電圧をＶｉとすると、回路動作に必要な最
低電源電圧ＶｃｃM1は次の（１）式となる。
ＶｃｃM1＝１／２Ｉ30（Ｒ13＋Ｒ15＋Ｒ18）＋２ＶBE＋Ｖｉ・・・（１）
そのため、高いゲイン及び広いダイナミックレンジを実
現しようとすると、電源電位Ｖｃｃを高くする必要があ
り、低電圧化及び低消費電力化が困難であった。また、
ゲイン制御端子ＶＡＰ，ＶＡＮに雑音が侵入すると、雑
音が直接出力信号に影響を与えてＳ／Ｎ比を悪化させる
という課題もあった。However, the conventional variable gain amplifier circuit has the following problems. The Trs 17 and 25 and the resistors 18 and 26 in FIG. 2 form a vertical differential amplifier under the differential amplifiers A1 and A2. Here, the resistance values of the resistors 13 , 15 , and 18 are R 13 , R 15 , and R 18 , the base-emitter voltage of Tr11 is V BE , the current flowing through the current source 30 is I 30 , and the reference voltage of the current source 30. Is V i , the minimum power supply voltage Vcc M1 required for circuit operation is given by the following equation (1). Vcc M1 = 1 / 2I 30 (R 13 + R 15 + R 18 ) + 2V BE + V i (1) Therefore, in order to realize high gain and wide dynamic range, it is necessary to increase the power supply potential Vcc, and It was difficult to reduce voltage and power consumption. Also,
If noise enters the gain control terminals VAP and VAN, the noise directly affects the output signal and deteriorates the S / N ratio.
【０００５】[0005]
【課題を解決するための手段】第１の発明は、前記課題
を解決するために、次のような構成の第１の差動増幅
部、第２の差動増幅部、ダミー回路、及び帰還手段をゲ
イン可変増幅回路に設けている。第１の差動増幅部は、
第１及び第２電極とその第１及び第２電極間の導通状態
を制御する制御電極とを持ち該第１電極同士が接続され
てそれぞれ差動動作を行う第１及び第２のトランジスタ
と、前記各第１及び第２のトランジスタの第２電極と電
源間にそれぞれ接続された第１及び第２の負荷抵抗と、
前記第１及び第２のトランジスタの第１電極の接続ノー
ドと接地間に接続されゲイン制御信号に基づいた電流を
該第１及び第２のトランジスタを介して前記第１及び第
２の負荷抵抗へ送出する第１の電流源とを有し、差動信
号入力端子を介して前記各制御電極に与えられた入力信
号を差動増幅した出力信号を生成する構成としている。
第２の差動増幅部は、前記第１及び第２電極と制御電極
とを持ち該第１電極同士が接続され該各第２電極が前記
第１及び第２の負荷抵抗を介して電源に接続されかつ該
制御電極には所定の電位が与えられた第３及び第４のト
ランジスタと、帰還信号に基づき制御され前記第３及び
第４のトランジスタに流れる電流を送出する第２の電流
源とを有し、前記出力信号のバイアス電位を設定する機
能を有している。ダミー回路は、前記ゲイン制御信号に
基づいた電流を流す電流路を有し、該電流路の電流で前
記第１の差動増幅部に流れる電流を監視するものであ
り、帰還手段は、前記電流路に流れる電流を一定とする
帰還信号を生成し前記ダミー回路に帰還すると共に前記
第２の電流源に帰還する構成としている。In order to solve the above-mentioned problems, a first aspect of the present invention is directed to a first differential amplifier section, a second differential amplifier section, a dummy circuit, and a feedback circuit having the following configurations. Means are provided in the variable gain amplifier circuit. The first differential amplification section is
First and second transistors having first and second electrodes and a control electrode for controlling a conduction state between the first and second electrodes, the first electrodes being connected to each other and performing a differential operation, respectively. First and second load resistors respectively connected between the second electrodes of the first and second transistors and a power source,
Said first and second transistor first electrode of the connecting node between the current based on the connected gain control signal between the ground first and second transistors to the first and second load resistance via the and a first current source for output transmission, and an input signal applied to the respective control electrodes via the differential signal input terminals configured to generate an output signal differential amplifier.
The second differential amplifying unit has the first and second electrodes and a control electrode, the first electrodes are connected to each other, and the second electrodes are connected to the power source via the first and second load resistors. Third and fourth transistors connected to the control electrode, to which a predetermined potential is applied, and a second current source which is controlled based on a feedback signal and sends out a current flowing through the third and fourth transistors. And has a function of setting the bias potential of the output signal. The dummy circuit has a current path through which a current based on the gain control signal flows, and monitors the current flowing through the first differential amplifier section with the current in the current path. A feedback signal that keeps the current flowing in the path constant is generated, fed back to the dummy circuit, and fed back to the second current source.
【０００６】第２の発明は、第１の発明における第１及
び第２のトランジスタと第１及び第２の負荷抵抗と、前
記第１及び第２のトランジスタの第１電極の接続ノード
と接地間に接続されて帰還信号に基づいた電流を前記第
１及び第２のトランジスタに送出する第１の電流源とを
有し、１対の差動信号入力端子を介して前記各制御電極
に与えられた入力信号を差動増幅した出力信号を生成す
る第１の差動増幅部と、第１の発明における第３及び第
４のトランジスタと、ゲイン制御信号に基づき制御され
前記第３及び第４のトランジスタに流れる電流を送出す
る第２の電流源とを有し、前記出力信号のバイアス電位
を設定する第２の差動増幅部とを、ゲイン可変増幅回路
に備えている。さらに、このゲイン可変増幅回路は、第
１の発明におけるの電流路を有し、該電流路の電流で前
記第２の差動増幅部に流れる電流を監視するダミー回路
と、前記電流路に流れる電流を一定とする帰還信号を生
成し前記ダミー回路に帰還すると共に前記第１の電流源
に帰還する帰還手段とを、設けている。 A second invention is between the first and second transistors of the first invention, the first and second load resistors, the connection node of the first electrodes of the first and second transistors, and the ground. A first current source connected to the first current source for sending a current based on a feedback signal to the first and second transistors, and supplied to each of the control electrodes via a pair of differential signal input terminals. A differential amplifier that differentially amplifies the input signal to generate an output signal, the third and fourth transistors in the first invention, and the third and fourth transistors controlled based on a gain control signal. A variable gain amplifier circuit is provided with a second differential amplifier section that has a second current source that sends out a current flowing through the transistor and that sets a bias potential of the output signal. Furthermore, this variable gain amplifier circuit has the current path of the first aspect of the invention, a dummy circuit that monitors the current flowing through the second differential amplifier section with the current of the current path, and a current flowing through the current path. a feedback means for feeding back to said first current source with generates a feedback signal to the current constant is fed back to the dummy circuit, that are provided.
【０００７】[0007]
【作用】第１の発明によれば、以上のようにゲイン可変
増幅回路を構成したので、第１の差動増幅部中の第１及
び第２のトランジスタがそれぞれ差動動作を行い、差動
信号入力端子を介して入力され入力信号を差動増幅した
出力信号を生成する。このときのゲインはゲイン制御信
号に基づく第１の電流源の送出電流で設定される。ま
た、第２の差動増幅部中の第２の電流源は帰還信号に対
応した電流を送出し、第２の差動増幅部が出力信号にお
けるバイアス電位を設定する。ダミー回路は、ゲイン制
御信号に基づいた電流を流す電流路を有し、その電流路
の電流で第１の差動増幅部に流れる電流を監視し、帰還
手段が、その電流を一定とする帰還信号を生成してダミ
ー回路に帰還すると共に第２の電流源に帰還する。これ
により、ゲイン制御信号の変化に対する負帰還がかか
り、出力信号のバイアス電位の変化が補償されて一定と
なる。According to the first aspect of the invention, since the variable gain amplifying circuit is configured as described above, the first and second transistors in the first differential amplifying section respectively perform a differential operation, and a differential operation is performed. An output signal is generated by differentially amplifying the input signal input through the signal input terminal. The gain at this time is set by the sending current of the first current source based on the gain control signal. The second current source in the second differential amplifier section sends out a current corresponding to the feedback signal, and the second differential amplifier section sets the bias potential in the output signal. The dummy circuit has a current path through which a current based on the gain control signal flows, and the current in the current path monitors the current flowing through the first differential amplifier section, and the feedback means feedbacks the current to a constant value. A signal is generated and fed back to the dummy circuit and fed back to the second current source. As a result, negative feedback is applied to changes in the gain control signal, and changes in the bias potential of the output signal are compensated and become constant.
【０００８】第２の発明によれば、第１の差動増幅部中
の第１及び第２のトランジスタがそれぞれ差動動作を行
い、差動信号入力端子を介して入力され入力信号を差動
増幅した出力信号を生成する。ゲインを変化させるゲイ
ン制御信号が第２の差動増幅部中の第２の電流源に与え
られ、その第２の電流源はゲイン制御信号に対応した電
流を送出する。これにより、出力信号のバイアス電位が
設定されると共にゲインが設定される。ダミー回路は、
電流路の電流で第１の差動増幅部に流れる電流を監視
し、帰還手段が、その電流を一定とする帰還信号を生成
してダミー回路に帰還すると共に第１の電流源に帰還す
る。これにより、ゲイン制御信号の変化に対する負帰還
がかかり、第１の電流源は負帰還に応じた電流を送出
し、出力信号のバイアス電位の変化が補償されて一定と
なる。 According to the second aspect of the invention, the first and second transistors in the first differential amplifier section respectively perform a differential operation and differentially input the input signal through the differential signal input terminal. Generate an amplified output signal. A gain control signal for changing the gain is given to a second current source in the second differential amplifier section, and the second current source sends out a current corresponding to the gain control signal. As a result, the bias potential of the output signal is set and the gain is set. The dummy circuit is
The current flowing through the first differential amplifier is monitored by the current in the current path, and the feedback means generates a feedback signal that keeps the current constant, feeds it back to the dummy circuit, and feeds it back to the first current source. Thus, it takes a negative feedback with respect to the change of the gain control signal, the first current source sends out a current corresponding to the negative feedback, constant and <br/> ing changes in the bias potential of the output signal is compensated.
【０００９】[0009]
【実施例】（ 第１の実施例）
図１は、本発明の第１の実施例を示すゲイン可変増幅回
路の回路図である。この回路は、入力信号の差動増幅を
行う第１の差動増幅部Ａ３と，差動増幅部Ａ３に接続さ
れ、１対の差動出力端子ＤＯＰ，ＤＯＮのバイアス電位
を制御する第２の差動増幅部Ａ４とを備えている。ま
た、差動増幅部Ａ３には、差動増幅部Ａ３に流れる電流
を監視するダミー回路Ｄ１が併設され、そのダミー回路
Ｄ１には帰還信号を送出してダミー回路Ｄ１に流れる電
流を一定にすると共に差動増幅部Ａ４に流れる電流を制
御する帰還手段Ｆ１が接続されている。差動増幅部Ａ３
は、１対の差動信号入力端子ＤＩＰ，ＤＩＮに制御電極
である各ベースがそれぞれ接続された第１及び第２のト
ランジスタであるＴｒ３１，３２を有し、各Ｔｒ３１，
３２の第２電極であるコレクタは負荷抵抗３３，３４を
それぞれ介して電源電位Ｖｃｃに接続されている。各Ｔ
ｒ３１，３２のエミッタはエミッタ抵抗３５，３６を介
して互いに接続され、それらの抵抗３５，３６の接続ノ
ードは第１の電流源である電流源３７に接続されてい
る。電流源３７はゲイン制御端子ＶＡに与えられたゲイ
ン制御信号の電位に基づいた電流をこの差動増幅部Ａ
３、即ち、Ｔｒ３１，３２及び負荷抵抗３３，３４に流
す構成となっいる。 ( First Embodiment ) FIG. 1 is a circuit diagram of a variable gain amplifier circuit showing a first embodiment of the present invention. This circuit is connected to a first differential amplification section A3 for differentially amplifying an input signal and a second differential amplification section A3 for controlling a bias potential of a pair of differential output terminals DOP and DON. And a differential amplifier A4. Further, the differential amplifier A3 is provided with a dummy circuit D1 for monitoring the current flowing through the differential amplifier A3, and a feedback signal is sent to the dummy circuit D1 to make the current flowing through the dummy circuit D1 constant. A feedback unit F1 for controlling the current flowing through the differential amplifier A4 is also connected. Differential amplifier A3
Has a pair of differential signal input terminals DIP, a first and second transistors each base Ru control electrode der to DIN are connected respectively Tr31,32, each Tr31,
The collector of the second electrode 32 is connected to the power supply potential Vcc via the load resistors 33 and 34, respectively. Each T
The emitters of r31 and 32 are connected to each other via emitter resistors 35 and 36, and the connection node of these resistors 35 and 36 is connected to a current source 37 which is a first current source. The current source 37 supplies a current based on the potential of the gain control signal applied to the gain control terminal VA to the differential amplifier A.
3, i.e., Tr31, 32 and load resistors 33, 34.
【００１０】差動増幅部Ａ４は、共通の電位Ｖｒ１に各
ベースが接続された第３及び第４のトランジスタである
Ｔｒ４１，４２を有し、各Ｔｒ４１，４２のコレクタは
負荷抵抗３３，３４をそれぞれ介して電源電位Ｖｃｃに
接続されている。即ち、抵抗３３，３４はＴｒ３１，３
２の負荷抵抗であると共にＴｒ４１，４２の負荷抵抗に
もなっている。各Ｔｒ４１，４２のエミッタはエミッタ
抵抗４３，４４を介して互いに接続され、それらの抵抗
４３，４４の接続ノードは第２の電流源である電流源４
５を介して接地電位Ｖｅｅに接続されている。ダミー回
路Ｄ１は、ゲイン制御端子ＶＡに与えられた電位を検出
して対応する電流を送出する電流源５１と、その電流源
５１と電源電位Ｖｃｃ間に接続された負荷抵抗５２とで
構成された電流路とを有し、さらに、負荷抵抗５２と電
流源５１の接続ノードＮ１に対して電流源５１と並列に
接続されて帰還電圧に基づいた電流を送出する電流源５
３を、備えている。帰還手段Ｆ１は、ノードＮ１の電位
を検出してダミー回路Ｄ１に流れる電流を一定とするよ
うに電流源５３に帰還電圧信号を送出すると共に、その
帰還電圧信号を電流源４５に与える演算増幅器（以下、
オペアンプという）６１を有している。このオペアンプ
６１には、帰還信号を生成するための参照電位Ｖｒ２が
接続されている。The differential amplifier A4 has Tr41 and 42 which are third and fourth transistors whose bases are connected to a common potential Vr1. The collectors of the Tr41 and 42 have load resistors 33 and 34, respectively. It is connected to the power supply potential Vcc via each. That is, the resistors 33 and 34 are the same as Tr31 and
In addition to being the load resistance of No. 2, it is also the load resistance of the Tr 41, 42. The emitters of the Trs 41 and 42 are connected to each other via emitter resistors 43 and 44, and the connection node of the resistors 43 and 44 is the current source 4 which is the second current source.
It is connected to the ground potential Vee via 5. The dummy circuit D1 is composed of a current source 51 that detects the potential applied to the gain control terminal VA and sends out a corresponding current, and a load resistor 52 that is connected between the current source 51 and the power source potential Vcc. A current source 5 which has a current path and which is connected in parallel to the current source 51 with respect to the connection node N1 of the load resistor 52 and the current source 51 and sends out a current based on the feedback voltage.
3 is provided. The feedback means F1 detects the potential of the node N1 and sends a feedback voltage signal to the current source 53 so as to make the current flowing through the dummy circuit D1 constant, and at the same time, an operational amplifier (which supplies the feedback voltage signal to the current source 45 ( Less than,
61). This op amp
Reference voltage Vr2 for generating a feedback signal is connected to 61 .
【００１１】次に、図１のゲイン可変増幅回路の動作を
説明する。差動増幅部Ａ３の各Ｔｒ３１，３２は、入力
信号に対する差動動作を行い、各Ｔｒ３１，３２のコレ
クタの電位が出力端子ＤＯＰ，ＤＯＮから出力信号とし
て出力される。一方、差動増幅部Ａ４では、電流源４５
の送出する電流に応じた電流を抵抗３３，３４に流す。
そのため、Ｔｒ３１，３２のコレクタの電位が制御さ
れ、出力信号のバイアス電位が設定される。ここで、ゲ
イン制御端子ＶＡの電位、即ちゲイン制御信号を変化さ
せると、その電位の変化量によって電流源３７の送出す
る電流Ｉ37が変化し、差動増幅部Ａ３に流れる電流が変
化する。そのため、各Ｔｒ３１，３２のコレクタの電位
がそれぞれ変化し、出力端子ＤＯＰ，ＤＯＮの電位差が
対応して変化する。即ち、ゲイン制御端子ＶＡの電位を
変化させることで、入力信号に対するゲインを可変とす
ることができる。また、ゲイン制御端子ＶＡの電位が変
化すると、電流源５１の出力する電流Ｉ51も電流Ｉ37に
比例して変化する。そのため、ノードＮ１の電位が変化
する。ここで、帰還手段Ｆ１のオペアンプ６１は、ノー
ドＮ１の電位が一定となるように、電流源５３及び電流
源４５に対する帰還信号を生成して負帰還をかける。こ
の負帰還によって電流源４５の送出する電流が変化し、
ゲイン制御信号の変化で生じた出力信号のバイアス電位
の変化を補償する。即ち、図１のゲイン可変増幅回路は
出力端子ＤＯＰ，ＤＯＮのバイアス電圧を変動させるこ
となく、ゲイン制御端子ＶＡの電位に応じたゲインを得
ることができる。Next, the operation of the variable gain amplifier circuit of FIG. 1 will be described. The Trs 31 and 32 of the differential amplifier A3 perform a differential operation with respect to the input signal, and the potentials of the collectors of the Trs 31 and 32 are output as output signals from the output terminals DOP and DON. On the other hand, in the differential amplifier A4, the current source 45
An electric current corresponding to the electric current sent by the device is passed through the resistors 33 and 34.
Therefore, the potentials of the collectors of the Trs 31 and 32 are controlled and the bias potential of the output signal is set. Here, when the potential of the gain control terminal VA, that is, the gain control signal is changed, the current I 37 sent from the current source 37 changes according to the amount of change in the potential, and the current flowing through the differential amplifier A3 changes. Therefore, the potentials of the collectors of the Trs 31 and 32 change, and the potential difference between the output terminals DOP and DON changes correspondingly. That is, the gain for the input signal can be made variable by changing the potential of the gain control terminal VA. When the potential of the gain control terminal VA changes, the current I 51 output from the current source 51 also changes in proportion to the current I 37 . Therefore, the potential of the node N1 changes. Here, the operational amplifier 61 of the feedback means F1 generates a feedback signal to the current source 53 and the current source 45 so as to make the potential of the node N1 constant, and applies negative feedback. This negative feedback changes the current sent by the current source 45,
The change in the bias potential of the output signal caused by the change in the gain control signal is compensated. That is, the variable gain amplifier circuit of FIG. 1 can obtain a gain according to the potential of the gain control terminal VA without changing the bias voltage of the output terminals DOP and DON.
【００１２】ここで、本実施例の回路動作に必要な最低
電源電圧Ｖｃｃ M2 は、抵抗３３，３５の抵抗値をＲ33，
Ｒ35、Ｔｒ３１のベース・エミッタ間電圧をＶBE 、電流
源３７に流れる電流をＩ37、及び電流源３７の基準電圧
をＶｉとすると、回路動作に必要な最低電源電圧Ｖｃｃ
M2は次の（２）式となる。
ＶｃｃM2＝１／２Ｉ37（Ｒ33＋Ｒ35）＋ＶBE＋Ｖｉ ・・・（２）
従来の（１）式と比較をするために、Ｉ30＝Ｉ37、Ｒ13
＝Ｒ33、及びＲ15＝Ｒ35とすると、次の（３）式の電圧
Ｖｃ1 分、最低電源電圧Ｖｃｃ M2 が下げられる。
Ｖｃ1 ＝ＶｃｃM1−ＶｃｃM2＝１／２Ｉ30Ｒ18＋ＶBE ・・・（３）
以上のように、本実施例では、ゲイン可変増幅回路の構
成を従来のように差動増幅部を縦積することなく実現で
きる。そのため、低い電源電圧で動作可能なゲイン可変
増幅回路を構成でき、低消費電力化と低コスト化を実現
できる。Here, the minimum power supply voltage Vcc M2 required for the circuit operation of this embodiment is the resistance value of the resistors 33 and 35 is R 33 ,
Assuming that the base-emitter voltage of R 35 and Tr 31 is V BE , the current flowing in the current source 37 is I 37 , and the reference voltage of the current source 37 is V i , the minimum power supply voltage Vcc required for circuit operation is Vcc.
M2 becomes the following formula (2). Vcc M2 = 1/2 I 37 (R 33 + R 35 ) + V BE + V i (2) In order to compare with the conventional formula (1), I 30 = I 37 , R 13
= R 33 and R 15 = R 35 , the minimum power supply voltage Vcc M2 can be lowered by the voltage Vc1 in the following equation (3). Vc1 = Vcc M1 -Vcc M2 = 1 / 2I 30 R 18 + V BE ··· (3) As described above, in this embodiment, vertical stack a differential amplifier so that the configuration of a conventional variable gain amplifier circuit Can be realized without doing. Therefore, a variable gain amplifier circuit that can operate with a low power supply voltage can be configured, and low power consumption and low cost can be realized.
【００１３】（第２の実施例）
図４は、本発明の第２の実施例を示すゲイン可変増幅回
路の回路図である。この回路は、入力信号の差動増幅を
行う第１の差動増幅部Ａ５と，差動増幅部Ａ５に接続さ
れ、１対の差動出力端子ＤＯＰ，ＤＯＮのバイアス電位
を制御する第２の差動増幅部Ａ６とを備えている。ま
た、差動増幅部Ａ６には、差動増幅部Ａ５に流れる電流
を監視するダミー回路Ｄ２が併設され、そのダミー回路
Ｄ２には、帰還信号を送出してダミー回路Ｄ２に流れる
電流を一定にすると共に差動増幅部Ａ５に流れる電流を
制御する帰還手段Ｆ２が接続されている。差動増幅部Ａ
５は、１対の差動信号入力端子ＤＩＰ，ＤＩＮに各ベー
スが接続された第１及び第２のトランジスタであるＴｒ
７１，７２を有し、各Ｔｒ７１，７２のコレクタは、負
荷抵抗７３，７４をそれぞれ介して電源電位Ｖｃｃに接
続されている。各Ｔｒ７１，７２のエミッタはエミッタ
抵抗７５，７６を介して互いに接続され、それらの抵抗
７５，７６の接続ノードは第１の電流源である電流源７
７に接続されている。電流源７７は帰還信号に基づいた
電流をこの差動増幅部Ａ５、即ちＴｒ７１，７２及び負
荷抵抗７３，７４に流す構成となっている。 ( Second Embodiment ) FIG. 4 is a circuit diagram of a variable gain amplifier circuit showing a second embodiment of the present invention. This circuit is connected to a first differential amplification section A5 that performs differential amplification of an input signal and a second differential amplification section A5 that controls a bias potential of a pair of differential output terminals DOP and DON. And a differential amplifier A6. Further, the differential amplifier A6 is provided with a dummy circuit D2 for monitoring the current flowing through the differential amplifier A5, and a feedback signal is sent to the dummy circuit D2 to make the current flowing through the dummy circuit D2 constant. In addition, feedback means F2 for controlling the current flowing through the differential amplifier A5 is connected. Differential amplifier A
Reference numeral 5 denotes Tr, which is a first and second transistor whose bases are connected to a pair of differential signal input terminals DIP and DIN.
71 and 72, and the collectors of the respective Trs 71 and 72 are connected to the power supply potential Vcc through the load resistors 73 and 74, respectively. The emitters of the Trs 71 and 72 are connected to each other via emitter resistors 75 and 76, and the connection node of the resistors 75 and 76 is the current source 7 which is the first current source.
Connected to 7. Current source 77 has a configuration in which electric current based on the feedback signal the differential amplifier A5, i.e. the Tr71,72 and load resistor 73, 74.
【００１４】差動増幅部Ａ６は、共通の電位Ｖｒ３に各
ベースが接続された第３及び第４のトランジスタである
Ｔｒ８１，８２を有し、各Ｔｒ８１，８２のコレクタは
負荷抵抗７３，７４をそれぞれ介して電源電位Ｖｃｃに
接続されている。即ち、抵抗７３，７４はＴｒ７１，７
２の負荷抵抗であると共にＴｒ８１，８２の負荷抵抗に
もなっている。各Ｔｒ８１，８２のエミッタはエミッタ
抵抗８３，８４を介して互いに接続され、それらの抵抗
８３，８４の接続ノードは第２の電流源である電流源８
５を介して接地電位Ｖｅｅに接続されている。電流源８
５はゲイン制御端子ＶＡに与えられたゲイン制御信号の
電位に基づいた電流をこの差動増幅部Ａ６、即ち、Ｔｒ
８１，８２に流す構成となっている。ダミー回路Ｄ２
は、ゲイン制御端子ＶＡに与えられた電位を検出して対
応する電流を送出する電流源９１と、その電流源９１と
電源電位Ｖｃｃ間に接続された負荷抵抗９２とで、構成
された電流路を有し、さらに負荷抵抗９２と電流源９１
の接続ノードＮ２に対して電流源９１と並列に接続され
て帰還電圧に基づいた電流を送出する電流源９３を、備
えている。帰還手段Ｆ２は、ノードＮ２の電位を検出し
てダミー回路Ｄ２に流れる電流を一定とするように電流
源９３に帰還電圧信号を送出すると共に、その帰還電圧
信号を電流源７７に与えるオペアンプ１０１を有してい
る。このオペアンプ１０１には、帰還信号を生成するた
めの参照電位Ｖｒ４が接続されている。The differential amplifier A6 has Tr81 and 82 which are third and fourth transistors whose bases are connected to a common potential Vr3, and the collectors of the Tr81 and 82 have load resistors 73 and 74, respectively. It is connected to the power supply potential Vcc via each. That is, the resistors 73 and 74 are the Tr 71 and 7
In addition to being the load resistance of No. 2, it is also the load resistance of the Tr 81, 82. The emitters of the Trs 81 and 82 are connected to each other via emitter resistors 83 and 84, and the connection node of the resistors 83 and 84 is the current source 8 that is the second current source.
It is connected to the ground potential Vee via 5. Current source 8
Reference numeral 5 denotes a current based on the potential of the gain control signal applied to the gain control terminal VA, which is supplied to the differential amplifier A6, that is, Tr.
It is configured to flow to 81 and 82. Dummy circuit D2
Is a current path configured by a current source 91 that detects the potential applied to the gain control terminal VA and sends out a corresponding current, and a load resistor 92 that is connected between the current source 91 and the power source potential Vcc. With a load resistor 92 and a current source 91.
And a current source 93 that is connected in parallel to the current source 91 with respect to the connection node N2 and sends out a current based on the feedback voltage. The feedback means F2 detects the potential of the node N2 and sends a feedback voltage signal to the current source 93 so as to make the current flowing through the dummy circuit D2 constant, and at the same time, an operational amplifier 101 which gives the feedback voltage signal to the current source 77. Have A reference potential Vr4 for generating a feedback signal is connected to the operational amplifier 101.
【００１５】次に、図４のゲイン可変増幅回路の動作を
説明する。差動増幅部Ａ５のＴｒ７１，７２は、入力信
号に対する差動動作を行い、Ｔｒ７１，７２のコレクタ
の電位が出力端子ＤＯＰ，ＤＯＮから出力信号として出
力される。一方、差動増幅部Ａ６では、電流源８５の送
出する電流Ｉ85に応じた電流を抵抗７３，７４に流す。
そのため、Ｔｒ７１，７２のコレクタの電位が変化し、
出力信号のバイアス電位が設定される。ここで、ゲイン
制御端子ＶＡの電位、即ちゲイン制御信号を変化させる
と、その電位の変化量によって電流源８５の送出する電
流Ｉ85が変化し、差動増幅部Ａ６に流れる電流が変化す
る。そのため、各Ｔｒ７１，７２のコレクタの電位がそ
れぞれ変化し、出力端子ＤＯＰ，ＤＯＮの電位差が対応
して変化する。即ち、ゲイン制御端子ＶＡの電位を駆動
して変化させることで、本実施例においても入力信号に
対するゲインを可変とすることができる。また、ゲイン
制御端子ＶＡの電位が変化すると、電流源９１の出力す
る電流Ｉ91も差動増幅部Ａ５に流れる電流に比例して変
化する。そのため、ノードＮ２の電位が変化する。ここ
で、帰還手段Ｆ１のオペアンプ１０１は、ノードＮ２の
電位が一定となるように、電流源９３及び電流源７７に
対する帰還信号を生成して負帰還をかける。この負帰還
によって電流源７７の送出する電流が変化し、ゲイン制
御信号ＶＡの変化で生じた出力信号の変化を補償する。
即ち、図４のゲイン可変増幅回路は出力端子ＤＯＰ，Ｄ
ＯＮのバイアス電圧を変動させることなく、ゲイン制御
端子ＶＡの電位に応じたゲインを得ることができる。以
上のように、本実施例ではゲインを可変にするゲイン制
御信号を電流源８５に与えるようにしているので、例え
ば、半導体集積回路（以下、ＩＣという）でゲイン可変
増幅回路を構成した場合において、ゲイン制御端子ＶＡ
を駆動する回路と本回路を別々のブロックにしても、配
線等から入るゲイン制御端子ＶＡの雑音が差動増幅を行
う差動増幅部Ａ５に与える影響を、第１の実施例に対し
て小さくすることができる。これにより、さらにＳ／Ｎ
比を改善することができる。Next, the operation of the variable gain amplifier circuit of FIG. 4 will be described. The Trs 71 and 72 of the differential amplifier A5 perform a differential operation with respect to the input signal, and the potentials of the collectors of the Trs 71 and 72 are output as output signals from the output terminals DOP and DON. On the other hand, in the differential amplifier A6, a current corresponding to the current I 85 sent from the current source 85 is passed through the resistors 73 and 74.
Therefore, the collector potential of Tr71 and 72 changes,
The bias potential of the output signal is set. Here, when the potential of the gain control terminal VA, that is, the gain control signal is changed, the current I 85 sent by the current source 85 changes according to the amount of change in the potential, and the current flowing through the differential amplifier A6 changes. Therefore, the potentials of the collectors of the Trs 71 and 72 change, and the potential difference between the output terminals DOP and DON changes correspondingly. That is, by driving and changing the potential of the gain control terminal VA, the gain for the input signal can be made variable also in this embodiment. Further, when the potential of the gain control terminal VA changes, the current I 91 output from the current source 91 also changes in proportion to the current flowing through the differential amplifier A5. Therefore, the potential of the node N2 changes. Here, the operational amplifier 101 of the feedback means F1 generates a feedback signal to the current source 93 and the current source 77 so as to make the potential of the node N2 constant, and applies negative feedback. This negative feedback changes the current sent from the current source 77, and compensates for the change in the output signal caused by the change in the gain control signal VA.
That is, the variable gain amplifier circuit of FIG. 4 has output terminals DOP and DOP.
It is possible to obtain a gain according to the potential of the gain control terminal VA without changing the ON bias voltage. As described above, in the present embodiment, the gain control signal for varying the gain is applied to the current source 85. Therefore, for example, in the case where the semiconductor integrated circuit (hereinafter referred to as IC) constitutes the variable gain amplifier circuit. , Gain control terminal VA
Even if the circuit for driving the circuit and this circuit are provided as separate blocks, the influence of the noise of the gain control terminal VA that enters from the wiring or the like on the differential amplification unit A5 that performs differential amplification is reduced compared to the first embodiment. can do. As a result, the S / N
The ratio can be improved.
【００１６】（第１の参考例）
図５は、本発明の第１の参考例を示すゲイン可変増幅回
路の回路図であり、第１の実施例と共通する要素には共
通の符号が付されている。このゲイン可変増幅回路は、
図１と同様の構成の第１の差動増幅部Ａ３及び第２の差
動増幅部Ａ４とを備え、第１の実施例とは異なるバイア
ス制御手段Ｂ１を、ダミー回路Ｄ１及び帰還手段Ｆ１の
代わりに設けている。バイアス制御手段Ｂ１は、差動増
幅部Ａ３に流れる電流を直接検出して対応する制御信号
を差動増幅部Ａ４内の電流源４５に帰還する構成となっ
ている。本参考例における差動増幅部Ａ３中の負荷抵抗
３３，３４は、直接電源電位Ｖｃｃに接続されず、抵抗
１１１を介して電源電位Ｖｃｃに接続されている。つま
り、各負荷抵抗３３，３４の一端は、共通に接続ノード
Ｎ３で抵抗１１１に接続されている。ノードＮ３はさら
にバイアス制御手段Ｂ１に接続されている。バイアス制
御手段Ｂ１は、ノードＮ３の電位を一方の入力端子から
入力するオペアンプ１２１を有し、そのオペアンプ１２
１の他方の入力端子には参照電位Ｖｒ６が入力されてい
る。オペアンプ１２１の出力端子が差動増幅部Ａ４の電
流源４５に接続されている。 (First Reference Example) FIG. 5 is a circuit diagram of a variable gain amplifier circuit showing a first reference example of the present invention. Elements common to the first embodiment are designated by common reference numerals. Has been done. This variable gain amplifier circuit
The first differential amplifier A3 and the second differential amplifier A4 having the same configuration as in FIG. 1 are provided, and the bias control unit B1 different from that of the first embodiment is provided in the dummy circuit D1 and the feedback unit F1. It is provided instead. The bias control means B1 is configured to directly detect the current flowing in the differential amplification section A3 and feed back the corresponding control signal to the current source 45 in the differential amplification section A4. The load resistors 33 and 34 in the differential amplifier A3 in this reference example are not directly connected to the power supply potential Vcc, but are connected to the power supply potential Vcc via the resistor 111. That is, one ends of the load resistors 33 and 34 are commonly connected to the resistor 111 at the connection node N3. The node N3 is further connected to the bias control means B1. The bias control means B1 has an operational amplifier 121 that inputs the potential of the node N3 from one input terminal.
The reference potential Vr6 is input to the other input terminal of 1. The output terminal of the operational amplifier 121 is connected to the current source 45 of the differential amplifier A4.
【００１７】次に、図５のゲイン可変増幅回路の動作を
説明する。基本的動作は第１の実施例と同様であり、差
動増幅部Ａ３中の各Ｔｒ３１，３２は入力信号に対する
差動増幅を行い、差動増幅部Ａ４では電流源４５の送出
する電流に応じた電流を抵抗３３，３４に流し、Ｔｒ３
１，３２のコレクタの電位が変化して出力信号のバイア
ス電位が設定される。そのため、ゲイン制御端子ＶＡの
電位を変化させることで、入力信号に対するゲインを可
変とすることができる。ここで、バイアス制御手段Ｂ１
はノードＮ３の電位から直接差動増幅部Ａ３に流れる電
流を検出する。オペアンプ１２１は参照電位Ｖｒ６に基
づいて第１の実施例における帰還信号に対応する制御信
号を生成して電流源４５に送出する。電流源４５はオペ
アンプ１２１からの制御信号に基づいて、出力信号にお
けるバイアス電位の変化を補償する。ここで抵抗１１１
の抵抗値をＲ111 として、第１の実施例と同様に回路動
作に必要な最小電源電圧ＶｃｃM3を求めると、（４）式
のようになる。
ＶｃｃM3＝Ｒ111 Ｉ37＋１／２Ｉ37（Ｒ33＋Ｒ35）＋ＶBE＋Ｖｉ
・・・（４）
また、これを従来の（１）式と比較をすると、次の
（５）式の電圧Ｖｃ2 分、最低電源電圧ＶｃｃM3が下げ
られる。
Ｖｃ2 ＝ＶｃｃM1−ＶｃｃM3＝１／２Ｉ37Ｒ18＋ＶBE−Ｒ111 Ｉ37
・・・（５）
以上のように、本参考例では差動増幅部Ａ３に流れる電
流を、ダミー回路を用いずに直接検出しているので、第
１の実施例に対して回路規模の小さいゲイン可変増幅回
路を構成することができる。そのため、ＩＣのチップ面
積を小さくでき、かつ、消費電力の少ないゲイン可変増
幅回路を実現できる。Next, the operation of the variable gain amplifier circuit shown in FIG. 5 will be described. The basic operation is the same as that of the first embodiment, the Trs 31 and 32 in the differential amplifier A3 perform differential amplification on the input signal, and the differential amplifier A4 responds to the current sent by the current source 45. Current flowing through resistors 33 and 34, and Tr3
The potentials of the collectors of 1, 32 are changed to set the bias potential of the output signal. Therefore, the gain for the input signal can be made variable by changing the potential of the gain control terminal VA. Here, the bias control means B1
Detects a current flowing directly into the differential amplifier A3 from the potential of the node N3. The operational amplifier 121 generates a control signal corresponding to the feedback signal in the first embodiment based on the reference potential Vr6 and sends it to the current source 45. The current source 45 compensates the change in the bias potential in the output signal based on the control signal from the operational amplifier 121. Resistor 111
When the minimum power supply voltage Vcc M3 required for the circuit operation is obtained with the resistance value of R 111 as R 111 , the equation (4) is obtained. Vcc M3 = R 111 I 37 + 1 / 2I 37 (R 33 + R 35 ) + V BE + V i (4) When this is compared with the conventional formula (1), the voltage of the following formula (5) is obtained. The minimum power supply voltage Vcc M3 is lowered by Vc2. Vc2 = Vcc M1 -Vcc M3 = 1/2 I 37 R 18 + V BE -R 111 I 37 (5) As described above, in the present reference example , the current flowing through the differential amplifier A3 uses a dummy circuit. Since it is directly detected without performing the detection, it is possible to configure a variable gain amplifier circuit having a smaller circuit scale than that of the first embodiment. Therefore, the chip area of the IC can be reduced and a variable gain amplifier circuit with low power consumption can be realized.
【００１８】（第２の参考例）
図６は、本発明の第２の参考例を示すゲイン可変増幅回
路の回路図であり、図４と共通する要素には共通の符号
が付されている。このゲイン可変増幅回路は、図４と同
様の構成の第１の差動増幅部Ａ５及び第２の差動増幅部
Ａ６とを備え、第２の参考例と同様のバイアス制御手段
Ｂ２を、ダミー回路Ｄ２及び帰還手段Ｆ２の代わりに設
けている。バイアス制御手段Ｂ２は、差動増幅部Ａ５に
流れる電流を直接検出して対応する制御信号を差動増幅
部Ａ５内の電流源７７に帰還する構成となっている。本
参考例における差動増幅部Ａ５の負荷抵抗７３，７４は
直接電源電位Ｖｃｃに接続されず、抵抗１３１を介して
電源電位Ｖｃｃに接続されている。つまり、各負荷抵抗
７３，７４の一端は、共通に接続ノードＮ４で抵抗１３
１に接続されている。ノードＮ４はさらにバイアス制御
手段Ｂ２に接続されている。バイアス制御回路は、ノー
ドＮ４の電位を一方の入力端子から入力するオペアンプ
１４１を有し、そのオペアンプ１４１の他方の入力端子
には参照電位Ｖｒ８が入力されている。オペアンプ１４
１の出力端子が差動増幅部Ａ５の電流源７７に接続され
ている。 (Second Reference Example) FIG. 6 is a circuit diagram of a variable gain amplifier circuit showing a second reference example of the present invention. Elements common to FIG. 4 are designated by common reference numerals. . This variable gain amplifier circuit includes a first differential amplifier section A5 and a second differential amplifier section A6 having the same configuration as in FIG. 4, and a bias control means B2 similar to that of the second reference example is used as a dummy. It is provided instead of the circuit D2 and the feedback means F2. The bias control means B2 is configured to directly detect the current flowing in the differential amplification section A5 and feed back the corresponding control signal to the current source 77 in the differential amplification section A5. Book
The load resistors 73 and 74 of the differential amplifier A5 in the reference example are not directly connected to the power supply potential Vcc, but are connected to the power supply potential Vcc via the resistor 131. That is, one end of each of the load resistors 73 and 74 is commonly connected to the resistor 13 at the connection node N4.
Connected to 1. The node N4 is further connected to the bias control means B2. The bias control circuit has an operational amplifier 141 that inputs the potential of the node N4 from one input terminal, and the reference potential Vr8 is input to the other input terminal of the operational amplifier 141. Operational amplifier 14
The output terminal of No. 1 is connected to the current source 77 of the differential amplifier A5.
【００１９】このゲイン可変増幅回路における基本動作
は第２の参考例と同様であるが、バイアス制御手段Ｂ２
はノードＮ４の電位から直接差動増幅部Ａ３に流れる電
流を検出し、オペアンプ１４１は参照電位Ｖｒ８に基づ
いた制御信号を生成して電流源７７に帰還する。電流源
７７はオペアンプ１４１からの制御信号に基づいて、出
力信号におけるバイアス電位の変化を補償する。以上の
ように、本参考例では、ゲイン制御端子ＶＡが入力信号
の差動増幅を行う差動増幅部Ａ５に直接接続されていな
いので、ゲイン制御端子ＶＡの電位における配線等から
侵入した雑音の影響を直接受けなくなる。そのため、第
２の参考例でのＳ／Ｎ比をさらに改善することができ
る。なお、本発明は、上記実施例や参考例に限定されず
種々の変形が可能である。例えば、第１、第２の実施例
及び第１、第２の参考例における差動増幅部Ａ３〜Ａ６
の差動用Ｔｒ３１，３２、Ｔｒ４１，４２、Ｔｒ７１，
７２、及びＴｒ８１，８２、のエミッタ同士は抵抗を介
して接続されていたが、直接接続して用いることも可能
である。また、第１、第２の実施例及び第１、第２の参
考例のゲイン増幅回路は、ピークホールド回路等を用い
た負帰還回路を付加することによってオートゲインコン
トロール回路を構成することも可能である。The basic operation of this variable gain amplifier circuit is the same as that of the second reference example , but the bias control means B2 is used.
Detects a current flowing through the differential amplifier A3 directly from the potential of the node N4, and the operational amplifier 141 generates a control signal based on the reference potential Vr8 and feeds it back to the current source 77. The current source 77 compensates the change in the bias potential in the output signal based on the control signal from the operational amplifier 141. As described above, in the present reference example , since the gain control terminal VA is not directly connected to the differential amplification section A5 that differentially amplifies the input signal, noise that has entered from the wiring or the like at the potential of the gain control terminal VA is not generated. Not directly affected. For this reason, the
The S / N ratio in the second reference example can be further improved. The present invention is not limited to the above-mentioned embodiments and reference examples , and various modifications can be made. For example, the first and second embodiments
And the differential amplifiers A3 to A6 in the first and second reference examples .
Differential Tr31, 32, Tr41, 42, Tr71,
Although the emitters of 72 and Tr 81 and 82 are connected to each other via a resistor, they may be directly connected and used. In addition, the first and second embodiments and the first and second reference
Gain amplifier circuit Reference Example, it is possible to configure the automatic gain control circuit by adding a negative feedback circuit using the peak hold circuit or the like.
【００２０】[0020]
【発明の効果】以上詳細に説明したように、第１の発明
によれば、入力信号を差動増幅した出力信号を生成する
第１の差動増幅部とその出力信号のバイアス電位を設定
する第２の差動増幅部と、ゲイン制御信号による第１の
差動増幅部に流れる電流の変化を監視するダミー回路
と、ダミー回路の監視結果に対応して第２の差動増幅部
中の第２の電流源に負帰還をかける帰還手段とを備えて
いるので、ゲイン制御信号の変化による出力信号のバイ
アス電位の変動を防いだゲイン可変増幅回路を、従来の
ように差動増幅部を縦積みすることなく構成できる。そ
のため、低電源電圧で動作が可能となり、低消費電力化
が実現できる。第２の発明によれば、入力信号を差動増
幅した出力信号を生成する第１の差動増幅部とその出力
信号のバイアス電位を設定する第２の差動増幅部と、ゲ
イン制御信号による第１の差動増幅部に流れる電流の変
化を監視するダミー回路と、帰還手段とを備え、ゲイン
制御信号は第２の差動増幅部中の第２の電流源の電流を
変化させる構成としている。そのため、低電源電圧で動
作が可能であり、さらにゲイン制御信号における雑音が
直接出力信号に影響しなくなり、出力信号の品質が向上
する。 As described in detail above, according to the first aspect of the present invention, the first differential amplifier section for generating the output signal by differentially amplifying the input signal and the bias potential of the output signal are set. A second differential amplification section, a dummy circuit for monitoring a change in current flowing through the first differential amplification section due to a gain control signal, and a dummy circuit in the second differential amplification section corresponding to a monitoring result of the dummy circuit. Since the second current source is provided with feedback means for providing negative feedback, a variable gain amplifier circuit that prevents fluctuations in the bias potential of the output signal due to changes in the gain control signal is used as a differential amplifier unit as in the conventional case. It can be configured without vertical stacking. Therefore, it is possible to operate with a low power supply voltage, and low power consumption can be realized. According to the second aspect of the invention, the first differential amplifier section that generates the output signal by differentially amplifying the input signal, the second differential amplifier section that sets the bias potential of the output signal, and the gain control signal are used. A configuration is provided in which a dummy circuit that monitors a change in the current flowing through the first differential amplification unit and a feedback unit are provided, and the gain control signal changes the current of the second current source in the second differential amplification unit. There is. Therefore, it is possible to operate with a low supply voltage, further noise will not affect directly to the output signal of the gain control signal, the quality of the output signal you increase <br/>.
【図１】本発明の第１の実施例を示すゲイン可変増幅回
路の回路図である。FIG. 1 is a circuit diagram of a variable gain amplifier circuit showing a first embodiment of the present invention.
【図２】従来のゲイン可変増幅回路を示す回路図であ
る。FIG. 2 is a circuit diagram showing a conventional variable gain amplifier circuit.
【図３】図２におけるゲイン特性を示す図である。FIG. 3 is a diagram showing a gain characteristic in FIG.
【図４】本発明の第２の実施例を示すゲイン可変増幅回
路の回路図である。FIG. 4 is a circuit diagram of a variable gain amplifier circuit showing a second embodiment of the present invention.
【図５】本発明の第１の参考例を示すゲイン可変増幅回
路の回路図である。FIG. 5 is a circuit diagram of a variable gain amplifier circuit showing a first reference example of the present invention.
【図６】本発明の第２の参考例を示すゲイン可変増幅回
路の回路図である。FIG. 6 is a circuit diagram of a variable gain amplifier circuit showing a second reference example of the present invention.
３１，３２，７１，７２ 第１及び第２のトランジ
スタ
３３，３４，７３，７４ 負荷抵抗
３７，７７ 第１の電流源
４１，４２，８１，８１ 第３及び第４のトランジ
スタ
４５，８５ 第２の電流源
Ａ３〜Ａ６ 第１または第２の差動増
幅部
Ｄ１，Ｄ２ ダミー回路
Ｆ１，Ｆ２ 帰還手段
Ｂ１，Ｂ２ バイアス制御手段
ＤＩＰ，ＤＩＮ 差動信号入力端子
ＤＯＰ，ＤＯＮ 出力端子
ＶＡ ゲイン制御端子31, 32, 71, 72 First and second transistors 33, 34, 73, 74 Load resistance 37, 77 First current source 41, 42, 81, 81 Third and fourth transistors 45, 85 Second Current sources A3 to A6 First or second differential amplifiers D1, D2 Dummy circuits F1, F2 Feedback means B1, B2 Bias control means DIP, DIN Differential signal input terminals DOP, DON output terminals VA Gain control terminals
フロントページの続き (56)参考文献 特開 平４−319805（ＪＰ，Ａ) 特開 昭63−136807（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H03G 3/12 H03F 3/34 H03F 3/45 Continuation of the front page (56) Reference JP-A-4-319805 (JP, A) JP-A-63-136807 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H03G 3 / 12 H03F 3/34 H03F 3/45
Claims (2)
極間の導通状態を制御する制御電極とを持ち該第１電極
同士が接続されてそれぞれ差動動作を行う第１及び第２
のトランジスタと、前記各第１及び第２のトランジスタ
の第２電極と電源間にそれぞれ接続された第１及び第２
の負荷抵抗と、前記第１及び第２のトランジスタの第１
電極の接続ノードと接地間に接続されゲイン制御信号に
基づいた電流を該第１及び第２のトランジスタを介して
前記第１及び第２の負荷抵抗へ送出する第１の電流源と
を有し、１対の差動信号入力端子を介して前記各制御電
極に与えられた入力信号を差動増幅した出力信号を生成
する第１の差動増幅部と、 前記第１及び第２電極と制御電極とを持ち該第１電極同
士が接続され該各第２電極が前記第１及び第２の負荷抵
抗を介して電源に接続されかつ該制御電極には所定の電
位が与えられた第３及び第４のトランジスタと、帰還信
号に基づき制御され前記第３及び第４のトランジスタに
流れる電流を送出する第２の電流源とを有し、前記出力
信号のバイアス電位を設定する第２の差動増幅部と、 前記ゲイン制御信号に基づいた電流を流す電流路を有
し、該電流路の電流で前記第１の差動増幅部に流れる電
流を監視するダミー回路と、 前記電流路に流れる電流を一定とする帰還信号を生成し
前記ダミー回路に帰還すると共に前記第２の電流源に帰
還する帰還手段とを、 備えたことを特徴とするゲイン可変増幅回路。1. A first and a second electrode having first and second electrodes and a control electrode for controlling a conduction state between the first and second electrodes, the first electrodes being connected to each other and performing a differential operation, respectively. Two
Transistor and first and second transistors connected between the second electrodes of the first and second transistors and the power supply, respectively.
Load resistance and the first and second transistors
A first current source that is connected between a connection node of the electrode and ground and that sends out a current based on the gain control signal to the first and second load resistors via the first and second transistors. A first differential amplification unit that generates an output signal by differentially amplifying an input signal applied to each of the control electrodes via a pair of differential signal input terminals; and controls the first and second electrodes. An electrode and the first electrodes are connected to each other, the second electrodes are connected to a power source through the first and second load resistors, and the control electrode is provided with a third potential A second differential circuit having a fourth transistor and a second current source which is controlled based on a feedback signal and sends out a current flowing through the third and fourth transistors, and which sets a bias potential of the output signal. An amplifier, and a current flowing a current based on the gain control signal A dummy circuit for monitoring the current flowing through the first differential amplifier with the current in the current path, and generating a feedback signal that keeps the current flowing through the current path constant and feeding back the dummy signal to the dummy circuit. A variable gain amplifier circuit comprising: feedback means for returning to the second current source.
スタと第１及び第２の負荷抵抗と、前記第１及び第２の
トランジスタの第１電極の接続ノードと接地間に接続さ
れて帰還信号に基づいた電流を前記第１及び第２のトラ
ンジスタに送出する第１の電流源とを有し、１対の差動
信号入力端子を介して前記各制御電極に与えられた入力
信号を差動増幅した出力信号を生成する第１の差動増幅
部と、 請求項１記載の第３及び第４のトランジスタと、ゲイン
制御信号に基づき制御され前記第３及び第４のトランジ
スタに流れる電流を送出する第２の電流源とを有し、前
記出力信号のバイアス電位を設定する第２の差動増幅部
と、 請求項１記載の電流路を有し、該電流路の電流で前記第
２の差動増幅部に流れる電流を監視するダミー回路と、 前記電流路に流れる電流を一定とする帰還信号を生成し
前記ダミー回路に帰還すると共に前記第１の電流源に帰
還する帰還手段とを、 備えたことを特徴とするゲイン可変増幅回路。 2. The first and second transistors according to claim 1, the first and second load resistors, and the connection node between the first electrode of the first and second transistors and the ground. A first current source for sending a current based on a feedback signal to the first and second transistors, and an input signal applied to each of the control electrodes via a pair of differential signal input terminals. A first differential amplifier section that generates an output signal that has been differentially amplified, the third and fourth transistors according to claim 1, and a current that is controlled based on a gain control signal and that flows through the third and fourth transistors. A second differential amplifier for setting a bias potential of the output signal; and a current path according to claim 1, wherein the second differential amplifier section sets the bias potential of the output signal. A dummy circuit for monitoring the current flowing through the differential amplifier section 2; A variable gain amplifying circuit, comprising: feedback means for generating a feedback signal for making the current flowing through the flow path constant, feeding back to the dummy circuit, and feeding back to the first current source .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20561394A JP3444667B2 (en) | 1994-08-30 | 1994-08-30 | Variable gain amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20561394A JP3444667B2 (en) | 1994-08-30 | 1994-08-30 | Variable gain amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0878980A JPH0878980A (en) | 1996-03-22 |
| JP3444667B2 true JP3444667B2 (en) | 2003-09-08 |
Family
ID=16509782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20561394A Expired - Fee Related JP3444667B2 (en) | 1994-08-30 | 1994-08-30 | Variable gain amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3444667B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583671B2 (en) * | 2000-12-01 | 2003-06-24 | Sony Corporation | Stable AGC transimpedance amplifier with expanded dynamic range |
| JP5239904B2 (en) * | 2009-01-28 | 2013-07-17 | 横河電機株式会社 | Differential amplifier |
| CN105324936B (en) | 2013-07-04 | 2018-02-23 | 株式会社村田制作所 | Power amplifier module |
-
1994
- 1994-08-30 JP JP20561394A patent/JP3444667B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0878980A (en) | 1996-03-22 |
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