JP3344904B2 - Limiter amplifier - Google Patents
Limiter amplifierInfo
- Publication number
- JP3344904B2 JP3344904B2 JP27766196A JP27766196A JP3344904B2 JP 3344904 B2 JP3344904 B2 JP 3344904B2 JP 27766196 A JP27766196 A JP 27766196A JP 27766196 A JP27766196 A JP 27766196A JP 3344904 B2 JP3344904 B2 JP 3344904B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- phase
- differential amplifier
- positive
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置等におけ
る差動増幅器および差動型のリミッタ増幅器に関する。The present invention relates to a differential amplifier and a differential type limiter amplifier in a semiconductor device or the like.
【０００２】[0002]
【従来の技術】差動増幅器においては、その差動対のベ
ースーエミッタ間電圧の不整合による直流オフセットの
発生が避けられない。特に、微小入力信号を矩形波に再
生するために、差動増幅器を多段従属接続して高利得を
得る差動型のリミッタ増幅器では、直流オフセットの発
生による悪影響が顕著で、再生波形のデューティ比の劣
化や、位相偏差の発生等の問題が生じる。2. Description of the Related Art In a differential amplifier, it is inevitable that a DC offset occurs due to mismatch between base-emitter voltages of a differential pair. In particular, in the case of a differential type limiter amplifier that obtains a high gain by cascading differential amplifiers in order to reproduce a minute input signal into a square wave, the adverse effect due to the occurrence of DC offset is remarkable, and the duty ratio of the reproduced waveform is large. Problems such as deterioration of the phase and occurrence of a phase deviation.
【０００３】従来は、これらの問題を回避するため、多
段従属接続される差動増幅器の段間を交流結合し、直流
オフセット電圧を補償する構成、もしくはリミッタ増幅
器の出力のピーク値を検出し、正相出力と逆相出力のピ
ーク値が等しくなるように差動増幅器の参照電圧入力端
子に直流帰還をかける構成をとっていた。Conventionally, in order to avoid these problems, a configuration in which the stages of multistage cascaded differential amplifiers are AC-coupled to compensate for a DC offset voltage, or a peak value of the output of a limiter amplifier is detected. DC feedback is applied to the reference voltage input terminal of the differential amplifier so that the peak values of the positive-phase output and the negative-phase output become equal.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記従
来の差動増幅器の段間を交流結合したリミッタ増幅器に
よって直流オフセッ卜電圧の補償を行うと、その低域遮
断特性により、増幅できる信号の低域側の周波数が制限
されるといった問題があった。However, when the DC offset voltage is compensated for by the limiter amplifier in which the stages of the above-mentioned conventional differential amplifier are AC-coupled, the low-frequency cutoff characteristic causes a low-frequency signal to be amplified. There is a problem that the frequency on the side is limited.
【０００５】また、上記従来の出力ピーク値を検出して
参照電圧入力端子に直流帰還をかけるリミッタ増幅器に
よると、参照電圧が外来雑音の影響によりゆらぎを生
じ、このためリミッタ増幅器の出力にジッタが生じると
いった問題があった。Further, according to the conventional limiter amplifier which detects the output peak value and applies DC feedback to the reference voltage input terminal, the reference voltage fluctuates due to the influence of external noise, so that the output of the limiter amplifier has jitter. There was a problem that occurred.
【０００６】本発明はこのような従来の問題を解消し、
増幅する信号の周波数制限がなく、また外来雑音の影響
を受けることなく直流オフセッ卜電圧を補償することが
できる差動増幅器およびリミッタ増幅器を提供すること
を目的とする。The present invention solves such a conventional problem,
It is an object of the present invention to provide a differential amplifier and a limiter amplifier capable of compensating for a DC offset voltage without limiting the frequency of a signal to be amplified and without being affected by external noise.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明の差動増幅器は、正相増幅信号および逆相増幅
信号を正相出力端子および逆相出力端子から差動出力す
る差動増幅回路と、前記正相増幅信号の平均直流電圧お
よび前記逆相増幅信号の平均直流電圧を検出する平滑回
路と、前記２つの平均直流電圧が等しくなるように、前
記正相出力端子および前記逆相出力端子から引き込む直
流電流あるいはこれらの端子に流し込む直流電流を調整
する直流補償回路とを備え、前記平滑回路は、制御電極
が前記正相出力端子に接続され、第１電極が第１の定電
圧源に接続された第１のトランジスタと、制御電極が前
記逆相出力端子に接続され、第１電極が前記第１の定電
圧源に接続された第２のトランジスタと、前記第１のト
ランジスタの第２電極と第２の定電圧源との間に設けら
れた第１の定電流源と、前記第２のトランジスタの第２
電極と前記第２の定電圧源との間に設けられた第２の定
電流源と、第１電極を前記正相増幅信号の平均直流電圧
を検出する正相検出端子とし、第２電極を前記逆相増幅
信号の平均直流電圧を検出する逆相検出端子とする平滑
コンデンサと、第１電極が前記第１のトランジスタの前
記第２電極に接続され、第２電極が前記正相検出端子に
接続された第１の平滑抵抗と、第１電極が前記第２のト
ランジスタの前記第２電極に接続され、第２電極が前記
逆相検出端子に接続された第２の平滑抵抗とを有するこ
とを特徴とする。Means for Solving the Problems] differential amplifier of the present invention in order to achieve the above object, a differential of the differential output of the positive-phase amplified signal and the negative phase amplified signal from the positive phase output terminal and the reverse phase output terminal An amplifying circuit, a smoothing circuit for detecting an average DC voltage of the positive-phase amplified signal and an average DC voltage of the negative-phase amplified signal, and the positive-phase output terminal and the reverse-phase output terminal so that the two average DC voltages are equal. A DC compensation circuit for adjusting a DC current drawn from a phase output terminal or a DC current flowing into these terminals, wherein the smoothing circuit has a control electrode connected to the positive phase output terminal, and a first electrode connected to a first constant output terminal. A first transistor connected to a voltage source, a second transistor having a control electrode connected to the opposite-phase output terminal, a second electrode having a first electrode connected to the first constant voltage source, and the first transistor Second A first constant current source provided between the electrode and the second constant voltage source, a second of said second transistor
A second constant current source provided between the electrode and the second constant voltage source; a first electrode serving as a positive-phase detection terminal for detecting an average DC voltage of the positive-phase amplified signal; A smoothing capacitor serving as a negative phase detection terminal for detecting an average DC voltage of the negative phase amplification signal, a first electrode connected to the second electrode of the first transistor, and a second electrode connected to the positive phase detection terminal A first smoothing resistor connected thereto; a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the antiphase detecting terminal; It is characterized by.
【０００８】[0008]
【０００９】[0009]
【００１０】次に、本発明のリミッタ増幅器は、正相増
幅信号および逆相増幅信号を正相出力端子および逆相出
力端子から差動出力する複数の差動増幅回路を、多段従
属接続してなる差動増幅回路列と、前記差動増幅回路列
の最終段の差動増幅回路における正相増幅信号の平均直
流電圧および逆相増幅信号の平均直流電圧を検出する平
滑回路と、前記最終段の差動増幅回路における２つの平
均直流電圧が等しくなるように、前記差動増幅器列の初
段の差動増幅回路における正相出力端子および逆相出力
端子から引き込む直流電流あるいはこれらの端子に流し
込む直流電流を調整する直流補償回路と、前記初段の差
動増幅回路における正相増幅信号および逆相増幅信号を
前記差動増幅器列の第２段の差動増幅回路における正相
入力端子および逆相入力端子に出力する内部出力回路
と、前記最終段の差動増幅回路の前記正相増幅信号およ
び逆相増幅信号を外部正相出力端子および外部逆相出力
端子に出力する出力回路とを備え、前記平滑回路は、制
御電極が前記最終段の差動増幅回路の前記正相出力端子
に接続され、第１電極が第１の定電圧源に接続された第
１のトランジスタと、制御電極が前記最終段の差動増幅
回路の前記逆相出力端子に接続され、第１電極が前記第
１の定電圧源に接続された第２のトランジスタと、前記
第１のトランジスタの第２電極と第２の定電圧源との間
に設けられた第１の定電流源と、前記第２のトランジス
タの第２電極と前記第２の定電圧源との間に設けられた
第２の定電流源と、第１電極を前記最終段の差動増幅回
路における正相増幅信号の平均直流電圧を検出する正相
検出端子とし、第２電極を前記最終段の差動増幅回路に
おける逆相増幅信号の平均直流電圧を検出する逆相検出
端子とする平滑コンデンサと、第１電極が前記第１のト
ランジスタの前記第２電極に接続され、第２電極が前記
正相検出端子に接続された第１の平滑抵抗と、第１電極
が前記第２のトランジスタの前記第２電極に接続され、
第２電極が前記逆相検出端子に接続された第２の平滑抵
抗とを有し、前記内部出力回路は、制御電極が前記初段
の差動増幅回路の前記正相出力端子に接続され、第１電
極が前記第１の定電圧源に接続され、第２電極が前記第
２段の差動増幅回路の前記正相入力端子に接続された第
１の内部出力トランジスタと、制御電極が前記初段の差
動増幅回路の前記逆相出力端子に接続され、第１電極が
前記第１の定電圧源に接続され 、第２電極が前記第２段
の差動増幅回路の前記逆相入力端子に接続された第２の
内部出力トランジスタと、前記第１の内部出力トランジ
スタの第２電極と前記第２の定電圧源との間に設けられ
た第１の内部出力定電流源と、前記第２の内部出力トラ
ンジスタの第２電極と前記第２の定電圧源との間に設け
られた第２の内部出力定電流源とを有し、前記出力回路
は、制御電極が前記最終段の差動増幅回路の前記正相出
力端子に接続され、第１電極が前記第１の定電圧源に接
続され、第２電極が前記外部正相出力端子に接続された
第１の出力トランジスタと、制御電極が前記最終段の差
動増幅回路の前記逆相出力端子に接続され、第１電極が
前記第１の定電圧源に接続され、第２電極が前記外部逆
相出力端子に接続された第２の出力トランジスタと、前
記第１の出力トランジスタの第２電極と前記第２の定電
圧源との間に設けられた第１の出力定電流源と、前記第
２の出力トランジスタの第２電極と前記第２の定電圧源
との間に設けられた第２の出力定電流源とを有すること
を特徴とする。[0010] Next, limiter amplifier of the present invention, a plurality of differential amplifier circuit which outputs a differential positive-phase amplified signal and the negative phase amplified signal from the positive phase output terminal and the reverse phase output terminal, and a multi-stage cascaded A differential amplifier circuit row, a smoothing circuit for detecting an average DC voltage of a positive-phase amplified signal and an average DC voltage of a negative-phase amplified signal in a differential amplifier circuit at the last stage of the differential amplifier circuit row; DC current drawn from the positive-phase output terminal and the negative-phase output terminal of the differential amplifier circuit at the first stage of the differential amplifier train, or flows into these terminals so that the two average DC voltages in the differential amplifier circuit at the stage become equal. DC compensation circuit for adjusting the DC current, and the difference between the first stage
The positive and negative phase amplified signals in the dynamic amplifier circuit
Positive phase in the second stage differential amplifier circuit of the differential amplifier train
Internal output circuit that outputs to the input terminal and the negative-phase input terminal
And the positive-phase amplified signal of the final-stage differential amplifier circuit and
External negative phase output terminal and external negative phase output
An output circuit for outputting to a terminal , wherein the smoothing circuit has a control electrode connected to the positive-phase output terminal of the final-stage differential amplifier circuit, and a first electrode connected to a first constant voltage source. A first transistor, a second transistor having a control electrode connected to the negative phase output terminal of the final stage differential amplifier circuit, and a first electrode connected to the first constant voltage source; A first constant current source provided between a second electrode of one transistor and a second constant voltage source, and a first constant current source provided between a second electrode of the second transistor and the second constant voltage source. The second constant current source provided and the first electrode serve as a positive phase detection terminal for detecting an average DC voltage of a positive phase amplification signal in the final stage differential amplifier circuit, and the second electrode is connected to the final stage differential amplifier. Smoothing capacitor as a negative-phase detection terminal that detects the average DC voltage of the negative-phase amplified signal in a dynamic amplifier circuit A capacitor, a first electrode connected to the second electrode of the first transistor, a second electrode connected to the positive phase detection terminal, a first smoothing resistor, and a first electrode connected to the second transistor. Is connected to the second electrode of
Second have a smoothing resistor to which the second electrode is connected to the negative-phase detection terminal, the internal output circuit, the first stage control electrode
Connected to the positive-phase output terminal of the differential amplifier circuit of
A pole is connected to the first constant voltage source, and a second electrode is connected to the first constant voltage source.
A second stage differential amplifier circuit connected to the positive-phase input terminal
1 internal output transistor and the control electrode
The first electrode is connected to the negative-phase output terminal of the dynamic amplifier circuit.
A second electrode connected to the first constant voltage source;
Of the differential amplifier circuit connected to the
An internal output transistor and said first internal output transistor
Provided between a second electrode of the star and the second constant voltage source.
A first internal output constant current source, and the second internal output
Provided between a second electrode of the transistor and the second constant voltage source.
And a second internal output constant current source.
Indicates that the control electrode is connected to the positive-phase output of the final-stage differential amplifier circuit.
And the first electrode is connected to the first constant voltage source.
And the second electrode is connected to the external positive phase output terminal.
A first output transistor and a control electrode connected to a difference between the last stage and the first stage.
The first electrode is connected to the negative-phase output terminal of the dynamic amplifier circuit.
The first electrode is connected to the first constant voltage source, and the second electrode is connected to the external reverse voltage source.
A second output transistor connected to the phase output terminal;
A second electrode of the first output transistor and the second constant voltage;
A first output constant current source provided between the
A second electrode of the second output transistor and the second constant voltage source
And a second output constant current source provided between them.
【００１１】[0011]
【００１２】[0012]
【００１３】[0013]
【００１４】[0014]
第１の実施形態 図１は本発明の第１の実施形態を示す差動増幅器の回路
図である。この差動増幅器は、例えば半導体装置におい
て用いられ、差動増幅部１とオフセット電圧補償部２に
よって構成される。First Embodiment FIG. 1 is a circuit diagram of a differential amplifier according to a first embodiment of the present invention. This differential amplifier is used in, for example, a semiconductor device, and includes a differential amplifier 1 and an offset voltage compensator 2.
【００１５】まず差動増幅部１の構成を説明する。差動
増幅部１は、差動入力信号を増幅する差動増幅回路１１
と、この差動増幅信号を外部に出力する出力回路１２と
を有する。First, the configuration of the differential amplifier 1 will be described. The differential amplifier 1 includes a differential amplifier circuit 11 for amplifying a differential input signal.
And an output circuit 12 for outputting the differential amplified signal to the outside.
【００１６】差動増幅回路１１は、ベース電極を正相入
力端子ＩＮとし、コレクタ電極を逆相出力端子ｒＰとす
るｎｐｎ型トランジスタＴｒ１と、エッミタ電極の共通
接続によりトランジスタＴｒ１と差動対をなし、ベース
電極を逆相入力端子ｒＩＮとし、コレクタ電極を正相出
力端子Ｐとするｎｐｎ型トランジスタＴｒ２と、トラン
ジスタＴｒ１のコレクタ電極と正の定電圧源ＶＣＣとの
間に設けられた負荷抵抗Ｒ１と、トランジスタＴｒ２の
コレクタ電極と定電圧源ＶＣＣとの間に設けられた負荷
抵抗Ｒ２と、トランジスタＴｒ１およびＴｒ２の共通エ
ミッタ電極と負の定電圧源ＶＥＥとの間に設けられた定
電流源ＩＤＤ１とを有する。この差動増幅回路１１は、
差動入力端子ＩＮ、ｒＩＮに外部から入力される差動入
力信号を増幅し、その正相増幅信号を正相出力端子Ｐか
ら出力し、その逆相増幅信号を逆相出力端子ｒＰから出
力する。ここで、負荷抵抗Ｒ１とＲ２の抵抗値は等しい
ものとする。The differential amplifier circuit 11 forms a differential pair with the transistor Tr1 by common connection of an npn-type transistor Tr1 having a base electrode as a positive-phase input terminal IN and a collector electrode as a negative-phase output terminal rP, and an emitter electrode. An npn-type transistor Tr2 having a base electrode as the negative-phase input terminal rIN and a collector electrode as the positive-phase output terminal P; a load resistor R1 provided between the collector electrode of the transistor Tr1 and the positive constant voltage source VCC; A load resistor R2 provided between the collector electrode of the transistor Tr2 and the constant voltage source VCC, and a constant current source IDD1 provided between the common emitter electrode of the transistors Tr1 and Tr2 and the negative constant voltage source VEE. Having. This differential amplifier circuit 11
A differential input signal input from the outside to the differential input terminals IN and rIN is amplified, the positive-phase amplified signal is output from the positive-phase output terminal P, and the negative-phase amplified signal is output from the negative-phase output terminal rP. . Here, it is assumed that the resistance values of the load resistors R1 and R2 are equal.
【００１７】出力回路１２は、ベース電極が差動増幅回
路１１の正相出力端子Ｐに接続され、コレクタ電極が定
電圧源ＶＣＣに接続され、エミッタ電極を正相出力端子
ＯＵＴとするｎｐｎ型トランジスタＴｒ３と、ベース電
極が差動増幅回路１１の逆相出力端子ｒＰに接続され、
コレクタ電極が定電圧源ＶＣＣに接続され、エミッタ電
極を逆相出力端子ｒＯＵＴとするｎｐｎ型トランジスタ
Ｔｒ４と、正相出力端子ＯＵＴと定電圧源ＶＥＥとの間
に設けられた定電流源ＩＤＤ２と、逆相出力端子ｒＯＵ
Ｔと定電圧源ＶＥＥとの間に設けられた定電流源ＩＤＤ
３とを有する。トランジスタＴｒ３と定電流源ＩＤＤ２
とは、正相増幅信号の出力回路を構成し、またトランジ
スタＴｒ４と定電流源ＩＤＤ３は、逆相増幅信号の出力
回路を構成している。ここで、トランジスタＴｒ３とＴ
ｒ４の電気的特性、および定電流源ＩＤＤ２とＩＤＤ３
の電気的特性は、それぞれ同じであるものとする。The output circuit 12 is an npn-type transistor whose base electrode is connected to the positive-phase output terminal P of the differential amplifier circuit 11, whose collector electrode is connected to the constant voltage source VCC, and whose emitter electrode is the positive-phase output terminal OUT. Tr3 and the base electrode are connected to the negative-phase output terminal rP of the differential amplifier circuit 11,
An npn-type transistor Tr4 whose collector electrode is connected to the constant voltage source VCC and whose emitter electrode is the negative phase output terminal rOUT, a constant current source IDD2 provided between the positive phase output terminal OUT and the constant voltage source VEE, Negative phase output terminal rOU
Constant current source IDD provided between T and constant voltage source VEE
And 3. Transistor Tr3 and constant current source IDD2
, Constitutes an output circuit of a positive-phase amplified signal, and the transistor Tr4 and the constant current source IDD3 constitute an output circuit of a negative-phase amplified signal. Here, the transistors Tr3 and T3
Electrical characteristics of r4 and constant current sources IDD2 and IDD3
Have the same electrical characteristics.
【００１８】次にオフセット電圧補償部２の構成を説明
する。オフセット電圧補償部２は、正相出力端子Ｐの平
均直流電圧（以下、正相平均直流電圧と称する）および
逆相出力端子ｒＰの平均直流電圧（以下、逆相平均直流
電圧と称する）をそれぞれ検出する平滑回路２１と、正
相平均直流電圧と逆相平均直流電圧が等しくなるよう
に、差動増幅回路１１の負荷抵抗Ｒ１およびＲ２に流れ
る直流電流を差動調整する直流補償回路２２とを有す
る。Next, the configuration of the offset voltage compensator 2 will be described. The offset voltage compensator 2 calculates the average DC voltage of the positive-phase output terminal P (hereinafter, referred to as positive-phase average DC voltage) and the average DC voltage of the negative-phase output terminal rP (hereinafter, referred to as negative-phase average DC voltage), respectively. A smoothing circuit 21 for detection and a DC compensation circuit 22 for differentially adjusting the DC current flowing through the load resistors R1 and R2 of the differential amplifier circuit 11 so that the positive-phase average DC voltage and the negative-phase average DC voltage become equal. Have.
【００１９】平滑回路２１は、ベース電極（制御電極）
が正相出力端子Ｐに接続され、コレクタ電極（第１電
極）が定電圧源ＶＣＣ（第１の定電圧源）に接続された
ｎｐｎ型トランジスタＴｒ５（第１のトランジスタ）
と、ベース電極が逆相出力端子ｒＰに接続され、コレク
タ電極が定電圧源ＶＣＣに接続されたｎｐｎ型トランジ
スタＴｒ６（第２のトランジスタ）と、トランジスタＴ
ｒ５のエミッタ電極（第２電極）と定電圧源ＶＥＥ（第
２の定電圧源）との間に設けられた定電流源ＩＤＤ４
（第１の定電流源）と、トランジスタＴｒ６のエミッタ
電極と定電圧源ＶＥＥとの間に設けられた定電流源ＩＤ
Ｄ５（第２の定電流源）と、第１電極がトランジスタＴ
ｒ５のエミッタ電極に接続された平滑抵抗Ｒ３（第１の
平滑抵抗）と、第１電極がトランジスタＴｒ６のエミッ
タ電極に接続された平滑抵抗Ｒ４（第２の平滑抵抗）
と、第１電極が平滑抵抗Ｒ３の第２電極に接続され、第
２電極が平滑抵抗Ｒ４の第２電極に接続された平滑コン
デンサＣ１とを有する。平滑コンデンサＣ１の第１電極
には、正相平均直流電圧（厳密には、Ｔｒ５におけるベ
ース−エッミタ間の電圧降下等があるので、平均直流電
圧に対応する直流電圧である）が現れ、また平滑コンデ
ンサＣ１の第２電極には、逆相平均直流電圧（厳密には
平均直流電圧に対応する直流電圧）が現れる。平滑コン
デンサＣ１の第１電極を正相検出端子Ｄ、第２電極を逆
相検出端子ｒＤとする。ここで、トランジスタＴｒ５と
Ｔｒ６の電気的特性、および定電流源ＩＤＤ４とＩＤＤ
５の電気的特性は、それぞれ同じであるものとする。ま
た抵抗Ｒ１とＲ２の抵抗値は等しいものとする。The smoothing circuit 21 includes a base electrode (control electrode)
Is connected to the positive-phase output terminal P, and an npn-type transistor Tr5 (first transistor) whose collector electrode (first electrode) is connected to the constant voltage source VCC (first constant voltage source)
An npn-type transistor Tr6 (second transistor) having a base electrode connected to the negative-phase output terminal rP and a collector electrode connected to the constant voltage source VCC,
A constant current source IDD4 provided between the emitter electrode (second electrode) of r5 and the constant voltage source VEE (second constant voltage source)
(First constant current source) and a constant current source ID provided between the emitter electrode of the transistor Tr6 and the constant voltage source VEE.
D5 (second constant current source), and the first electrode is a transistor T
A smoothing resistor R3 (first smoothing resistor) connected to the emitter electrode of r5 and a smoothing resistor R4 (second smoothing resistor) whose first electrode is connected to the emitter electrode of the transistor Tr6.
And a smoothing capacitor C1 having a first electrode connected to a second electrode of the smoothing resistor R3 and a second electrode connected to a second electrode of the smoothing resistor R4. A positive-phase average DC voltage (strictly, a DC voltage corresponding to the average DC voltage because there is a voltage drop between the base and the emitter in Tr5, etc.) appears on the first electrode of the smoothing capacitor C1, and the smoothing capacitor C1 also performs smoothing. A negative-phase average DC voltage (strictly speaking, a DC voltage corresponding to the average DC voltage) appears on the second electrode of the capacitor C1. The first electrode of the smoothing capacitor C1 is a positive phase detection terminal D, and the second electrode is a negative phase detection terminal rD. Here, the electrical characteristics of the transistors Tr5 and Tr6, and the constant current sources IDD4 and IDD
5 have the same electrical characteristics. Also, assume that the resistance values of the resistors R1 and R2 are equal.
【００２０】直流補償回路２２は、ベース電極が平滑回
路２１の正相検出端子Ｄに接続され、コレクタ電極が差
動増幅回路１１の正相出力端子Ｐに接続されたｎｐｎ型
トランジスタＴｒ７（第３のトランジスタ）と、エッミ
タ電極の共通接続によりトランジスタＴｒ７と差動対を
なし、ベース電極が逆相検出端子ｒＤに接続され、コレ
クタ電極が逆相出力端子ｒＰに接続されたｎｐｎ型トラ
ンジスタＴｒ８（第４のトランジスタ）と、トランジス
タＴｒ７およびＴｒ８の共通エミッタ電極と定電圧源Ｖ
ＥＥとの間に設けられた定電流源ＩＤＤ６（第３の定電
流源）とを有する。トランジスタＴｒ７とＴｒ８は、正
相検出端子Ｄと逆相検出端子ｒＤの差分電圧（正相平均
直流電圧と逆相平均直流電圧との差分電圧）に応じて、
負荷抵抗Ｒ１に流れる直流電流と負荷抵抗Ｒ２に流れる
直流電流とを可変する。The DC compensation circuit 22 includes an npn-type transistor Tr7 (third transistor) having a base electrode connected to the positive phase detection terminal D of the smoothing circuit 21 and a collector electrode connected to the positive phase output terminal P of the differential amplifier circuit 11. A differential pair with the transistor Tr7 by common connection of an emitter electrode and an emitter electrode, an npn-type transistor Tr8 (first transistor) having a base electrode connected to the negative phase detection terminal rD, and a collector electrode connected to the negative phase output terminal rP. 4), a common emitter electrode of transistors Tr7 and Tr8, and a constant voltage source V
EE and a constant current source IDD6 (third constant current source). The transistors Tr7 and Tr8 operate according to the differential voltage between the positive-phase detection terminal D and the negative-phase detection terminal rD (the differential voltage between the positive-phase average DC voltage and the negative-phase average DC voltage).
The DC current flowing through the load resistor R1 and the DC current flowing through the load resistor R2 are varied.
【００２１】次に、この差動増幅器の動作を説明する。
図１において、正相平均直流電圧（正相出力端子Ｐの平
均直流電圧）をＶｐ、逆相平均直流電圧（逆相出力端子
ｒＰの平均直流電圧）をＶｒｐとし、正相検出端子Ｄの
端子電圧をＶｄ、逆相検出端子ｒＤの端子電圧をＶｒｄ
とする。また負荷抵抗Ｒ１に流れる平均直流電流をＩｒ
１、負荷抵抗Ｒ２に流れる平均直流電流をＩｒ２、トラ
ンジスタＴｒ１に流れる平均直流電流をＩｔ１、トラン
ジスタＴｒ２に流れる平均直流電流をＩｔ２、トランジ
スタＴｒ７に流れる電流をＩｃ（以下、正相補償電流と
称する）、トランジスタＴｒ８に流れる電流をＩｒｃ
（以下、逆相補償電流と称する）とする。Ｉｒ１＝Ｉｔ
１＋Ｉｒｃ、Ｉｒ２＝Ｉｔ２＋Ｉｃであり、また Ｖｐ＝ＶＣＣ−Ｒ２×Ｉｒ２＝ＶＣＣ−Ｒ２（Ｉｔ２＋
Ｉｃ） Ｖｒｐ＝ＶＣＣ−Ｒ１×Ｉｒ１＝ＶＣＣ−Ｒ１（Ｉｔ１
＋Ｉｒｃ） である。またトランジスタＴｒ３〜Ｔｒ６のベース−エ
ミッタ間の降下電圧をともにＶｂｅとする。Next, the operation of the differential amplifier will be described.
In FIG. 1, the positive-phase average DC voltage (the average DC voltage of the positive-phase output terminal P) is Vp, the negative-phase average DC voltage (the average DC voltage of the negative-phase output terminal rP) is Vrp, and the terminal of the positive-phase detection terminal D is shown in FIG. The voltage is Vd, and the terminal voltage of the reverse phase detection terminal rD is Vrd.
And The average DC current flowing through the load resistor R1 is Ir
1. The average DC current flowing through the load resistor R2 is Ir2, the average DC current flowing through the transistor Tr1 is It1, the average DC current flowing through the transistor Tr2 is It2, and the current flowing through the transistor Tr7 is Ic (hereinafter, referred to as a positive phase compensation current). , The current flowing through the transistor Tr8 is represented by Irc
(Hereinafter, referred to as a negative-phase compensation current). Ir1 = It
1 + Irc, Ir2 = It2 + Ic, and Vp = VCC-R2 × Ir2 = VCC-R2 (It2 +
Ic) Vrp = VCC-R1 × Ir1 = VCC-R1 (It1
+ Irc). Also, let Vbe be the voltage drop between the base and the emitter of each of the transistors Tr3 to Tr6.
【００２２】図１に示す差動増幅回路１１のトランジス
タＴｒ１とＴｒ２の電気的特性が整合していない場合に
は、直流オフセット電圧ΔＶが発生し、差動増幅回路１
１が単体で存在し、差動入力端子ＩＮ、ｒＩＮに信号入
力がされていないときでも（入力端子ＩＮとｒＩＮの端
子電圧が同じであるときでも）、正相出力端子Ｐの端子
電圧と逆相出力端子ｒＰの端子電圧は等しくならず上記
のΔＶだけ異なる。If the electrical characteristics of the transistors Tr1 and Tr2 of the differential amplifier circuit 11 shown in FIG. 1 do not match, a DC offset voltage ΔV is generated, and
1 is present alone, even when no signal is input to the differential input terminals IN and rIN (even when the terminal voltages of the input terminals IN and rIN are the same), the voltage is opposite to the terminal voltage of the positive-phase output terminal P. The terminal voltages of the phase output terminals rP are not equal and differ by the above ΔV.
【００２３】図１において、正弦波の差動信号が差動入
力端子ＩＮおよびｒＩＮに入力されると、差動増幅回路
１１はこれを増幅して差動出力端子ＰおよびｒＰに出力
する。正相増幅信号をｖｐとすると、正相出力端子Ｐの
端子電圧はＶｐ＋ｖｐ、逆相出力端子ｒＰの端子電圧は
Ｖｒｐ−ｖｐとなる。このとき、正相平均直流電圧Ｖｐ
と逆相平均直流電圧Ｖｒｐは上記の直流オフセット電圧
ΔＶにより等しくならない（補償電流ＩｃとＩｒｃが等
しいときにはΔＶだけ異なる値となる）。このＶｐとＶ
ｒｐのずれは、オフセット電圧補償部２によって補償さ
れる。In FIG. 1, when a sine wave differential signal is input to the differential input terminals IN and rIN, the differential amplifier circuit 11 amplifies the signal and outputs it to the differential output terminals P and rP. Assuming that the positive-phase amplified signal is vp, the terminal voltage of the positive-phase output terminal P is Vp + vp, and the terminal voltage of the negative-phase output terminal rP is Vrp−vp. At this time, the positive-phase average DC voltage Vp
And the negative-phase average DC voltage Vrp are not equal due to the DC offset voltage ΔV described above (when the compensation currents Ic and Irc are equal, the values differ by ΔV). This Vp and V
The deviation of rp is compensated by the offset voltage compensator 2.
【００２４】オフセット電圧補償部２において、平滑回
路２１は、上記の正相平均直流電圧Ｖｐおよび逆相平均
直流電圧Ｖｒｐを検出する。すなわち、トランジスタＴ
ｒ５のエッミタ電極における信号Ｖｐ＋ｖｐ−Ｖｂｅ
は、平滑抵抗Ｒ３および平滑コンデンサＣ１により平滑
され、正相検出電圧ＶｄはＶｐ−Ｖｂｅとなる。またト
ランジスタＴｒ６のエッミタ電極における信号Ｖｐ−ｖ
ｐ−Ｖｂｅは、平滑抵抗Ｒ４および平滑コンデンサＣ１
により平滑され、逆相検出電圧ＶｒｄはＶｒｐ−Ｖｂｅ
となる。In the offset voltage compensator 2, the smoothing circuit 21 detects the positive-phase average DC voltage Vp and the negative-phase average DC voltage Vrp. That is, the transistor T
The signal Vp + vp−Vbe at the emitter electrode of r5
Is smoothed by the smoothing resistor R3 and the smoothing capacitor C1, and the positive-phase detection voltage Vd becomes Vp-Vbe. Also, the signal Vp-v at the emitter electrode of the transistor Tr6
p-Vbe is equal to the smoothing resistance R4 and the smoothing capacitor C1.
And the negative phase detection voltage Vrd is Vrp−Vbe
Becomes
【００２５】直流補償回路２２は、正相平均直流電圧Ｖ
ｐと逆相平均直流電圧Ｖｒｐが等しくなるように、正相
補償電流Ｉｃおよび逆相補償電流Ｉｒｃを調整して直流
オフセット電圧ΔＶを補償する。すなわち、Ｖｐ＞Ｖｒ
ｐの場合には、Ｖｄ＞Ｖｒｄとなるので、正相補償電流
Ｉｃを増加させ、逆相補償電流Ｉｒｃを減少させる。こ
れにより、負荷抵抗Ｒ２の平均直流電流Ｉｒ２が増加し
てＶｐが降下し、負荷抵抗Ｒ１の平均直流電流Ｉｒ１が
減少してＶｒｐが上昇し、ＶｐとＶｒｐは等しくなる
（厳密には、ＶｐはＶｒｐよりも僅かに大きくなるが、
負荷抵抗Ｒ１とＲ２の抵抗値およびトランジスタＴｒ７
およびＴｒ８の電流増幅率を適度に設定することにより
Ｖｐ＝Ｖｒｐとみなすことができる）。また逆にＶｐ＜
Ｖｒｐの場合には、Ｖｄ＜Ｖｒｄとなるので、正相補償
電流Ｉｃを減少させ、逆相補償電流Ｉｒｃを増加させ
る。これにより、Ｉｒ２が減少してＶｐが上昇し、Ｉｒ
１が増加してＶｒｐが降下し、ＶｐとＶｒｐは等しくな
る。尚、トランジスタＴｒ７とＴｒ８の電気的特性は必
ずしも整合している必要はない。以上の直流オフセット
電圧補償動作により、出力回路１２の差動出力端子ＯＵ
Ｔ、ｒＯＵＴからは平均直流電圧が等しい差動増幅信号
が出力される。すなわち正相出力端子ＯＵＴからは正相
増幅信号（Ｖｐ−Ｖｂｅ）＋ｖｐが出力され、逆相出力
端子ｒＯＵＴからは逆相増幅信号（Ｖｐ−Ｖｂｅ）−ｖ
ｐが出力される。The DC compensating circuit 22 calculates the positive-phase average DC voltage V
The DC offset voltage ΔV is compensated by adjusting the positive-phase compensation current Ic and the negative-phase compensation current Irc so that p becomes equal to the negative-phase average DC voltage Vrp. That is, Vp> Vr
In the case of p, since Vd> Vrd, the positive phase compensation current Ic is increased and the negative phase compensation current Irc is decreased. As a result, the average DC current Ir2 of the load resistor R2 increases and Vp decreases, the average DC current Ir1 of the load resistor R1 decreases and Vrp increases, and Vp and Vrp become equal (strictly speaking, Vp is Slightly larger than Vrp,
The resistance values of the load resistors R1 and R2 and the transistor Tr7
Vp = Vrp can be considered by appropriately setting the current amplification factor of Tr8 and Tr8). Conversely, Vp <
In the case of Vrp, since Vd <Vrd, the positive-phase compensation current Ic is decreased and the negative-phase compensation current Irc is increased. Thereby, Ir2 decreases and Vp increases, and Ir increases.
1 increases and Vrp drops, and Vp and Vrp become equal. Note that the electrical characteristics of the transistors Tr7 and Tr8 do not necessarily need to match. By the above-described DC offset voltage compensation operation, the differential output terminal OU of the output circuit 12
T and rOUT output differentially amplified signals having the same average DC voltage. That is, a positive-phase amplified signal (Vp-Vbe) + vp is output from the positive-phase output terminal OUT, and a negative-phase amplified signal (Vp-Vbe) -v is output from the negative-phase output terminal rOUT.
p is output.
【００２６】このように第１の実施形態の差動増幅器に
よれば、平滑回路２１により正相平均直流電圧Ｖｐおよ
び逆相平均直流電圧Ｖｒｐを検出し、直流補償回路２２
によりＶｐとＶｒｐの差分電圧に応じて負荷抵抗Ｒ１お
よびＲ２に流れる直流電流を差動調整することにより、
外来雑音の影響を受けることなく高精度に直流オフセッ
卜電圧を補償することができる。As described above, according to the differential amplifier of the first embodiment, the smoothing circuit 21 detects the positive-phase average DC voltage Vp and the negative-phase average DC voltage Vrp, and the DC compensation circuit 22
By differentially adjusting the DC current flowing through the load resistors R1 and R2 according to the differential voltage between Vp and Vrp,
The DC offset voltage can be compensated with high accuracy without being affected by external noise.
【００２７】第２の実施形態 図２は本発明の第２の実施形態を示すリミッタ増幅器の
回路図であり、３つの差動増幅器ＤＡ１〜ＤＡ３を直流
結合により多段従属接続したものである。このリミッタ
増幅器は、例えば半導体装置において用いられる。Second Embodiment FIG. 2 is a circuit diagram of a limiter amplifier according to a second embodiment of the present invention, in which three differential amplifiers DA1 to DA3 are connected in multiple stages by DC coupling. This limiter amplifier is used, for example, in a semiconductor device.
【００２８】図２において、差動増幅器ＤＡ１〜ＤＡ３
は、それぞれ図１に示す差動増幅器と同じ構成を有す
る。各差動増幅器は、それぞれ図１に示すオフセット電
圧補償部２と同一構成のオフセット電圧補償部を有して
おり、このオフセット電圧補償部による直流オフセット
電圧の補償動作により、各差動増幅器から出力される正
相増幅信号と逆相増幅信号の平均直流電圧は等しい。In FIG. 2, differential amplifiers DA1 to DA3
Have the same configuration as the differential amplifier shown in FIG. Each differential amplifier has an offset voltage compensator having the same configuration as the offset voltage compensator 2 shown in FIG. 1, and the output of each differential amplifier is compensated for by a DC offset voltage compensation operation by the offset voltage compensator. The average DC voltages of the positive-phase amplified signal and the negative-phase amplified signal are equal.
【００２９】このように第２の実施形態のリミッタ増幅
器によれば、上記第１の実施形態の差動増幅器を直流結
合で多段従属接続することにより、外来雑音の影響を受
けることなく、かつ低周波数側に制限を受けることなく
直流オフセット電圧を高精度に補償することができる。As described above, according to the limiter amplifier of the second embodiment, the differential amplifier of the first embodiment is connected in a multistage cascade by DC coupling, so that the differential amplifier is not affected by external noise and has low noise. The DC offset voltage can be compensated with high accuracy without being restricted on the frequency side.
【００３０】尚、図２には差動増幅器の従属接続段数が
３段の場合を示したが、従属接続段数はこれに限定され
ないことは言うまでもない。Although FIG. 2 shows a case where the number of cascaded stages of the differential amplifier is three, it is needless to say that the number of cascaded stages is not limited to this.
【００３１】第３の実施形態 図３は本発明の第３の実施形態を示すリミッタ増幅器の
回路図である。このリミッタ増幅器は、例えば半導体装
置において用いられ、差動増幅部３１とオフセット電圧
補償部３２によって構成される。Third Embodiment FIG. 3 is a circuit diagram of a limiter amplifier according to a third embodiment of the present invention. This limiter amplifier is used, for example, in a semiconductor device, and includes a differential amplifier 31 and an offset voltage compensator 32.
【００３２】まず差動増幅部３１の構成を説明する。差
動増幅部３１は、差動入力信号を増幅する差動増幅回路
４１と、この差動増幅信号を中継する出力回路４２と、
出力回路４２からの差動信号を増幅する差動増幅回路４
３と、差動増幅回路４３の差動増幅信号を増幅する差動
増幅回路４４と、差動増幅回路４４の差動増幅信号を外
部に出力する出力回路４５とを有する。すなわち差動増
幅部３１は、差動増幅回路４１を初段、差動増幅回路４
４を最終段として３つの差動増幅回路を多段従属接続し
たものである。First, the configuration of the differential amplifier 31 will be described. The differential amplifier 31 includes a differential amplifier circuit 41 that amplifies the differential input signal, an output circuit 42 that relays the differential amplified signal,
Differential amplifier circuit 4 for amplifying the differential signal from output circuit 42
3, a differential amplifier circuit 44 for amplifying the differential amplified signal of the differential amplifier circuit 43, and an output circuit 45 for outputting the differential amplified signal of the differential amplifier circuit 44 to the outside. That is, the differential amplifier 31 includes the differential amplifier 41 in the first stage, the differential amplifier 4
4 is the last stage and three differential amplifier circuits are connected in a multistage cascade.
【００３３】差動増幅回路４１は、ベース電極を正相入
力端子ＩＮとし、コレクタ電極を逆相出力端子ｒＰ１と
するｎｐｎ型トランジスタＴｒ１１と、エッミタ電極の
共通接続によりトランジスタＴｒ１１と差動対をなし、
ベース電極を逆相入力端子ｒＩＮとし、コレクタ電極を
正相出力端子Ｐとするｎｐｎ型トランジスタＴｒ１２
と、トランジスタＴｒ１１のコレクタ電極と正の定電圧
源ＶＣＣとの間に設けられた負荷抵抗Ｒ１１と、トラン
ジスタＴｒ１２のコレクタ電極と定電圧源ＶＣＣとの間
に設けられた負荷抵抗Ｒ１２と、トランジスタＴｒ１１
およびＴｒ１２の共通エミッタ電極と負の定電圧源ＶＥ
Ｅとの間に設けられたされた定電流源ＩＤＤ１１とを有
する。ここで、負荷抵抗Ｒ１１とＲ１２の抵抗値は等し
いものとする。The differential amplifier circuit 41 forms a differential pair with the npn-type transistor Tr11 having a base electrode as a positive-phase input terminal IN and a collector electrode as a negative-phase output terminal rP1, and a transistor Tr11 by common connection of an emitter electrode. ,
An npn-type transistor Tr12 having a base electrode as a negative-phase input terminal rIN and a collector electrode as a positive-phase output terminal P
A load resistor R11 provided between the collector electrode of the transistor Tr11 and the positive constant voltage source VCC; a load resistor R12 provided between the collector electrode of the transistor Tr12 and the constant voltage source VCC;
And the common emitter electrode of Tr12 and the negative constant voltage source VE
And E and a constant current source IDD11 provided therebetween. Here, it is assumed that the resistance values of the load resistors R11 and R12 are equal.
【００３４】出力回路４２は、ベース電極が差動増幅回
路４１の正相出力端子Ｐ１に接続され、コレクタ電極が
定電圧源ＶＣＣに接続され、エミッタ電極を正相出力端
子Ｐ２とするｎｐｎ型トランジスタＴｒ１３と、ベース
電極が差動増幅回路４１の逆相出力端子ｒＰ１に接続さ
れ、コレクタ電極が定電圧源ＶＣＣに接続され、エミッ
タ電極を逆相出力端子ｒＰ２とするｎｐｎ型トランジス
タＴｒ１４と、正相出力端子Ｐ２と定電圧源ＶＥＥとの
間に設けられた定電流源ＩＤＤ１２と、逆相出力端子ｒ
Ｐ２と定電圧源ＶＥＥとの間に設けられた定電流源ＩＤ
Ｄ１３とを有する。ここで、トランジスタＴｒ１３とＴ
ｒ１４の電気的特性、および定電流源ＩＤＤ１２とＩＤ
Ｄ１３の電気的特性は、それぞれ同じであるものとす
る。The output circuit 42 has an npn-type transistor whose base electrode is connected to the positive-phase output terminal P1 of the differential amplifier circuit 41, whose collector electrode is connected to the constant voltage source VCC, and whose emitter electrode is the positive-phase output terminal P2. Tr13, an npn-type transistor Tr14 having a base electrode connected to the negative-phase output terminal rP1 of the differential amplifier circuit 41, a collector electrode connected to the constant voltage source VCC, and an emitter electrode having the negative-phase output terminal rP2, A constant current source IDD12 provided between the output terminal P2 and the constant voltage source VEE;
Constant current source ID provided between P2 and constant voltage source VEE
D13. Here, the transistors Tr13 and T13
Electrical characteristics of r14 and constant current sources IDD12 and IDD
The electrical characteristics of D13 are assumed to be the same.
【００３５】差動増幅回路４３は、差動増幅回路４１と
同じ構成であり、ベース電極が出力回路４２の正相出力
端子Ｐ２に接続され、コレクタ電極を逆相出力端子ｒＰ
３とするｎｐｎ型トランジスタＴｒ１５と、ベース電極
が出力回路４２の逆相出力端子ｒＰ２に接続され、コレ
クタ電極を正相出力端子Ｐ３とするｎｐｎ型トランジス
タＴｒ１６と、負荷抵抗Ｒ１３および１４と、定電流源
ＩＤＤ１４とを有する。ここで、負荷抵抗Ｒ１３とＲ１
４の抵抗値は等しいものとする。The differential amplifier circuit 43 has the same configuration as the differential amplifier circuit 41. The base electrode is connected to the positive output terminal P2 of the output circuit 42, and the collector electrode is connected to the negative output terminal rP.
3, an npn-type transistor Tr15 having a base electrode connected to the negative-phase output terminal rP2 of the output circuit 42 and a collector electrode having a positive-phase output terminal P3, load resistors R13 and R14, and a constant current. Source IDD14. Here, the load resistors R13 and R1
4 have the same resistance value.
【００３６】差動増幅回路４４も、差動増幅回路４１、
４３と同じ構成であり、ベース電極が差動増幅回路４３
の正相出力端子Ｐ３に接続され、コレクタ電極を逆相出
力端子ｒＰ４とするｎｐｎ型トランジスタＴｒ１７と、
ベース電極が差動増幅回路４３の逆相出力端子ｒＰ３に
接続され、コレクタ電極を正相出力端子Ｐ４とするｎｐ
ｎ型トランジスタＴｒ１８と、負荷抵抗Ｒ１５およびＲ
１６と、定電流源ＩＤＤ１５とを有する。ここで、負荷
抵抗Ｒ１５とＲ１６の抵抗値は等しいものとする。The differential amplifier circuit 44 also includes the differential amplifier circuit 41,
43 has the same configuration as that of the differential amplifier 43
An npn-type transistor Tr17 connected to the positive-phase output terminal P3 and having the collector electrode as the negative-phase output terminal rP4;
The base electrode is connected to the negative-phase output terminal rP3 of the differential amplifier circuit 43, and the collector electrode is used as the positive-phase output terminal P4.
An n-type transistor Tr18 and load resistors R15 and R15
16 and a constant current source IDD15. Here, it is assumed that the resistance values of the load resistors R15 and R16 are equal.
【００３７】出力回路４５は、出力回路４２と同じ構成
であり、ベース電極が差動増幅回路４３の正相出力端子
Ｐ４に接続され、エミッタ電極を正相出力端子ＯＵＴと
するｎｐｎ型トランジスタＴｒ１９と、ベース電極が差
動増幅回路４３の逆相出力端子ｒＰ４に接続され、エミ
ッタ電極を逆相出力端子ｒＯＵＴとするｎｐｎ型トラン
ジスタＴｒ２０と、定電流源ＩＤＤ１６およびＩＤＤ１
７とを有する。ここで、トランジスタＴｒ１９とＴｒ２
０の電気的特性、および定電流源ＩＤＤ１６とＩＤＤ１
７の電気的特性は、それぞれ同じであるものとする。The output circuit 45 has the same configuration as the output circuit 42. The output circuit 45 has an npn-type transistor Tr19 whose base electrode is connected to the positive-phase output terminal P4 of the differential amplifier circuit 43 and whose emitter electrode is the positive-phase output terminal OUT. , The base electrode is connected to the negative-phase output terminal rP4 of the differential amplifier circuit 43, the npn-type transistor Tr20 having the emitter electrode as the negative-phase output terminal rOUT, the constant current sources IDD16 and IDD1.
And 7. Here, transistors Tr19 and Tr2
0 and the constant current sources IDD16 and IDD1
7 have the same electrical characteristics.
【００３８】次にオフセット電圧補償部３２の構成を説
明する。オフセット電圧補償部３２は、最終段の差動増
幅回路４４の正相平均直流電圧および逆相平均直流電圧
をそれぞれ検出する平滑回路５１と、差動増幅回路４３
の正相平均直流電圧と逆相平均直流電圧が等しくなるよ
うに、初段の差動増幅回路４１の負荷抵抗Ｒ１１および
Ｒ１２に流れる直流電流を差動調整する直流補償回路５
２とを有し、各差動増幅回路で発生する直流オフセット
電圧をリミッタ増幅器内部で補償する。Next, the configuration of the offset voltage compensator 32 will be described. The offset voltage compensator 32 includes a smoothing circuit 51 for detecting the positive-phase average DC voltage and the negative-phase average DC voltage of the final-stage differential amplifier circuit 44, respectively, and a differential amplifier circuit 43.
DC compensation circuit 5 for differentially adjusting the DC current flowing through load resistors R11 and R12 of first-stage differential amplifier circuit 41 so that the positive-phase average DC voltage and the negative-phase average DC voltage become equal.
2 to compensate for the DC offset voltage generated in each differential amplifier circuit inside the limiter amplifier.
【００３９】平滑回路５１は、ベース電極（制御電極）
が正相出力端子Ｐ４に接続され、コレクタ電極（第１電
極）が定電圧源ＶＣＣ（第１の定電圧源）に接続された
ｎｐｎ型トランジスタＴｒ２１（第１のトランジスタ）
と、ベース電極が逆相出力端子ｒＰ４に接続され、コレ
クタ電極が定電圧源ＶＣＣに接続されたｎｐｎ型トラン
ジスタＴｒ２２（第２のトランジスタ）と、トランジス
タＴｒ２１のエミッタ電極（第２電極）と定電圧源ＶＥ
Ｅ（第２の定電圧源）との間に設けられた定電流源ＩＤ
Ｄ１８（第１の定電流源）と、トランジスタＴｒ２２の
エミッタ電極と定電圧源ＶＥＥとの間に設けられた定電
流源ＩＤＤ１９（第２の定電流源）と、第１電極がトラ
ンジスタＴｒ２１のエミッタ電極に接続された平滑抵抗
Ｒ１７（第１の平滑抵抗）と、第１電極がトランジスタ
Ｔｒ２２のエミッタ電極に接続された平滑抵抗Ｒ１８
（第２の平滑抵抗）と、第１電極が平滑抵抗Ｒ１７の第
２電極に接続され、第２電極が平滑抵抗Ｒ１８の第２電
極に接続された平滑コンデンサＣ１１とを有する。平滑
コンデンサＣ１１の第１電極を正相検出端子Ｄとし、第
２電極を逆相検出端子ｒＤとする。正相検出端子Ｄには
差動増幅回路４４の正相平均直流電圧が現れ、逆相検出
端子ｒＤには、差動増幅回路４４の逆相平均直流電圧が
現れる。ここで、トランジスタＴｒ２１とＴｒ２２の電
気的特性、および定電流源ＩＤＤ１８とＩＤＤ１９の電
気的特性は、それぞれ同じであるものとする。また平滑
抵抗Ｒ１７と平滑抵抗Ｒ１８の抵抗値は等しいものとす
る。The smoothing circuit 51 includes a base electrode (control electrode)
Is connected to the positive-phase output terminal P4, and an npn-type transistor Tr21 (first transistor) having a collector electrode (first electrode) connected to a constant voltage source VCC (first constant voltage source).
And an npn-type transistor Tr22 (second transistor) having a base electrode connected to the negative-phase output terminal rP4 and a collector electrode connected to the constant voltage source VCC, and an emitter electrode (second electrode) of the transistor Tr21 and a constant voltage. Source VE
E (second constant voltage source) and a constant current source ID provided
D18 (first constant current source), a constant current source IDD19 (second constant current source) provided between the emitter electrode of the transistor Tr22 and the constant voltage source VEE, and a first electrode connected to the emitter of the transistor Tr21. A smoothing resistor R17 (first smoothing resistor) connected to the electrode and a smoothing resistor R18 having the first electrode connected to the emitter electrode of the transistor Tr22.
(A second smoothing resistor), and a smoothing capacitor C11 having a first electrode connected to the second electrode of the smoothing resistor R17 and a second electrode connected to a second electrode of the smoothing resistor R18. The first electrode of the smoothing capacitor C11 is a positive phase detection terminal D, and the second electrode is a negative phase detection terminal rD. The positive-phase average DC voltage of the differential amplifier circuit 44 appears at the positive-phase detection terminal D, and the negative-phase average DC voltage of the differential amplifier circuit 44 appears at the negative-phase detection terminal rD. Here, it is assumed that the electrical characteristics of the transistors Tr21 and Tr22 and the electrical characteristics of the constant current sources IDD18 and IDD19 are the same. Further, it is assumed that the resistance values of the smoothing resistor R17 and the smoothing resistor R18 are equal.
【００４０】直流補償回路５２は、ベース電極が正相検
出端子Ｄに接続され、コレクタ電極が正相出力端子Ｐ１
に接続されたｎｐｎ型トランジスタＴｒ２３（第３のト
ランジスタ）と、トランジスタＴｒ２３と差動対をな
し、ベース電極が逆相検出端子ｒＤに接続され、コレク
タ電極が逆相出力端子ｒＰ１に接続されたｎｐｎ型トラ
ンジスタＴｒ２４（第４のトランジスタ）と、トランジ
スタＴｒ２３およびＴｒ２４の共通エミッタ電極と定電
圧源ＶＥＥとの間に設けられた定電流源ＩＤＤ２０（第
３の定電流源）とを有する。トランジスタＴｒ２３とＴ
ｒ２４は、正相検出端子Ｄと逆相検出端子ｒＤの差分電
圧、すなわち最終段の差動増幅回路４４の正相平均直流
電圧と逆相平均直流電圧との差分電圧に応じて、初段の
差動増幅回路４１の負荷抵抗に流れる直流電流を可変す
る。The DC compensation circuit 52 has a base electrode connected to the positive phase detection terminal D, and a collector electrode connected to the positive phase output terminal P1.
Npn-type transistor Tr23 (third transistor), which is connected to a negative-phase output terminal rP1, and a differential pair with the transistor Tr23, a base electrode is connected to the negative-phase detection terminal rD, and a collector electrode is connected to the negative-phase output terminal rP1. It has a type transistor Tr24 (fourth transistor) and a constant current source IDD20 (third constant current source) provided between the common emitter electrode of the transistors Tr23 and Tr24 and the constant voltage source VEE. Transistors Tr23 and T
r24 is a differential voltage between the positive-phase detection terminal D and the negative-phase detection terminal rD, that is, a differential voltage between the positive-phase average DC voltage and the negative-phase average DC voltage of the final-stage differential amplifier circuit 44, The DC current flowing through the load resistance of the dynamic amplification circuit 41 is varied.
【００４１】次に、図３のリミッタ増幅器の動作を説明
する。図３において、差動増幅回路４１の正相平均直流
電圧（正相出力端子Ｐ１の平均直流電圧）をＶｐ１、差
動増幅回路４１の逆相平均直流電圧（逆相出力端子ｒＰ
１の平均直流電圧）をＶｒｐ１、差動増幅回路４４の正
相平均直流電圧（正相出力端子Ｐ４の平均直流電圧）を
Ｖｐ４、差動増幅回路４４の逆相平均直流電圧（出力端
子ｒＰ４の平均直流電圧）をＶｒｐ４とし、正相検出端
子Ｄの端子電圧をＶｄ、逆相検出端子ｒＤの端子電圧を
Ｖｒｄとする。トランジスタＴｒ２３に流れる正相補償
電流をＩｃ、トランジスタＴｒ２４に流れる逆相補償電
流をＩｒｃとする。またトランジスタＴｒ１３、Ｔｒ１
４、Ｔｒ１９〜Ｔｒ２２のベース−エミッタ間の降下電
圧をともにＶｂｅとする。Next, the operation of the limiter amplifier of FIG. 3 will be described. In FIG. 3, the positive-phase average DC voltage of the differential amplifier circuit 41 (the average DC voltage of the positive-phase output terminal P1) is Vp1, and the negative-phase average DC voltage of the differential amplifier circuit 41 (the negative-phase output terminal rP
1 is Vrp1, the positive-phase average DC voltage of the differential amplifier circuit 44 (the average DC voltage of the positive-phase output terminal P4) is Vp4, and the negative-phase average DC voltage of the differential amplifier circuit 44 (the output terminal rP4). The average DC voltage is Vrp4, the terminal voltage of the positive-phase detection terminal D is Vd, and the terminal voltage of the negative-phase detection terminal rD is Vrd. The positive-phase compensation current flowing through the transistor Tr23 is Ic, and the negative-phase compensation current flowing through the transistor Tr24 is Irc. Also, transistors Tr13 and Tr1
4. The voltage drop between the base and the emitter of Tr19 to Tr22 is Vbe.
【００４２】図３において、正弦波の差動信号が差動入
力端子ＩＮおよびｒＩＮに入力されると、差動増幅回路
４１はこれを増幅して差動出力端子Ｐ１およびｒＰ１に
出力する。この差動増幅信号は、出力回路４２を介して
差動増幅回路４３および差動増幅回路４４でさらに増幅
され、差動出力端子Ｐ４、ｒＰ４に出力される。この正
相増幅信号をｖｐ４とすると、正相出力端子Ｐ４の端子
電圧はＶｐ４＋ｖｐ４、逆相出力端子ｒＰ４の端子電圧
はＶｒｐ４−ｖｐ４となる。このとき、差動対をなして
いるトランジスタＴｒ１１とＴｒ１２、Ｔｒ１５とＴｒ
１６、Ｔｒ１７とＴｒ１８のいずれかの電気的特性が整
合していないと直流オフセット電圧が発生し、これを補
償しないとＶｐ４とＶｒｐ４は等しくならない。このＶ
ｐ４とＶｒｐ４のずれは、オフセット電圧補償部３２に
よって補償される。In FIG. 3, when a sine wave differential signal is input to the differential input terminals IN and rIN, the differential amplifier circuit 41 amplifies the signal and outputs it to the differential output terminals P1 and rP1. This differentially amplified signal is further amplified by the differential amplifier circuit 43 and the differential amplifier circuit 44 via the output circuit 42 and output to the differential output terminals P4 and rP4. Assuming that the positive-phase amplified signal is vp4, the terminal voltage of the positive-phase output terminal P4 is Vp4 + vp4, and the terminal voltage of the negative-phase output terminal rP4 is Vrp4-vp4. At this time, the transistors Tr11 and Tr12, Tr15 and Tr
16, if any of the electrical characteristics of Tr17 and Tr18 do not match, a DC offset voltage is generated, and unless this is compensated, Vp4 and Vrp4 will not be equal. This V
The offset between p4 and Vrp4 is compensated by the offset voltage compensator 32.
【００４３】オフセット電圧補償部３２において、平滑
回路５１は、上記の正相平均直流電圧Ｖｐ４および逆相
平均直流電圧Ｖｒｐ４を検出する。すなわち、上記の正
相増幅信号Ｖｐ４＋ｖｐ４は、平滑抵抗Ｒ１７および平
滑コンデンサＣ１１により平滑され、正相検出電圧Ｖｄ
はＶｐ４−Ｖｂｅとなる。また上記の逆相増幅信号Ｖｒ
ｐ４−ｖｐ４は、平滑抵抗Ｒ１８および平滑コンデンサ
Ｃ１１により平滑され、逆相検出電圧ＶｒｄはＶｒｐ４
−Ｖｂｅとなる。In the offset voltage compensating unit 32, the smoothing circuit 51 detects the positive-phase average DC voltage Vp4 and the negative-phase average DC voltage Vrp4. That is, the positive-phase amplified signal Vp4 + vp4 is smoothed by the smoothing resistor R17 and the smoothing capacitor C11, and the positive-phase detection voltage Vd
Becomes Vp4-Vbe. Also, the above-mentioned inverted-phase amplified signal Vr
p4-vp4 is smoothed by the smoothing resistor R18 and the smoothing capacitor C11, and the anti-phase detection voltage Vrd is Vrp4
−Vbe.
【００４４】直流補償回路５２は、正相平均直流電圧Ｖ
ｐ４と逆相平均直流電圧Ｖｒｐ４が等しくなるように、
補償電流ＩｃおよびＩｒｃを調整し、直流オフセット電
圧を補償する。すなわち、Ｖｐ４＞Ｖｒｐ４の場合に
は、Ｖｄ＞Ｖｒｄとなるので、正相補償電流Ｉｃを増加
させて正相平均直流電圧Ｖｐ１を降下させ、また逆相補
償電流Ｉｒｃを減少させて逆相平均直流電圧Ｖｒｐ１を
上昇させる。これにより、Ｖｐ４が降下し、Ｖｒｐ４が
上昇して、Ｖｐ４とＶｒｐ４は等しくなる。また逆にＶ
ｐ４＜Ｖｒｐ４の場合には、Ｖｄ＜Ｖｒｄとなるので、
Ｉｃを減少させてＶｐ１を上昇させ、またＩｒｃを増加
させてＶｒｐを降下させて、ＶｐとＶｒｐを等しくさせ
る。尚、トランジスタＴｒ２３とＴｒ２４の電気的特性
は必ずしも整合している必要はない。以上の直流電圧補
償により、出力回路４５の差動出力端子ＯＵＴ、ｒＯＵ
Ｔからは平均直流電圧が等しい差動増幅信号が出力され
る。The DC compensating circuit 52 outputs the positive-phase average DC voltage V
In order that p4 and the negative-phase average DC voltage Vrp4 become equal,
The compensation currents Ic and Irc are adjusted to compensate for the DC offset voltage. That is, when Vp4> Vrp4, Vd> Vrd, so that the positive-phase compensation current Ic is increased to decrease the positive-phase average DC voltage Vp1, and the negative-phase compensation current Irc is decreased to reduce the negative-phase average DC voltage. The voltage Vrp1 is increased. As a result, Vp4 decreases, Vrp4 increases, and Vp4 and Vrp4 become equal. And V
If p4 <Vrp4, Vd <Vrd, so
Decreasing Ic raises Vp1, and increasing Irc lowers Vrp so that Vp equals Vrp. Note that the electrical characteristics of the transistors Tr23 and Tr24 do not necessarily have to match. By the above DC voltage compensation, the differential output terminals OUT and rOU of the output circuit 45 are output.
A differential amplified signal having the same average DC voltage is output from T.
【００４５】このように第３の実施形態によれば、平滑
回路５１により最終段の差動増幅回路４４の正相平均直
流電圧Ｖｐ４および逆相平均直流電圧Ｖｒｐ４を検出
し、直流補償回路５２によりＶｐ４とＶｒｐ４の差分電
圧に応じて初段の差動増幅回路４１の負荷抵抗に流す直
流電流を差動調整することにより、外来雑音の影響を受
けることなく、かつ低周波数側に制限を受けることなく
高精度に直流オフセッ卜電圧を補償することができる。
さらに上記第２の実施形態に比べて回路規模が大幅に削
減できるため、低消費電力化が可能となる。As described above, according to the third embodiment, the smoothing circuit 51 detects the positive-phase average DC voltage Vp4 and the negative-phase average DC voltage Vrp4 of the differential amplifier circuit 44 at the final stage, and the DC compensation circuit 52 By differentially adjusting the DC current flowing through the load resistance of the first-stage differential amplifier circuit 41 in accordance with the difference voltage between Vp4 and Vrp4, without being affected by external noise and without being restricted to the low frequency side The DC offset voltage can be compensated with high accuracy.
Further, since the circuit scale can be significantly reduced as compared with the second embodiment, low power consumption can be achieved.
【００４６】尚、図３には差動増幅回路の従属接続段数
が３段の場合を示したが、従属接続段数はこれに限定さ
れない。また図３に示すリミッタ回路をさらに多段従属
接続して良い。例えば、差動増幅回路の従属接続段数が
１０段であり、初段から第３段までの差動増幅回路と、
第４段から最終段までの差動増幅回路に、別々にオフセ
ット電圧補償部を設けた構成としても良い。Although FIG. 3 shows a case where the number of the cascade connection stages of the differential amplifier circuit is three, the number of the cascade connection stages is not limited to this. Further, the limiter circuit shown in FIG. 3 may be further connected in multiple stages. For example, the number of cascade connection stages of the differential amplifier circuit is 10, and the differential amplifier circuits from the first stage to the third stage are:
The differential amplifier circuits from the fourth stage to the last stage may be provided with separate offset voltage compensating units.
【００４７】[0047]
【発明の効果】以上説明したように、本発明の差動増幅
器によれば、平滑回路により正相平均直流電圧および逆
相平均直流電圧を検出し、直流補償回路により２つの平
均直流電圧が等しくなるように、正相出力端子および逆
相出力端子から引き込む直流電流あるいはこれらの端子
に流し込む直流電流を調整することにより、外来雑音の
影響を受けることなく高精度に直流オフセッ卜電圧を補
償することができるという効果がある。As described above, according to the differential amplifier of the present invention, the positive-phase average DC voltage and the negative-phase average DC voltage are detected by the smoothing circuit, and the two average DC voltages are made equal by the DC compensation circuit. By adjusting the DC current drawn from the positive-phase output terminal and the negative-phase output terminal or the DC current flowing into these terminals, the DC offset voltage can be compensated with high accuracy without being affected by external noise. There is an effect that can be.
【００４８】また本発明の差動増幅器を多段従属接続し
たリッミタ増幅器によれば、外来雑音の影響を受けるこ
となく、かつ低周波数側に制限を受けることなく直流オ
フセット電圧を高精度に補償することができるという効
果がある。According to the limiter amplifier of the present invention in which the differential amplifiers are connected in multiple stages, the DC offset voltage can be compensated with high accuracy without being affected by external noise and without being restricted on the low frequency side. There is an effect that can be.
【００４９】[0049]
【発明の効果】また本発明のリミッタ増幅器によれば、
平滑回路により最終段の差動増幅回路の正相平均直流電
圧および逆相平均直流電圧を検出し、直流補償回路によ
りこの２つの平均直流電圧が等しくなるように初段の差
動増幅回路の正相出力端子および逆相出力端子から引き
込む直流電流あるいはこれらの端子に流し込む直流電流
を調整することにより、外来雑音の影響を受けることな
く、かつ低周波数側に制限を受けることなく高精度に直
流オフセッ卜電圧を補償することができ、さらに上記の
差動増幅器を多段従属接続したリッミタ増幅器に比べて
回路規模を大幅に削減できるため、低消費電力化が可能
となるという効果がある。Effects of the Invention] According to the limiter amplifier of the present invention,
The smoothing circuit detects the positive-phase average DC voltage and the negative-phase average DC voltage of the final-stage differential amplifier circuit, and the DC-compensation circuit adjusts the positive-phase average DC voltage of the first-stage differential amplifier circuit so that the two average DC voltages become equal. By adjusting the DC current drawn from the output terminal and the negative-phase output terminal or the DC current flowing into these terminals, the DC offset can be accurately performed without being affected by external noise and without being restricted to the low frequency side. The voltage can be compensated, and the circuit scale can be significantly reduced as compared with the limiter amplifier in which the above-described differential amplifiers are connected in a multistage cascade, so that the power consumption can be reduced.
【図１】本発明の第１の実施形態を示す差動増幅器の回
路図である。FIG. 1 is a circuit diagram of a differential amplifier according to a first embodiment of the present invention.
【図２】本発明の第２の実施形態を示す差動増幅型のリ
ミッタ増幅器の回路図である。FIG. 2 is a circuit diagram of a differential amplification type limiter amplifier according to a second embodiment of the present invention.
【図３】本発明の第３の実施形態を示す差動増幅型のリ
ミッタ増幅器の回路図である。FIG. 3 is a circuit diagram of a differential amplification type limiter amplifier according to a third embodiment of the present invention.
１、３１ 差動増幅部、２、３２ オフセット電圧補償
部、１１、４１、４３、４４ 差動増幅回路、１２、４
２、４５ 出力回路、２１、５１ 平滑回路、２２、５
２ 直流補償回路、ＤＡ１〜ＤＡ３ 差動増幅器、ＩＮ
正相入力端子、ｒＩＮ 逆相入力端子、ＯＵＴ、Ｐ、
Ｐ１〜Ｐ４ 正相出力端子、ｒＯＵＴ、ｒＰ、ｒＰ１〜
ｒＰ４ 逆相出力端子、Ｔｒ１〜Ｔｒ８、Ｔｒ１１〜Ｔ
ｒ２４ｎｐｎ型トランジスタ、Ｒ１〜Ｒ４、Ｒ１１〜Ｒ
１８ 抵抗、Ｃ１、Ｃ１１ 平滑コンデンサ、Ｄ 正相
検出端子、ｒＤ 逆相検出端子、ＩＤＤ１〜ＩＤＤ６、
ＩＤＤ１１〜ＩＤＤ２０ 定電流源、ＶＣＣ、ＶＥＥ
定電圧源、Ｉｃ 正相補償電流、Ｉｒｃ 逆相補償電流1, 31 differential amplifier, 2, 32 offset voltage compensator, 11, 41, 43, 44 differential amplifier, 12, 4
2,45 output circuit, 21,51 smoothing circuit, 22,5
2 DC compensation circuit, DA1 to DA3 differential amplifier, IN
Normal phase input terminal, rIN Negative phase input terminal, OUT, P,
P1 to P4 Normal phase output terminals, rOUT, rP, rP1
rP4 Negative phase output terminal, Tr1 to Tr8, Tr11 to T
r24npn type transistors, R1 to R4, R11 to R
18 resistance, C1, C11 smoothing capacitor, D positive phase detection terminal, rD reverse phase detection terminal, IDD1 to IDD6,
IDD11 to IDD20 Constant current source, VCC, VEE
Constant voltage source, Ic positive phase compensation current, Irc negative phase compensation current
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H03G 11/00 - 11/08 H03F 3/34 - 3/45 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H03G 11/00-11/08 H03F 3/34-3/45
Claims (4)
出力端子および逆相出力端子から差動出力する複数の差
動増幅回路を、多段従属接続してなる差動増幅回路列
と、 前記差動増幅回路列の最終段の差動増幅回路における正
相増幅信号の平均直流電圧および逆相増幅信号の平均直
流電圧を検出する平滑回路と、 前記最終段の差動増幅回路における２つの平均直流電圧
が等しくなるように、前記差動増幅器列の初段の差動増
幅回路における正相出力端子および逆相出力端子から引
き込む直流電流あるいはこれらの端子に流し込む直流電
流を調整する直流補償回路と、 前記初段の差動増幅回路における正相増幅信号および逆
相増幅信号を前記差動増幅器列の第２段の差動増幅回路
における正相入力端子および逆相入力端子に出力する内
部出力回路と、 前記最終段の差動増幅回路の前記正相増幅信号および逆
相増幅信号を外部正相出力端子および外部逆相出力端子
に出力する出力回路と を備え、 前記平滑回路は、 制御電極が前記最終段の差動増幅回路の前記正相出力端
子に接続され、第１電極が第１の定電圧源に接続された
第１のトランジスタと、 制御電極が前記最終段の差動増幅回路の前記逆相出力端
子に接続され、第１電極が前記第１の定電圧源に接続さ
れた第２のトランジスタと、 前記第１のトランジスタの第２電極と第２の定電圧源と
の間に設けられた第１の定電流源と、 前記第２のトランジスタの第２電極と前記第２の定電圧
源との間に設けられた第２の定電流源と、 第１電極を前記最終段の差動増幅回路における正相増幅
信号の平均直流電圧を検出する正相検出端子とし、第２
電極を前記最終段の差動増幅回路における逆相増幅信号
の平均直流電圧を検出する逆相検出端子とする平滑コン
デンサと、 第１電極が前記第１のトランジスタの前記第２電極に接
続され、第２電極が前記正相検出端子に接続された第１
の平滑抵抗と、 第１電極が前記第２のトランジスタの前記第２電極に接
続され、第２電極が前記逆相検出端子に接続された第２
の平滑抵抗とを有し、 前記内部出力回路は、 制御電極が前記初段の差動増幅回路の前記正相出力端子
に接続され、第１電極が前記第１の定電圧源に接続さ
れ、第２電極が前記第２段の差動増幅回路の前記正相入
力端子に接続された第１の内部出力トランジスタと、 制御電極が前記初段の差動増幅回路の前記逆相出力端子
に接続され、第１電極が前記第１の定電圧源に接続さ
れ、第２電極が前記第２段の差動増幅回路の前記逆相入
力端子に接続された第２の内部出力トランジスタと、 前記第１の内部出力トランジスタの第２電極と前記第２
の定電圧源との間に設けられた第１の内部出力定電流源
と、 前記第２の内部出力トランジスタの第２電極と前記第２
の定電圧源との間に設けられた第２の内部出力定電流源
と を有し、 前記出力回路は、 制御電極が前記最終段の差動増幅回路の前記正相出力端
子に接続され、第１電極が前記第１の定電圧源に接続さ
れ、第２電極が前記外部正相出力端子に接続された第１
の出力トランジスタと、 制御電極が前記最終段の差動増幅回路の前記逆相出力端
子に接続され、第１電極が前記第１の定電圧源に接続さ
れ、第２電極が前記外部逆相出力端子に接続された第２
の出力トランジスタと、 前記第１の出力トランジスタの第２電極と前記第２の定
電圧源との間に設けられた第１の出力定電流源と、 前記第２の出力トランジスタの第２電極と前記第２の定
電圧源との間に設けられた第２の出力定電流源と を有す
る ことを特徴とするリミッタ増幅器。1. A differential amplifier circuit row in which a plurality of differential amplifier circuits that differentially output a positive-phase amplified signal and a negative-phase amplified signal from a positive-phase output terminal and a negative-phase output terminal are cascaded, A smoothing circuit that detects an average DC voltage of the positive-phase amplified signal and an average DC voltage of the negative-phase amplified signal in the final-stage differential amplifier circuit of the differential amplifier circuit row; A DC compensation circuit for adjusting a DC current drawn from a positive-phase output terminal and a negative-phase output terminal or a DC current flowing to these terminals in a first-stage differential amplifier circuit of the differential amplifier train so that the average DC voltage is equal; , positive-phase amplified signal and the inverse of the differential amplifier circuit of the first stage
A second stage differential amplifier circuit of the differential amplifier train
Output to the positive and negative phase input terminals at
Unit output circuit, the positive-phase amplified signal of the final-stage differential amplifier circuit and the inverted
Outputs the phase amplified signal to external positive output terminal and external negative output terminal
And a smoothing circuit, wherein a control electrode is connected to the positive-phase output terminal of the final-stage differential amplifier circuit, and a first electrode is connected to a first constant voltage source. A second transistor having a control electrode connected to the opposite-phase output terminal of the final-stage differential amplifier circuit, and a first electrode connected to the first constant-voltage source; A first constant current source provided between the second electrode of the transistor and the second constant voltage source; and a first constant current source provided between the second electrode of the second transistor and the second constant voltage source. The second constant current source and the first electrode as a positive-phase detection terminal for detecting the average DC voltage of the positive-phase amplified signal in the final-stage differential amplifier circuit.
A first electrode is connected to the second electrode of the first transistor, and a smoothing capacitor having an electrode as a reverse-phase detection terminal for detecting an average DC voltage of the reverse-phase amplified signal in the final-stage differential amplifier circuit; A first electrode having a second electrode connected to the positive phase detection terminal;
And a second electrode having a first electrode connected to the second electrode of the second transistor and a second electrode connected to the negative phase detection terminal.
Possess the a smoothing resistor, the internal output circuit, the positive-phase output terminal of the control electrode is a differential amplifier circuit of the first stage
And the first electrode is connected to the first constant voltage source.
A second electrode is connected to the positive input of the second stage differential amplifier circuit.
A first internal output transistor connected to a power terminal, and a control electrode connected to the negative-phase output terminal of the first-stage differential amplifier circuit.
And the first electrode is connected to the first constant voltage source.
A second electrode is connected to the reverse input of the second stage differential amplifier circuit.
A second internal output transistor connected to the input terminal; a second electrode of the first internal output transistor;
Internal output constant current source provided between the internal constant voltage source
A second electrode of the second internal output transistor and the second electrode;
Internal output constant current source provided between the constant current source
Has the door, said output circuit, the positive phase output terminal of the differential amplifier circuit of the control electrode is the final stage
And a first electrode connected to the first constant voltage source.
A first electrode having a second electrode connected to the external positive-phase output terminal.
And the control electrode is connected to the opposite-phase output terminal of the final-stage differential amplifier circuit.
And a first electrode connected to the first constant voltage source.
A second electrode connected to the external negative-phase output terminal.
Output transistor, a second electrode of the first output transistor, and the second constant
A first output constant current source provided between the first output constant current source and a second electrode of the second output transistor;
Having a second output constant current source provided between the voltage source
Limiting amplifier, characterized in that that.
荷抵抗を接続し、この接続点をそれぞれ前記正相出力端
子および前記逆相出力端子とするものであり、 前記直流補償回路は、 前記最終段の差動増幅回路における２つの平均直流電圧
の差分電圧に応じて、前記初段の差動増幅回路における
負荷抵抗に流れる直流電流を差動調整するものであるこ
とを特徴とする請求項１記載のリミッタ増幅器。2. The differential amplifier circuit of the first stage, wherein a load resistor is connected to each of two transistors forming a differential pair, and the connection points are respectively connected to the positive-phase output terminal and the negative-phase output terminal. The DC compensation circuit differentially adjusts a DC current flowing through a load resistor in the first-stage differential amplifier circuit according to a difference voltage between two average DC voltages in the final-stage differential amplifier circuit. 2. The limiter amplifier according to claim 1, wherein
記初段の差動増幅回路の前記正相出力端子に接続された
第３のトランジスタと、 制御電極が前記逆相検出端子に接続され、第１電極が前
記初段の差動増幅回路の前記逆相出力端子に接続され、
第２電極が前記第３のトランジスタの第２電極に接続さ
れた第４のトランジスタと、 前記第４のトランジスタの前記第２電極と前記第２の定
電圧源との間に設けられた第３の定電流源とを有するこ
とを特徴とする請求項１または２に記載のリミッタ増幅
器A third transistor having a control electrode connected to the positive-phase detection terminal and a first electrode connected to the positive-phase output terminal of the first-stage differential amplifier circuit; A control electrode is connected to the negative phase detection terminal, a first electrode is connected to the negative phase output terminal of the first stage differential amplifier circuit,
A fourth transistor having a second electrode connected to a second electrode of the third transistor; and a third transistor provided between the second electrode of the fourth transistor and the second constant voltage source. 3. The limiter amplifier according to claim 1, further comprising:
ミッタ増幅器を、多段従属接続したことを特徴とするリ
ミッタ増幅器。4. A re <br/> limiter amplifier according to any one of claims 1 to 3, a limiter amplifier, characterized in that the multi-stage cascaded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27766196A JP3344904B2 (en) | 1996-10-21 | 1996-10-21 | Limiter amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27766196A JP3344904B2 (en) | 1996-10-21 | 1996-10-21 | Limiter amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10126183A JPH10126183A (en) | 1998-05-15 |
| JP3344904B2 true JP3344904B2 (en) | 2002-11-18 |
Family
ID=17586546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27766196A Expired - Fee Related JP3344904B2 (en) | 1996-10-21 | 1996-10-21 | Limiter amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3344904B2 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE41831E1 (en) | 2000-05-23 | 2010-10-19 | Marvell International Ltd. | Class B driver |
| US7606547B1 (en) | 2000-07-31 | 2009-10-20 | Marvell International Ltd. | Active resistance summer for a transformer hybrid |
| US6483380B1 (en) * | 2000-09-18 | 2002-11-19 | Conexant Systems, Inc. | GMC filter and method for suppressing unwanted signals introduced by the filter |
| JP4494614B2 (en) * | 2000-10-13 | 2010-06-30 | Ｏｋｉセミコンダクタ株式会社 | Amplitude limiting circuit and filter circuit |
| JP4567177B2 (en) * | 2000-11-30 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | Wideband preamplifier |
| JP4544947B2 (en) * | 2004-09-15 | 2010-09-15 | 三菱電機株式会社 | Amplifier circuit |
| US7298173B1 (en) | 2004-10-26 | 2007-11-20 | Marvell International Ltd. | Slew rate control circuit for small computer system interface (SCSI) differential driver |
| US7843264B2 (en) * | 2008-01-29 | 2010-11-30 | Qualcomm, Incorporated | Differential amplifier with accurate input offset voltage |
| JP2009239330A (en) * | 2008-03-25 | 2009-10-15 | Nippon Telegr & Teleph Corp <Ntt> | Amplitude limit amplifier circuit |
| JP2011109721A (en) * | 2011-03-03 | 2011-06-02 | Nippon Telegr & Teleph Corp <Ntt> | Amplitude limit amplifier circuit |
| JP5541821B1 (en) * | 2013-02-13 | 2014-07-09 | 日本電信電話株式会社 | Amplitude detection circuit |
-
1996
- 1996-10-21 JP JP27766196A patent/JP3344904B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10126183A (en) | 1998-05-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20060267685A1 (en) | Fast settling, low noise, low offset operational amplifier and method | |
| JP3967065B2 (en) | Amplifier circuit | |
| JP3504176B2 (en) | Signal amplification circuit | |
| JP3344904B2 (en) | Limiter amplifier | |
| JP3088262B2 (en) | Low distortion differential amplifier circuit | |
| JPH04217106A (en) | Preamplifier of balanced microphone in cmos technique | |
| EP2424108B1 (en) | Amplifying circuit | |
| US5196807A (en) | Amplifying circuit | |
| CN112491369B (en) | Sensor signal processing circuit | |
| US10797665B2 (en) | Programmable gain amplifier systems and methods | |
| JP4295109B2 (en) | Power amplifier module | |
| JP3404209B2 (en) | Transimpedance amplifier circuit | |
| JP3338847B2 (en) | Class D power amplifier | |
| JP5333520B2 (en) | Amplifier circuit | |
| US4015214A (en) | Push-pull amplifier | |
| US4498054A (en) | Differential amplifier circuit | |
| JP3444667B2 (en) | Variable gain amplifier circuit | |
| WO2003028210A1 (en) | Variable gain amplifier of low power consumption | |
| JP3180821B2 (en) | Complementary amplifier circuit | |
| JPH0870223A (en) | Offset cancellation circuit | |
| JPH03154508A (en) | Amplifier circuit and bias circuit thereof | |
| US3439285A (en) | Stabilized direct-coupled amplifier | |
| JPH04119005A (en) | Operational amplifier circuit | |
| JP3360911B2 (en) | Differential amplifier circuit | |
| JPH05121971A (en) | Differential amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20020820 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070830 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080830 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090830 Year of fee payment: 7 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090830 Year of fee payment: 7 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090830 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100830 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100830 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110830 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110830 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120830 Year of fee payment: 10 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120830 Year of fee payment: 10 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120830 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130830 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |