JP3443313B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3443313B2 JP3443313B2 JP07972998A JP7972998A JP3443313B2 JP 3443313 B2 JP3443313 B2 JP 3443313B2 JP 07972998 A JP07972998 A JP 07972998A JP 7972998 A JP7972998 A JP 7972998A JP 3443313 B2 JP3443313 B2 JP 3443313B2
- Authority
- JP
- Japan
- Prior art keywords
- resin material
- glass transition
- thermal expansion
- transition temperature
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、多ピン化、高速
化対応の半導体装置に係り、外部接続端子を有するプリ
ント配線基板上にシリコンチップを搭載した半導体装置
及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device compatible with high pin count and high speed, and more particularly to a semiconductor device having a silicon chip mounted on a printed wiring board having external connection terminals and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年の電子機器の小型化、薄型化に伴い
高集積化、高密度化、多ピン化、高速化の半導体装置の
要求が高くなっている。2. Description of the Related Art With the recent miniaturization and thinning of electronic equipment, there is an increasing demand for semiconductor devices with high integration, high density, high pin count, and high speed.
【０００３】従来の半導体装置について説明する。特開
平８−８３５４号公報には、シリコンチップ封止材の熱
膨張係数とプリント配線基板の熱膨脹係数の差が±５×
１０-6／℃以内との記載がある。また、封止樹脂材、及
びプリント配線基板の熱膨張係数との関係で半導体装置
の信頼性を確保している。A conventional semiconductor device will be described. In JP-A-8-8354, the difference between the coefficient of thermal expansion of the silicon chip sealing material and the coefficient of thermal expansion of the printed wiring board is ± 5 ×.
There is a statement that it is within 10 -6 / ° C. Further, the reliability of the semiconductor device is ensured in relation to the sealing resin material and the thermal expansion coefficient of the printed wiring board.
【０００４】すなわち、シリコンチップと同等又は極め
て近い熱膨張係数、弾性率、ガラス転移温度に、基板、
封止樹脂をすることで発生応力を低減し、剥離やクラッ
クの発生を抑制し、信頼性を向上させている。しかし、
事実上、シリコンチップと同等又は極めて近い値にする
ことは不可能である。That is, the substrate, the thermal expansion coefficient, the elastic modulus and the glass transition temperature of which are the same as or very close to those of the silicon chip,
By using a sealing resin, the stress generated is reduced, the occurrence of peeling and cracks is suppressed, and the reliability is improved. But,
In fact, it is impossible to achieve a value equal to or very close to that of a silicon chip.
【０００５】さらに、特開平６一１２０６２６号公報で
は、基材の熱膨張率を電子部品より大きく且つ封止樹脂
より小さくすることで、熱膨張による悪影響を緩和させ
ている。Further, in Japanese Unexamined Patent Publication No. 61-120626, the adverse effect of thermal expansion is alleviated by making the coefficient of thermal expansion of the base material larger than that of the electronic component and smaller than that of the sealing resin.
【０００６】しかし、半導体装置の多様化に伴い、ＱＦ
Ｐ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ：クウアッド
・フラット・パッケージ）、ＴＣＰ（Ｔａｐｅ Ｃａｒ
ｉｅｒ Ｐａｃｋａｇｅ）、ＣＯＢ（Ｃｈｉｐ ｏｎ
Ｂｏｒｄ）、フリップチップ、ＢＧＡ（Ｂａｌｌ Ｇｒ
ｉｄ Ａｒｙ）、ＣＳＰ（Ｃｈｉｐ Ｓｃａｌｅ Ｐａ
ｃｋａｇｅ）等の製造で、熱膨張係数のみの関係で半導
体装置の信頼性を確保することは難しい。However, with the diversification of semiconductor devices, QF
P (Quad Flat Package), TCP (Tape Car)
tier package), COB (Chip on)
Bold), flip chip, BGA (Ball Gr)
id Ary), CSP (Chip Scale Pa)
It is difficult to secure the reliability of the semiconductor device in the manufacture of a semiconductor device, etc. because of only the coefficient of thermal expansion.
【０００７】[0007]
【発明が解決しようとする課題】上述したような従来の
半導体装置では、熱膨張係数の関係で信頼性を確保しよ
うとしているが、熱膨張係数だけの関係で半導体装置の
信頼性を確保することは難しいという問題点があった。In the conventional semiconductor device as described above, the reliability is to be ensured by the relationship of the thermal expansion coefficient, but the reliability of the semiconductor device is ensured only by the relationship of the thermal expansion coefficient. Was difficult.
【０００８】この発明は、前述した問題点を解決するた
めになされたもので、耐湿度信頼性、耐はんだリフロー
性等の信頼性と成形性に優れた半導体装置及びその製造
方法を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to obtain a semiconductor device excellent in reliability such as humidity resistance reliability, solder reflow resistance and the like and moldability, and a manufacturing method thereof. To aim.
【０００９】[0009]
【課題を解決するための手段】この発明に係る半導体装
置は、プリント配線基板上にダイボンド材によりシリコ
ンチップを搭載し、その上を封止樹脂材によりモールド
されたワイヤーボンド方式の半導体装置において、前記
プリント配線基板の熱膨脹係数をα１、ガラス転移温度
をＴｇ１とし、前記ダイボンド材の熱膨脹係数をα２、
ガラス転移温度をＴｇ２とし、前記封止樹脂材の熱膨脹
係数をα３、ガラス転移温度をＴｇ３としたときに、関
係式、Ｔｇ１≧Ｔｇ２≧Ｔｇ３、及びα１≦α２≦α３
を満たすものである。SUMMARY OF THE INVENTION A semiconductor device according to the present invention is a silicon wafer formed on a printed wiring board by a die bond material.
The-chip mounted, in the semiconductor device of a wire bonding method, which is molded with a sealing resin material thereon, said
The coefficient of thermal expansion of the printed wiring board is α1 , the glass transition temperature
Was a Tg1, the thermal expansion coefficient of the die bonding material [alpha] 2,
The glass transition temperature was Tg2, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, Tg1 ≧ Tg2 ≧ Tg3, and α1 ≦ α2 ≦ α3
To meet.
【００１０】また、この発明に係る半導体装置は、プリ
ント配線基板上にアンダーフィル材及び導電性接着樹脂
材又は異方性導電性樹脂材によりシリコンチップを搭載
し、その上を封止樹脂材によりモールドされたフリップ
チップ方式の半導体装置において、前記プリント配線基
板の熱膨脹係数をα１、ガラス転移温度をＴｇ１とし、
前記アンダーフィル材及び導電性接着樹脂材又は異方性
導電性樹脂材の熱膨脹係数をα４、ガラス転移温度をＴ
ｇ４とし、前記封止樹脂材の熱膨脹係数をα３、ガラス
転移温度をＴｇ３としたときに、関係式、Ｔｇ１≧Ｔｇ
４≧Ｔｇ３、及びα１≦α４≦α３を満たすものであ
る。Further, the semiconductor device according to the present invention, pre
A flip-chip type semiconductor device in which a silicon chip is mounted on a wiring board by an underfill material and a conductive adhesive resin material or an anisotropic conductive resin material, and a silicon resin is molded thereon by a sealing resin material. In the above, the coefficient of thermal expansion of the printed wiring board is α1 , the glass transition temperature is Tg1, and
The underfill material and the conductive adhesive resin material or anisotropy
The coefficient of thermal expansion of the conductive resin material is α 4 , the glass transition temperature is T
and g4, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, Tg1 ≧ Tg
4 ≧ Tg3 and α1 ≦ α4 ≦ α3 are satisfied.
【００１１】さらに、この発明に係る半導体装置は、プ
リント配線基板上にダイボンド材、アンダーフィル材及
び導電性接着樹脂材又は異方性導電性樹脂材により多重
シリコンチップを搭載し、その上を封止樹脂材によりモ
ールドされたスタックド方式の半導体装置において、前
記プリント配線基板の熱膨脹係数をα１、ガラス転移温
度をＴｇ１とし、前記ダイボンド材、アンダーフィル材
及び導電性接着樹脂材又は異方性導電性樹脂材の熱膨脹
係数をα５、ガラス転移温度をＴｇ５とし、前記封止樹
脂材の熱膨脹係数をα３、ガラス転移温度をＴｇ３とし
たときに、関係式、Ｔｇ１≧Ｔｇ５≧Ｔｇ３、及びα１
≦α５≦α３を満たすものである。[0011] In addition, the semiconductor device according to the invention, up
Multiple layers of die bonding material, underfill material and conductive adhesive resin material or anisotropic conductive resin material on the printed wiring board
In a stacked semiconductor device having a silicon chip mounted thereon and molded with a sealing resin material, a thermal expansion coefficient of the printed wiring board is α1 , a glass transition temperature is Tg1 , and the die bond material and the underfill material are
And thermal expansion coefficient of the conductive adhesive resin material or an anisotropic conductive resin material .alpha.5, the glass transition temperature and Tg5, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature of Tg3
When, the relational expressions, Tg1 ≧ Tg5 ≧ Tg3, and α1
It satisfies ≦ α5 ≦ α3.
【００１２】この発明に係る半導体装置の製造方法は、
プリント配線基板上にダイボンド材によりシリコンチッ
プを搭載し、その上を封止樹脂材によりモールドされた
ワイヤーボンド方式の半導体装置の製造方法において、
前記プリント配線基板の熱膨脹係数をα１、ガラス転移
温度をＴｇ１とし、前記ダイボンド材の熱膨脹係数をα
２、ガラス転移温度をＴｇ２とし、前記封止樹脂材の熱
膨脹係数をα３、ガラス転移温度をＴｇ３としたとき
に、関係式、Ｔｇ１≧Ｔｇ２≧Ｔｇ３、及びα１≦α２
≦α３を満たすものである。A method of manufacturing a semiconductor device according to the present invention is
In a method of manufacturing a wire bond type semiconductor device, in which a silicon chip is mounted on a printed wiring board by a die bond material, and a silicon resin is molded thereon by a sealing resin material,
The coefficient of thermal expansion of the printed wiring board is α 1 , the glass transition temperature is Tg 1 , and the coefficient of thermal expansion of the die bond material is α 1.
2, the glass transition temperature and Tg2, thermal <br/> expansion coefficient of the sealing resin material .alpha.3, when the glass transition temperature and Tg3
The relational expression, Tg1 ≧ Tg2 ≧ Tg3, and [alpha] 1 ≦ [alpha] 2
It satisfies ≦ α3.
【００１３】また、この発明に係る半導体装置の製造方
法は、プリント配線基板上にアンダーフィル材及び導電
性接着樹脂材又は異方性導電性樹脂材によりシリコンチ
ップを搭載し、その上を封止樹脂材によりモールドされ
たフリップチップ方式の半導体装置の製造方法におい
て、前記プリント配線基板の熱膨脹係数をα１、ガラス
転移温度をＴｇ１とし、前記アンダーフィル材及び導電
性接着樹脂材又は異方性導電性樹脂材の熱膨脹係数をα
４、ガラス転移温度をＴｇ４とし、前記封止樹脂材の熱
膨脹係数をα３、ガラス転移温度をＴｇ３としたとき
に、関係式、Ｔｇ１≧Ｔｇ４≧Ｔｇ３、及びα１≦α４
≦α３を満たすものである。Further, a method of manufacturing a semiconductor device according to the present invention, a silicon Ji <br/>-up equipped with the under-fill material and the conductive adhesive resin material or an anisotropic conductive resin material on the printed circuit board In the method of manufacturing a flip-chip type semiconductor device having a resin molded thereon with a sealing resin material, the thermal expansion coefficient of the printed wiring board is α1 , the glass transition temperature is Tg1, and the underfill material and the conductive material are electrically conductive.
Coefficient of thermal expansion of the conductive adhesive resin material or anisotropic conductive resin material is α
4, the glass transition temperature and Tg4, thermal <br/> expansion coefficient of the sealing resin material .alpha.3, when the glass transition temperature and Tg3
The relational expression, Tg1 ≧ Tg4 ≧ Tg3, and [alpha] 1 ≦ alpha 4
It satisfies ≦ α3.
【００１４】さらに、この発明に係る半導体装置の製造
方法は、プリント配線基板上にダイボンド材、アンダー
フィル材及び導電性接着樹脂材又は異方性導電性樹脂材
により多重シリコンチップを搭載し、その上を封止樹脂
材によりモールドされたスタックド方式の半導体装置の
製造方法において、前記プリント配線基板の熱膨脹係数
をα１、ガラス転移温度をＴｇ１とし、前記ダイボンド
材、アンダーフィル材及び導電性接着樹脂材又は異方性
導電性樹脂材の熱膨脹係数をα５、ガラス転移温度をＴ
ｇ５とし、前記封止樹脂材の熱膨脹係数をα３、ガラス
転移温度をＴｇ３としたときに、関係式、Ｔｇ１≧Ｔｇ
５≧Ｔｇ３、及びα１≦α５≦α３を満たすものであ
る。Furthermore, in the method of manufacturing a semiconductor device according to the present invention, a multiple silicon chip is mounted on a printed wiring board by a die bond material, an underfill material and a conductive adhesive resin material or an anisotropic conductive resin material, In a method of manufacturing a stacked type semiconductor device having an upper part molded with a sealing resin material, the coefficient of thermal expansion of the printed wiring board
The [alpha] 1, the glass transition temperature of Tg1, said die bond
Material, underfill material and conductive adhesive resin material or anisotropy
The coefficient of thermal expansion of the conductive resin material is α5 , the glass transition temperature is T
g5 and then, the thermal expansion coefficient of the sealing resin material .alpha.3, when the glass transition temperature and Tg3, relationship, Tg1 ≧ Tg
5 ≧ Tg3 and α1 ≦ α5 ≦ α3 are satisfied.
【００１５】[0015]
【発明の実施の形態】実施の形態１．この発明の実施の
形態１に係る半導体装置及びその製造方法について図面
を参照しながら説明する。図１は、この発明の実施の形
態１に係る半導体装置を示す図である。なお、各図中、
同一符号は同一又は相当部分を示す。BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention. In each figure,
The same reference numerals indicate the same or corresponding parts.
【００１６】図１において、１ははんだバンプ（ハンダ
ボールグリッド）、２はプリント配線基板、３はモール
ド（封止樹脂材）、４は金ワイヤー、５はベアチップ
（シリコンチップ）、６はダイボンド材である。In FIG. 1, 1 is a solder bump (solder ball grid), 2 is a printed wiring board, 3 is a mold (sealing resin material), 4 is a gold wire, 5 is a bare chip (silicon chip), and 6 is a die bond material. Is.
【００１７】図１は、裏面にハンダボールグリッド１を
形成したプリント配線基板２へ、表面のシリコンチップ
５の搭載面から伸びたワイヤーボンドで配線し、封止樹
脂材によりモールドした半導体装置である。FIG. 1 shows a semiconductor device in which a printed wiring board 2 having a solder ball grid 1 formed on its back surface is wired by wire bonds extending from the mounting surface of a silicon chip 5 on the front surface and molded with a sealing resin material. .
【００１８】ここでは、プリント配線基板２、ダイボン
ド材６及び封止樹脂材３のガラス転移温度、及び熱膨脹
係数をコントロールすることで高信頼性を確保する。Here, high reliability is ensured by controlling the glass transition temperature and the coefficient of thermal expansion of the printed wiring board 2, the die bond material 6 and the sealing resin material 3.
【００１９】すなわち、ワイヤーボンドによって電気接
続した高密度半導体装置において、基板２のガラス転移
温度を「Ｔｇ１」、基板２の線膨脹係数を「α１」と
し、ダイボンド材６のガラス転移温度を「Ｔｇ２」、ダ
イボンド材６の線膨脹係数を「α２」とし、封止樹脂材
３のガラス転移温度を「Ｔｇ３」、封止樹脂材３の線膨
脹係数を「α３」としたときに、以下の関係式（１）及
び（２）を満たすようにする。That is, in a high density semiconductor device electrically connected by wire bonding, the glass transition temperature of the substrate 2 is "Tg1", the linear expansion coefficient of the substrate 2 is "α1", and the glass transition temperature of the die bond material 6 is "Tg2". When the linear expansion coefficient of the die bond material 6 is “α2”, the glass transition temperature of the sealing resin material 3 is “Tg3”, and the linear expansion coefficient of the sealing resin material 3 is “α3”, the following relation Formulas (1) and (2) are satisfied.
【００２０】 Ｔｇ１≧Ｔｇ２≧Ｔｇ３ ・・・式（１）[0020] Tg1 ≧ Tg2 ≧ Tg3 ... Formula (1)
【００２１】 α１≦α２≦α３ ・・・式（２）[0021] α1 ≦ α2 ≦ α3 ... Formula (2)
【００２２】耐はんだリフロー性、プレッシャークッカ
ーテスト、高温放置等の信頼性試験における吸湿や熱に
より発生する応力による界面剥離やパッケージ内外部ク
ラック現象を抑制できる。It is possible to suppress interfacial peeling and external cracking inside the package due to stress generated by moisture absorption and heat in reliability tests such as solder reflow resistance, pressure cooker test, and high temperature storage.
【００２３】熱ストレスをかけた場合、半導体装置を構
成する材料が、温度が上がるにつれて膨脹しはじめる。
そこで、半導体装置の構成上、基板２、ダイボンド材
６、封止樹脂材３の順番、もしくは同時に膨脹をはじめ
ると、内部にストレスが発生しにくく、内外部クラック
を抑制できる。また、応力残磋も少ない。When heat stress is applied, the material forming the semiconductor device begins to expand as the temperature rises.
Therefore, in the structure of the semiconductor device, when the substrate 2, the die bond material 6, and the encapsulating resin material 3 are expanded in this order or at the same time, stress is less likely to be generated inside and cracks inside and outside can be suppressed. In addition, there are few stress remnants.
【００２４】つまり、ガラス転移温度を近似もしくは上
記の関係式を満たすように組み合わせると、ベアチップ
５周辺に発生する応力残磋が少なく、チップと基板をワ
イヤーボンドで電気接続しているＣＯＢ（Ｃｈｉｐ ｏ
ｎ Ｂｏｒｄ）には効果がある。That is, if the glass transition temperatures are approximated or combined so as to satisfy the above relational expression, the stress remnant generated around the bare chip 5 is small, and the chip and the substrate are electrically connected by a wire bond.
nBord) is effective.
【００２５】熱膨脹係数の場合は、半導体装置の土台と
なる基板２の熱膨脹係数を基準にし、基板２、ダイボン
ド材６、封止樹脂材３の順番で値を大きくしていく、又
は、同一にする方が電気接続子の断線を防ぐことに効果
がある。In the case of the coefficient of thermal expansion, the coefficient of thermal expansion of the substrate 2 which is the base of the semiconductor device is used as a reference, and the value is increased in the order of the substrate 2, the die bond material 6, and the sealing resin material 3, or the same. It is more effective to prevent disconnection of the electrical connector.
【００２６】それぞれの関係式を別々に半導体装置製造
に適用しても良いが、ガラス転移温度、及び熱膨脹係数
の関係式（１）及び（２）を合わせて用いる方が電気接
続子の断線、内外部クラック、及び、界面剥離の現象に
は十分効果がある。Although each of the relational expressions may be applied to the manufacture of a semiconductor device separately, it is better to use the relational expressions (1) and (2) of the glass transition temperature and the coefficient of thermal expansion together to break the electric connector. It is sufficiently effective for the phenomena of internal and external cracks and interfacial peeling.
【００２７】すなわち、この実施の形態１に係る半導体
装置は、基板２、ダイボンド材６、及び封止樹脂材３の
熱膨脹係数とガラス転移温度をコントロールすること
で、熱ストレスによる応力残磋を低減することができ
る。That is, in the semiconductor device according to the first embodiment, by controlling the coefficient of thermal expansion and the glass transition temperature of the substrate 2, the die bond material 6, and the encapsulating resin material 3, the stress residue due to thermal stress is reduced. can do.
【００２８】また、応力の発生する順番にガラス転移温
度によりコントロールすることで、応力が発生しても解
散する方向に進むため、応力残磋が低減され、温度リサ
イクルや、吸湿、加熱によるワイヤーボンドの断線及び
バンプずれによる電気接続子の断線、内外部クラック及
び界面剥離を抑えることができ、耐湿信頼性、耐はんだ
リフロー性などを向上することができる。Further, by controlling the glass transition temperature in the order in which stress is generated, even if stress is generated, it progresses in the direction in which it is dissociated, so that stress remnants are reduced, and wire recycling by temperature recycling, moisture absorption, and heating is performed. It is possible to suppress the disconnection of the electric connector due to the disconnection of the wire and the displacement of the bump, the internal / external crack and the interface peeling, and it is possible to improve the moisture resistance reliability and the solder reflow resistance.
【００２９】さらに、土台である基板２よりもダイボン
ド材６、封止材３の熱膨脹系数が等しい又は大きくコン
トロールした方が温度サイクルや加熱、又熱ストレスに
よる、ワイヤーボンド断線、バンプズレ等の電気接続子
の断線や、内部クラックの発生を抑えることができ、耐
湿信頼性、耐はんだリフロー性等を向上することができ
る。Further, it is preferable to control the die bond material 6 and the encapsulating material 3 so that the coefficient of thermal expansion is equal to or larger than that of the substrate 2 which is the base, and the electrical connection such as wire bond disconnection or bump deviation due to temperature cycle or heating or thermal stress. It is possible to suppress the disconnection of the child and the generation of internal cracks, and it is possible to improve the moisture resistance reliability, the solder reflow resistance, and the like.
【００３０】これにより、基板２と封止材３との接着力
を高めることができる。As a result, the adhesive force between the substrate 2 and the sealing material 3 can be increased.
【００３１】実施の形態２．この発明の実施の形態２に
係る半導体装置及びその製造方法について図面を参照し
ながら説明する。図２は、この発明の実施の形態２に係
る半導体装置を示す図である。なお、各図中、同一符号
は同一又は相当部分を示す。Embodiment 2. A semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention. In each figure, the same reference numerals indicate the same or corresponding parts.
【００３２】図２において、１ははんだバンプ（ハンダ
ボールグリッド）、２はプリント配線基板、３はモール
ド（封止樹脂材）、５はベアチップ（シリコンチッ
プ）、７はバンプ、８は導電性接着樹脂材、９はアンダ
ーフィル材である。なお、導電性接着樹脂材８の代わり
に異方性導電性樹脂材でもよい。In FIG. 2, 1 is a solder bump (solder ball grid), 2 is a printed wiring board, 3 is a mold (sealing resin material), 5 is a bare chip (silicon chip), 7 is a bump, and 8 is a conductive adhesive. Resin material, 9 is an underfill material. An anisotropic conductive resin material may be used instead of the conductive adhesive resin material 8.
【００３３】図２は、裏面にハンダボールグリッド１を
形成したプリント配線基板２へ、表面のシリコンチップ
５の下部のバンプ７と導電性接着樹脂材８により電気接
合し、封止樹脂材３によりモールドした半導体装置であ
る。In FIG. 2, the printed wiring board 2 having the solder ball grid 1 formed on the back surface is electrically joined to the bumps 7 below the silicon chip 5 on the front surface by the conductive adhesive resin material 8 and by the sealing resin material 3. It is a molded semiconductor device.
【００３４】ここでは、プリント配線基板２、アンダー
フィル材９、導電性接着樹脂材８及び封止樹脂材３のガ
ラス転移温度、及び熱膨脹係数をコントロールすること
で高信頼性を確保する。Here, high reliability is ensured by controlling the glass transition temperature and the coefficient of thermal expansion of the printed wiring board 2, the underfill material 9, the conductive adhesive resin material 8 and the sealing resin material 3.
【００３５】すなわち、フリップチップによって電気接
続した高密度半導体装置において、基板２のガラス転移
温度を「Ｔｇ１」、基板２の線膨脹係数を「α１」と
し、導電性接着樹脂材８、及びアンダーフィル材９のガ
ラス転移温度を「Ｔｇ４」、導電性接着樹脂材８、及び
アンダーフィル材９の線膨脹係数を「α４」とし、封止
樹脂材３のガラス転移温度を「Ｔｇ３」、封止樹脂材３
の線膨脹係数を「α３」としたときに、以下の関係式
（３）及び（４）を満たすようにする。That is, in a high-density semiconductor device electrically connected by flip chip, the glass transition temperature of the substrate 2 is "Tg1", the linear expansion coefficient of the substrate 2 is "α1", the conductive adhesive resin material 8 and the underfill are used. The glass transition temperature of the material 9 is “Tg4”, the linear expansion coefficient of the conductive adhesive resin material 8 and the underfill material 9 is “α4”, the glass transition temperature of the sealing resin material 3 is “Tg3”, the sealing resin Material 3
The following relational expressions (3) and (4) are satisfied when the linear expansion coefficient of is α3.
【００３６】 Ｔｇ１≧Ｔｇ４≧Ｔｇ３ ・・・式（３）[0036] Tg1 ≧ Tg4 ≧ Tg3 ... Expression (3)
【００３７】 α１≦α４≦α３ ・・・式（４）[0037] α1 ≦ α4 ≦ α3 (4)
【００３８】耐はんだリフロー性、プレッシャークッカ
ーテスト、高温放置等の信頼性試験における吸湿や熱に
より発生する応力による界面剥離やパッケージ内外部ク
ラック現象を抑制できる。It is possible to suppress interfacial peeling and internal cracking inside the package due to stress generated by moisture absorption and heat in reliability tests such as solder reflow resistance, pressure cooker test, and high temperature storage.
【００３９】熱ストレスをかけた場合、半導体装置を構
成する材料が、温度が上がるにつれて膨脹しはじめる。
そこで、半導体装置の構成上、基板２、導電性接着樹脂
材８、及びアンダーフィル材９、封止樹脂材３の順番、
もしくは同時に膨脹をはじめると、内部にストレスが発
生しにくく、内外部クラックを抑制できる。また、応力
残磋も少ない。When heat stress is applied, the material forming the semiconductor device begins to expand as the temperature rises.
Therefore, in terms of the structure of the semiconductor device, the substrate 2, the conductive adhesive resin material 8, the underfill material 9, and the sealing resin material 3 are arranged in this order,
Alternatively, if expansion starts at the same time, stress is less likely to be generated inside, and cracks inside and outside can be suppressed. In addition, there are few stress remnants.
【００４０】つまり、ガラス転移温度を近似もしくは上
記の関係式を満たすように組み合わせると、ベアチップ
５周辺に発生する応力残磋が少なく、チップにバンプを
付けて直接電気接続しているフリップチップには効果が
ある。That is, if the glass transition temperatures are combined so as to approximate or satisfy the above relational expressions, the stress remnants generated around the bare chip 5 are small, and the flip chip directly bumped and electrically connected to the chip. effective.
【００４１】熱膨脹係数の場合は、半導体装置の土台と
なる基板２の熱膨脹係数を基準にし、基板２、導電性接
着樹脂材８、及びアンダーフィル材９、封止樹脂材３の
順番で値を大きくしていく、又は、同一にする方が電気
接続子の断線を防ぐことに効果がある。In the case of the coefficient of thermal expansion, the values are set in the order of the substrate 2, the conductive adhesive resin material 8, the underfill material 9 and the sealing resin material 3 with reference to the thermal expansion coefficient of the substrate 2 which is the base of the semiconductor device. Increasing the size or making them the same is effective in preventing disconnection of the electrical connector.
【００４２】それぞれの関係式を別々に半導体装置製造
に適用しても良いが、ガラス転移温度、及び熱膨脹係数
の関係式（３）及び（４）を合わせて用いる方が電気接
続子の断線、内外部クラック、及び、界面剥離の現象に
は十分効果がある。Although each of the relational expressions may be applied to the manufacture of the semiconductor device separately, it is better to use the relational expressions (3) and (4) of the glass transition temperature and the coefficient of thermal expansion together to break the electric connector. It is sufficiently effective for the phenomena of internal and external cracks and interfacial peeling.
【００４３】実施の形態３．この発明の実施の形態３に
係る半導体装置及びその製造方法について図面を参照し
ながら説明する。図３は、この発明の実施の形態３に係
る半導体装置を示す図である。なお、各図中、同一符号
は同一又は相当部分を示す。Embodiment 3. A semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a diagram showing a semiconductor device according to a third embodiment of the present invention. In each figure, the same reference numerals indicate the same or corresponding parts.
【００４４】図３において、１ははんだバンプ（ハンダ
ボールグリッド）、２はプリント配線基板、３はモール
ド（封止樹脂材）、４は金ワイヤー、５はベアチップ
（シリコンチップ）、６はダイボンド材、７はバンプ、
８は導電性接着樹脂材、９はアンダーフィル材である。
なお、導電性接着樹脂材８の代わりに異方性導電性樹脂
材でもよい。In FIG. 3, 1 is a solder bump (solder ball grid), 2 is a printed wiring board, 3 is a mold (sealing resin material), 4 is a gold wire, 5 is a bare chip (silicon chip), and 6 is a die bond material. , 7 is a bump,
Reference numeral 8 is a conductive adhesive resin material, and 9 is an underfill material.
An anisotropic conductive resin material may be used instead of the conductive adhesive resin material 8.
【００４５】図３は、裏面にハンダボールグリッド１を
形成したプリント配線基板２へ、表面の多重シリコンチ
ップ（スタックド）５の下部のバンプと導電性接着樹脂
材８又はワイヤーボンドで電気接合し、封止樹脂材３に
よりモールドした半導体装置である。シリコンチップ搭
載面から、ワイヤーボンドやバンプによる配線を施し、
封止樹脂材３によりモールドした半導体装置である。In FIG. 3, bumps under the multiple silicon chips (stacked) 5 on the front surface are electrically connected to a printed wiring board 2 having a solder ball grid 1 formed on the back surface by a conductive adhesive resin material 8 or wire bond, The semiconductor device is molded with the sealing resin material 3. Wiring is performed from the silicon chip mounting surface by wire bonds and bumps,
The semiconductor device is molded with the sealing resin material 3.
【００４６】ここでは、プリント配線基板２、ダイボン
ド材６、導電性接着樹脂材８、アンダーフィル材９及び
封止樹脂材３のガラス転移温度、及び熱膨脹係数をコン
トロールすることで高信頼性を確保する。Here, high reliability is ensured by controlling the glass transition temperature and the coefficient of thermal expansion of the printed wiring board 2, the die bond material 6, the conductive adhesive resin material 8, the underfill material 9 and the sealing resin material 3. To do.
【００４７】つまり、ベアチップを多層化又はマルチチ
ップ化させたＣＯＢ、ＣＳＰ又はＢＧＡにおいて、基板
２のガラス転移温度を「Ｔｇ１」、基板２の線膨脹係数
を「α１」とし、ダイボンド材６、導電性接着樹脂材
８、及びアンダーフィル材９のガラス転移温度を「Ｔｇ
５」、ダイボンド材６、導電性接着樹脂材８、及びアン
ダーフィル材９の線膨脹係数を「α５」とし、封止樹脂
材３のガラス転移温度を「Ｔｇ３」、封止樹脂材３の線
膨脹係数を「α３」としたとき、以下の関係式（５）及
び（６）を満たす特性値により製造する。That is, in COB, CSP or BGA in which bare chips are multilayered or multi-chips, the glass transition temperature of the substrate 2 is “Tg1”, the linear expansion coefficient of the substrate 2 is “α1”, the die bond material 6 and the conductive material are conductive. The glass transition temperature of the adhesive resin material 8 and the underfill material 9 is set to “Tg
5 ”, the die bond material 6, the conductive adhesive resin material 8, and the underfill material 9 have a coefficient of linear expansion of“ α5 ”, the glass transition temperature of the sealing resin material 3 is“ Tg3 ”, and the line of the sealing resin material 3 is When the expansion coefficient is “α3”, the manufacturing is performed with the characteristic values satisfying the following relational expressions (5) and (6).
【００４８】 Ｔｇ１≧Ｔｇ５≧Ｔｇ３ ・・・式（５）[0048] Tg1 ≧ Tg5 ≧ Tg3 ... Formula (5)
【００４９】 α１≦α５≦α３ ・・・式（６）[0049] α1 ≦ α5 ≦ α3 ... Formula (6)
【００５０】実施の形態４．この発明の実施の形態４に
係る半導体装置及びその製造方法について図面を参照し
ながら説明する。図４は、この発明の実施の形態４に係
る半導体装置を示す図である。なお、各図中、同一符号
は同一又は相当部分を示す。Fourth Embodiment A semiconductor device and a manufacturing method thereof according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a diagram showing a semiconductor device according to a fourth embodiment of the present invention. In each figure, the same reference numerals indicate the same or corresponding parts.
【００５１】図４において、２はプリント配線基板、１
０は電子部品、２０はワイヤーボンド方式ＣＯＢであ
る。In FIG. 4, 2 is a printed wiring board, 1
Reference numeral 0 is an electronic component, and 20 is a wire bond type COB.
【００５２】図４は、他の電子部品１０が実装されてい
るプリント配線基板２に、直接実装したベアチップにワ
イヤーボンドにより電気接続し、封止樹脂材によりモー
ルドしたＣＯＢ（Ｃｈｉｐ ｏｎ Ｂｏａｄ）を施すも
のである。In FIG. 4, a printed wiring board 2 on which another electronic component 10 is mounted is electrically connected to a directly mounted bare chip by wire bonding, and a COB (Chip on Board) molded with a sealing resin material is applied. It is a thing.
【００５３】ここでは、基板２、ダイボンド材及び封止
樹脂材のガラス転移温度、及び熱膨脹係数をコントロー
ルすることで高信頼性を確保する。Here, high reliability is ensured by controlling the glass transition temperature and the coefficient of thermal expansion of the substrate 2, the die bond material and the sealing resin material.
【００５４】実施の形態５．この発明の実施の形態５に
係る半導体装置及びその製造方法について図面を参照し
ながら説明する。図５は、この発明の実施の形態５に係
る半導体装置を示す図である。なお、各図中、同一符号
は同一又は相当部分を示す。Embodiment 5. A semiconductor device and a manufacturing method thereof according to a fifth embodiment of the present invention will be described with reference to the drawings. 5 is a diagram showing a semiconductor device according to a fifth embodiment of the present invention. In each figure, the same reference numerals indicate the same or corresponding parts.
【００５５】図５において、２はプリント配線基板、１
０は電子部品、３０はスタックド方式ＣＯＢである。In FIG. 5, 2 is a printed wiring board, and 1 is
Reference numeral 0 is an electronic component, and 30 is a stacked COB.
【００５６】図５は、他の電子部品１０が実装されてい
るプリント配線基板２に、多層構造のベアチップ（スタ
ックド）のバンプを介して導電性接着樹脂材、異方性導
電性樹脂材又はワイヤーボンドにより電気接続し、封止
樹脂材によりモールドしたＣＯＢ（Ｃｈｉｐ ｏｎ Ｂ
ｏａｄ）を施すものである。In FIG. 5, a conductive adhesive resin material, an anisotropic conductive resin material or a wire is mounted on a printed wiring board 2 on which another electronic component 10 is mounted, via bumps of bare chips (stacked) having a multilayer structure. COB (Chip on B) electrically connected by a bond and molded by a sealing resin material
Oad).
【００５７】ここでは、基板、ダイボンド材、アンダー
フィル材、導電性接着樹脂材、異方性導電性樹脂材及び
封止樹脂材のガラス転移温度、及び熱膨脹係数をコント
ロールすることで高信頼性を確保する。Here, high reliability is achieved by controlling the glass transition temperature and the coefficient of thermal expansion of the substrate, the die bond material, the underfill material, the conductive adhesive resin material, the anisotropic conductive resin material and the sealing resin material. Secure.
【００５８】実施の形態６．この発明の実施の形態６に
係る半導体装置及びその製造方法について図面を参照し
ながら説明する。図６は、この発明の実施の形態６に係
る半導体装置を示す図である。なお、各図中、同一符号
は同一又は相当部分を示す。Sixth Embodiment A semiconductor device and a manufacturing method thereof according to a sixth embodiment of the present invention will be described with reference to the drawings. 6 is a diagram showing a semiconductor device according to a sixth embodiment of the present invention. In each figure, the same reference numerals indicate the same or corresponding parts.
【００５９】図６において、２はプリント配線基板、１
０は電子部品、４０はフリップチップ方式ＣＯＢであ
る。In FIG. 6, 2 is a printed wiring board, and 1 is
Reference numeral 0 is an electronic component, and 40 is a flip-chip type COB.
【００６０】図６は、他の電子部品１０が実装されてい
るプリント配線基板２に、ベアチップのパンブを介して
導電性接着樹脂材、異方性導電性樹脂材により電気接続
し、封止樹脂材によりモールドしたＣＯＢ（Ｃｈｉｐ
ｏｎ Ｂｏａｄ）を施すものである。In FIG. 6, the printed wiring board 2 on which the other electronic component 10 is mounted is electrically connected by a conductive adhesive resin material or an anisotropic conductive resin material via a bare chip bump, and a sealing resin is formed. COB (Chip) molded with material
on Board).
【００６１】ここでは、基板、導電性接着樹脂材、異方
性導電性樹脂材及び封止樹脂材のガラス転移温度、及び
熱膨脹係数をコントロールすることで高信頼性を確保す
る。Here, high reliability is ensured by controlling the glass transition temperature and the coefficient of thermal expansion of the substrate, the conductive adhesive resin material, the anisotropic conductive resin material and the sealing resin material.
【００６２】[0062]
【発明の効果】この発明に係る半導体装置は、以上説明
したとおり、プリント配線基板上にダイボンド材により
シリコンチップを搭載し、その上を封止樹脂材によりモ
ールドされたワイヤーボンド方式の半導体装置におい
て、前記プリント配線基板の熱膨脹係数をα１、ガラス
転移温度をＴｇ１とし、前記ダイボンド材の熱膨脹係数
をα２、ガラス転移温度をＴｇ２とし、前記封止樹脂材
の熱膨脹係数をα３、ガラス転移温度をＴｇ３としたと
きに、関係式、Ｔｇ１≧Ｔｇ２≧Ｔｇ３、及びα１≦α
２≦α３を満たすので、熱ストレスにより発生する応力
を低減し、また応力残磋を少なくすることにより基板と
封止樹脂材との密着力を高めることができ、従来の温度
サイクル試験や吸湿、加熱により発生しやすい界面での
剥離並びにクラックを抑えることができるという効果を
奏する。As described above, the semiconductor device according to the present invention has a die-bonding material on the printed wiring board.
In a wire bond type semiconductor device in which a silicon chip is mounted and which is molded with a sealing resin material, the coefficient of thermal expansion of the printed wiring board is α1 , the glass transition temperature is Tg1, and the coefficient of thermal expansion of the die bond material is
The [alpha] 2, the glass transition temperature of Tg2, the sealing resin material
The coefficient of thermal expansion of α3 and the glass transition temperature of Tg3 are
Then, the relational expressions, Tg1 ≧ Tg2 ≧ Tg3, and α1 ≦ α
Since 2 ≦ α3 is satisfied, the stress generated by thermal stress can be reduced, and the adhesive strength between the substrate and the encapsulating resin material can be increased by reducing the stress remnants. It is possible to suppress the peeling and cracks at the interface which are likely to occur due to heating.
【００６３】また、この発明に係る半導体装置は、以上
説明したとおり、プリント配線基板上にアンダーフィル
材及び導電性接着樹脂材又は異方性導電性樹脂材により
シリコンチップを搭載し、その上を封止樹脂材によりモ
ールドされたフリップチップ方式の半導体装置におい
て、前記プリント配線基板の熱膨脹係数をα１、ガラス
転移温度をＴｇ１とし、前記アンダーフィル材及び導電
性接着樹脂材又は異方性導電性樹脂材の熱膨脹係数をα
４、ガラス転移温度をＴｇ４とし、前記封止樹脂材の熱
膨脹係数をα３、ガラス転移温度をＴｇ３としたとき
に、関係式、Ｔｇ１≧Ｔｇ４≧Ｔｇ３、及びα１≦α４
≦α３を満たすので、熱ストレスにより発生する応力を
低減し、また応力残磋を少なくすることにより基板と封
止樹脂材との密着力を高めることができ、従来の温度サ
イクル試験や吸湿、加熱により発生しやすい界面での剥
離並びにクラックを抑えることができるという効果を奏
する。Further, as described above, the semiconductor device according to the present invention is provided with the underfill material and the conductive adhesive resin material or the anisotropic conductive resin material on the printed wiring board.
In a flip-chip type semiconductor device in which a silicon chip is mounted and which is molded with a sealing resin material, a thermal expansion coefficient of the printed wiring board is α1 , a glass transition temperature is Tg1, and the underfill material and the conductive material are electrically conductive.
Coefficient of thermal expansion of the conductive adhesive resin material or anisotropic conductive resin material is α
4, the glass transition temperature and Tg4, thermal <br/> expansion coefficient of the sealing resin material .alpha.3, when the glass transition temperature and Tg3
The relational expression, Tg1 ≧ Tg4 ≧ Tg3, and [alpha] 1 ≦ alpha 4
Since ≦ α3 is satisfied, the stress generated by thermal stress can be reduced, and the adhesive strength between the substrate and the encapsulating resin material can be increased by reducing the stress remnants, and the conventional temperature cycle test, moisture absorption, heating This has the effect of suppressing peeling and cracking at the interface that tends to occur.
【００６４】さらに、この発明に係る半導体装置は、以
上説明したとおり、プリント配線基板上にダイボンド
材、アンダーフィル材及び導電性接着樹脂材又は異方性
導電性樹脂材により多重シリコンチップを搭載し、その
上を封止樹脂材によりモールドされたスタックド方式の
半導体装置において、前記プリント配線基板の熱膨脹係
数をα１、ガラス転移温度をＴｇ１とし、前記ダイボン
ド材、アンダーフィル材及び導電性接着樹脂材又は異方
性導電性樹脂材の熱膨脹係数をα５、ガラス転移温度を
Ｔｇ５とし、前記封止樹脂材の熱膨脹係数をα３、ガラ
ス転移温度をＴｇ３としたときに、関係式、Ｔｇ１≧Ｔ
ｇ５≧Ｔｇ３、及びα１≦α５≦α３を満たすので、熱
ストレスにより発生する応力を低減し、また応力残磋を
少なくすることにより基板と封止樹脂材との密着力を高
めることができ、従来の温度サイクル試験や吸湿、加熱
により発生しやすい界面での剥離並びにクラックを抑え
ることができるという効果を奏する。Further, in the semiconductor device according to the present invention, as described above, the multiple silicon chips are mounted on the printed wiring board by the die bond material, the underfill material and the conductive adhesive resin material or the anisotropic conductive resin material. In the stacked semiconductor device having a sealing resin material molded thereon, the coefficient of thermal expansion of the printed wiring board is α1 , the glass transition temperature is Tg1 , and the die bond
Material, underfill material and conductive adhesive resin material or anisotropic
The thermal expansion coefficient of sex electroconductive resin .alpha.5, the glass transition temperature and Tg5, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, Tg1 ≧ T
Since g5 ≧ Tg3 and α1 ≦ α5 ≦ α3 are satisfied, the stress generated by thermal stress can be reduced, and the adhesive strength between the substrate and the sealing resin material can be increased by reducing the stress remnant. It is possible to suppress the peeling and cracks at the interface that are likely to occur due to the temperature cycle test, moisture absorption, and heating.
【００６５】この発明に係る半導体装置の製造方法は、
以上説明したとおり、プリント配線基板上にダイボンド
材によりシリコンチップを搭載し、その上を封止樹脂材
によりモールドされたワイヤーボンド方式の半導体装置
の製造方法において、前記プリント配線基板の熱膨脹係
数をα１、ガラス転移温度をＴｇ１とし、前記ダイボン
ド材の熱膨脹係数をα２、ガラス転移温度をＴｇ２と
し、前記封止樹脂材の熱膨脹係数をα３、ガラス転移温
度をＴｇ３としたときに、関係式、Ｔｇ１≧Ｔｇ２≧Ｔ
ｇ３、及びα１≦α２≦α３を満たすので、熱ストレス
により発生する応力を低減し、また応力残磋を少なくす
ることにより基板と封止樹脂材との密着力を高めること
ができ、従来の温度サイクル試験や吸湿、加熱により発
生しやすい界面での剥離並びにクラックを抑えることが
できるという効果を奏する。A method of manufacturing a semiconductor device according to the present invention is
As described above, in the method for manufacturing a wire bond type semiconductor device in which a silicon chip is mounted on a printed wiring board by a die bonding material and is molded with a sealing resin material, the coefficient of thermal expansion of the printed wiring board is α1. the glass transition temperature of Tg1, said die bonding
The thermal expansion coefficient of the material is α2 , and the glass transition temperature is Tg2 .
And, the thermal expansion coefficient of the sealing resin material .alpha.3, when the glass transition temperature and Tg3, relationship, Tg1 ≧ Tg2 ≧ T
Since g3 and α1 ≦ α2 ≦ α3 are satisfied, the stress generated by thermal stress can be reduced, and the adhesive strength between the substrate and the sealing resin material can be increased by reducing the stress remnants. This has the effect of suppressing peeling and cracks at the interface that are likely to occur due to a cycle test, moisture absorption, and heating.
【００６６】また、この発明に係る半導体装置の製造方
法は、以上説明したとおり、プリント配線基板上にアン
ダーフィル材及び導電性接着樹脂材又は異方性導電性樹
脂材によりシリコンチップを搭載し、その上を封止樹脂
材によりモールドされたフリップチップ方式の半導体装
置の製造方法において、前記プリント配線基板の熱膨脹
係数をα１、ガラス転移温度をＴｇ１とし、前記アンダ
ーフィル材及び導電性接着樹脂材又は異方性導電性樹脂
材の熱膨脹係数をα４、ガラス転移温度をＴｇ４とし、
前記封止樹脂材の熱膨脹係数をα３、ガラス転移温度を
Ｔｇ３としたときに、関係式、Ｔｇ１≧Ｔｇ４≧Ｔｇ
３、及びα１≦α４≦α３を満たすので、熱ストレスに
より発生する応力を低減し、また応力残磋を少なくする
ことにより基板と封止樹脂材との密着力を高めることが
でき、従来の温度サイクル試験や吸湿、加熱により発生
しやすい界面での剥離並びにクラックを抑えることがで
きるという効果を奏する。As described above, the method for manufacturing a semiconductor device according to the present invention mounts a silicon chip on a printed wiring board with an underfill material and a conductive adhesive resin material or an anisotropic conductive resin material, the method of manufacturing a semiconductor device flip-chip method, which is molded with a sealing resin material thereon, the thermal expansion coefficient of the printed wiring board [alpha] 1, the glass transition temperature of Tg1, said under-
-Fill material and conductive adhesive resin material or anisotropic conductive resin
The thermal expansion coefficient of the wood alpha 4, a glass transition temperature of Tg4,
The thermal expansion coefficient of the sealing resin material .alpha.3, when the glass transition temperature and Tg3, relationship, Tg1 ≧ Tg4 ≧ Tg
3 and α1 ≦ α4 ≦ α3 are satisfied, the stress generated by thermal stress can be reduced, and the stress remnant can be reduced to enhance the adhesion between the substrate and the sealing resin material. This has the effect of suppressing peeling and cracks at the interface that are likely to occur due to a cycle test, moisture absorption, and heating.
【００６７】さらに、この発明に係る半導体装置の製造
方法は、以上説明したとおり、プリント配線基板上にダ
イボンド材、アンダーフィル材及び導電性接着樹脂材又
は異方性導電性樹脂材により多重シリコンチップを搭載
し、その上を封止樹脂材によりモールドされたスタック
ド方式の半導体装置の製造方法において、前記プリント
配線基板の熱膨脹係数をα１、ガラス転移温度をＴｇ１
とし、前記ダイボンド材、アンダーフィル材及び導電性
接着樹脂材又は異方性導電性樹脂材の熱膨脹係数をα
５、ガラス転移温度をＴｇ５とし、前記封止樹脂材の熱
膨脹係数をα３、ガラス転移温度をＴｇ３としたとき
に、関係式、Ｔｇ１≧Ｔｇ５≧Ｔｇ３、及びα１≦α５
≦α３を満たすので、熱ストレスにより発生する応力を
低減し、また応力残磋を少なくすることにより基板と封
止樹脂材との密着力を高めることができ、従来の温度サ
イクル試験や吸湿、加熱により発生しやすい界面での剥
離並びにクラックを抑えることができるという効果を奏
する。Further, as described above, the method for manufacturing a semiconductor device according to the present invention provides a multiple silicon chip on a printed wiring board by using a die bond material, an underfill material and a conductive adhesive resin material or an anisotropic conductive resin material. the mounting <br/>, in the manufacturing method of a semiconductor device molded stacked manner by a sealing resin material thereon, said print
The coefficient of thermal expansion of the wiring board is α1 , the glass transition temperature is Tg1
And the die bond material, underfill material, and conductivity
The thermal expansion coefficient of the adhesive resin material or the anisotropic conductive resin material is α
5, the glass transition temperature and Tg5, thermal <br/> expansion coefficient of the sealing resin material .alpha.3, when the glass transition temperature and Tg3
The relational expression, Tg1 ≧ Tg5 ≧ Tg3, and [alpha] 1 ≦ .alpha.5
Since ≦ α3 is satisfied, the stress generated by thermal stress can be reduced, and the adhesive strength between the substrate and the encapsulating resin material can be increased by reducing the stress remnants, and the conventional temperature cycle test, moisture absorption, heating This has the effect of suppressing peeling and cracking at the interface that tends to occur.
【図１】 この発明の実施の形態１に係る半導体装置を
示す図である。FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.
【図２】 この発明の実施の形態２に係る半導体装置を
示す図である。FIG. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention.
【図３】 この発明の実施の形態３に係る半導体装置を
示す図である。FIG. 3 is a diagram showing a semiconductor device according to a third embodiment of the present invention.
【図４】 この発明の実施の形態４に係る半導体装置を
示す図である。FIG. 4 is a diagram showing a semiconductor device according to a fourth embodiment of the present invention.
【図５】 この発明の実施の形態５に係る半導体装置を
示す図である。FIG. 5 is a diagram showing a semiconductor device according to a fifth embodiment of the present invention.
【図６】 この発明の実施の形態６に係る半導体装置を
示す図である。FIG. 6 is a diagram showing a semiconductor device according to a sixth embodiment of the present invention.
１ はんだバンプ（ハンダボールグリッド）、２ プリ
ント配線基板、３ モールド（封止樹脂材）、４ 金ワ
イヤー、５ ベアチップ（シリコンチップ）、６ ダイ
ボンド材、７ バンプ、８ 導電性接着樹脂又は異方性
導電性樹脂材、９ アンダーフィル材、１０ 電子部
品、２０ ワイヤーボンド方式ＣＯＢ、３０ スタック
ド方式ＣＯＢ、４０ フリップチップ方式ＣＯＢ。1 solder bump (solder ball grid), 2 printed wiring board, 3 mold (sealing resin material), 4 gold wire, 5 bare chip (silicon chip), 6 die bond material, 7 bump, 8 conductive adhesive resin or anisotropy Conductive resin material, 9 underfill material, 10 electronic parts, 20 wire bond type COB, 30 stacked type COB, 40 flip chip type COB.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 25/07 25/18 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/29 H01L 21/52 H01L 25/065 H01L 25/07 H01L 25/18 H01L 21/60 311 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 identification code FI H01L 25/07 25/18 (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/29 H01L 21/52 H01L 25/065 H01L 25/07 H01L 25/18 H01L 21/60 311
Claims (6)
りシリコンチップを搭載し、その上を封止樹脂材により
モールドされたワイヤーボンド方式の半導体装置におい
て、 前記プリント配線基板の熱膨脹係数をα１、ガラス転移
温度をＴｇ１とし、 前記ダイボンド材の熱膨脹係数をα２、ガラス転移温度
をＴｇ２とし、 前記封止樹脂材の熱膨脹係数をα３、ガラス転移温度を
Ｔｇ３としたときに、 関係式、Ｔｇ１≧Ｔｇ２≧Ｔｇ３、 及びα１≦α２≦α３ を満たすことを特徴とする半導体装置。1. A wire bond type semiconductor device in which a silicon chip is mounted on a printed wiring board by a die-bonding material, and a silicon resin is molded on the printed wiring board by a sealing resin material, wherein the thermal expansion coefficient of the printed wiring board is α 1 , and the glass transition. The temperature is Tg1 , the coefficient of thermal expansion of the die-bonding material is α2 , the glass transition temperature
Was a Tg2, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, wherein a satisfying Tg1 ≧ Tg2 ≧ Tg3, and α1 ≦ α2 ≦ α3.
及び導電性接着樹脂材又は異方性導電性樹脂材によりシ
リコンチップを搭載し、その上を封止樹脂材によりモー
ルドされたフリップチップ方式の半導体装置において、 前記プリント配線基板の熱膨脹係数をα１、ガラス転移
温度をＴｇ１とし、 前記アンダーフィル材及び導電性接着樹脂材又は異方性
導電性樹脂材の熱膨脹係数をα４、ガラス転移温度をＴ
ｇ４とし、 前記封止樹脂材の熱膨脹係数をα３、ガラス転移温度を
Ｔｇ３としたときに、 関係式、Ｔｇ１≧Ｔｇ４≧Ｔｇ３、 及びα１≦α４≦α３ を満たすことを特徴とする半導体装置。 Sheet by wherein underfill material on the printed circuit board and the conductive adhesive resin material or an anisotropic conductive resin material
In a flip-chip type semiconductor device in which a recon chip is mounted and which is molded with a sealing resin material, a thermal expansion coefficient of the printed wiring board is α1 , a glass transition temperature is Tg1, and the underfill material and the conductive adhesive are Resin material or anisotropic
The coefficient of thermal expansion of the conductive resin material is α 4 , the glass transition temperature is T
and g4, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, wherein a satisfying Tg1 ≧ Tg4 ≧ Tg3, and α1 ≦ α4 ≦ α3.
ンダーフィル材及び導電性接着樹脂材又は異方性導電性
樹脂材により多重シリコンチップを搭載し、その上を封
止樹脂材によりモールドされたスタックド方式の半導体
装置において、 前記プリント配線基板の熱膨脹係数をα１、ガラス転移
温度をＴｇ１とし、 前記ダイボンド材、アンダーフィル材及び導電性接着樹
脂材又は異方性導電性樹脂材の熱膨脹係数をα５、ガラ
ス転移温度をＴｇ５とし、 前記封止樹脂材の熱膨脹係数をα３、ガラス転移温度を
Ｔｇ３としたときに、 関係式、Ｔｇ１≧Ｔｇ５≧Ｔｇ３、 及びα１≦α５≦α３ を満たすことを特徴とする半導体装置。3. A stacked body in which a multiple silicon chip is mounted on a printed wiring board by a die bond material, an underfill material and a conductive adhesive resin material or an anisotropic conductive resin material, and a stacked resin chip is molded thereon with a sealing resin material. In the semiconductor device of the type, the coefficient of thermal expansion of the printed wiring board is α1 , the glass transition temperature is Tg1 , and the die bond material, the underfill material and the conductive adhesive resin are used.
The thermal expansion coefficient of fat material or an anisotropic conductive resin material .alpha.5, the glass transition temperature and Tg5, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, Tg1 ≧ Tg5 A semiconductor device satisfying ≧ Tg3 and α1 ≦ α5 ≦ α3.
りシリコンチップを搭載し、その上を封止樹脂材により
モールドされたワイヤーボンド方式の半導体装置の製造
方法において、前記プリント配線基板の 熱膨脹係数をα１、ガラス転移
温度をＴｇ１とし、 前記ダイボンド材の熱膨脹係数をα２、ガラス転移温度
をＴｇ２とし、前記封止樹脂材の 熱膨脹係数をα３、ガラス転移温度を
Ｔｇ３としたときに、 関係式、Ｔｇ１≧Ｔｇ２≧Ｔｇ３、 及びα１≦α２≦α３ を満たすことを特徴とする半導体装置の製造方法。 4. In a method of manufacturing a wire bond type semiconductor device, in which a silicon chip is mounted on a printed wiring board by a die-bonding material and is molded with a sealing resin material, a thermal expansion coefficient of the printed wiring board is α1. , The glass transition temperature is Tg1 , the coefficient of thermal expansion of the die-bonding material is α2 , the glass transition temperature
Was a Tg2, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, a semiconductor device and satisfies the Tg1 ≧ Tg2 ≧ Tg3, and α1 ≦ α2 ≦ α3 Production method.
び導電性接着樹脂材又は異方性導電性樹脂材によりシリ
コンチップを搭載し、その上を封止樹脂材によりモール
ドされたフリップチップ方式の半導体装置の製造方法に
おいて、前記プリント配線基板の 熱膨脹係数をα１、ガラス転移
温度をＴｇ１とし、 前記アンダーフィル材及び導電性接着樹脂材又は異方性
導電性樹脂材の熱膨脹係数をα４、ガラス転移温度をＴ
ｇ４とし、前記封止樹脂材の 熱膨脹係数をα３、ガラス転移温度を
Ｔｇ３としたときに、 関係式、Ｔｇ１≧Ｔｇ４≧Ｔｇ３、 及びα１≦α４≦α３ を満たすことを特徴とする半導体装置の製造方法。5. A silicon by the underfill material and the conductive adhesive resin material or an anisotropic conductive resin material on the printed circuit board
Equipped with con chip, the manufacturing method of the semiconductor device flip-chip method, which is molded with a sealing resin material thereon, the thermal expansion coefficient of the printed wiring board [alpha] 1, the glass transition temperature of Tg1, the underfill material and Conductive adhesive resin material or anisotropic
The coefficient of thermal expansion of the conductive resin material is α 4 , the glass transition temperature is T
and g4, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, manufacturing of semiconductor devices and satisfies the Tg1 ≧ Tg4 ≧ Tg3, and α1 ≦ α4 ≦ α3 Method.
ンダーフィル材及び導電性接着樹脂材又は異方性導電性
樹脂材により多重シリコンチップを搭載し、その上を封
止樹脂材によりモールドされたスタックド方式の半導体
装置の製造方法において、前記プリント配線基板の 熱膨脹係数をα１、ガラス転移
温度をＴｇ１とし、 前記ダイボンド材、アンダーフィル材及び導電性接着樹
脂材又は異方性導電性樹脂材の熱膨脹係数をα５、ガラ
ス転移温度をＴｇ５とし、前記封止樹脂材の 熱膨脹係数をα３、ガラス転移温度を
Ｔｇ３としたときに、 関係式、Ｔｇ１≧Ｔｇ５≧Ｔｇ３、 及びα１≦α５≦α３ を満たすことを特徴とする半導体装置の製造方法。6. A stacked body in which a multiple silicon chip is mounted on a printed wiring board by a die bond material, an underfill material and a conductive adhesive resin material or an anisotropic conductive resin material, and a stacked resin chip is molded thereon with a sealing resin material. In the method of manufacturing a semiconductor device of the type, the coefficient of thermal expansion of the printed wiring board is α1 , the glass transition temperature is Tg1 , and the die bond material, the underfill material and the conductive adhesive resin are used.
The thermal expansion coefficient of fat material or an anisotropic conductive resin material .alpha.5, the glass transition temperature and Tg5, the thermal expansion coefficient of the sealing resin material .alpha.3, the glass transition temperature is taken as Tg3, relationship, Tg1 ≧ Tg5 A manufacturing method of a semiconductor device, wherein ≧ Tg3 and α1 ≦ α5 ≦ α3 are satisfied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07972998A JP3443313B2 (en) | 1998-03-26 | 1998-03-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07972998A JP3443313B2 (en) | 1998-03-26 | 1998-03-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11274375A JPH11274375A (en) | 1999-10-08 |
| JP3443313B2 true JP3443313B2 (en) | 2003-09-02 |
Family
ID=13698304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07972998A Expired - Fee Related JP3443313B2 (en) | 1998-03-26 | 1998-03-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3443313B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4872180B2 (en) * | 2001-09-25 | 2012-02-08 | 日立化成工業株式会社 | Semiconductor mounting substrate and semiconductor package |
| US20060189119A1 (en) * | 2005-01-24 | 2006-08-24 | Michael Jin | Encapsulation of circuit components to reduce thermal cycling stress |
| JP5502268B2 (en) | 2006-09-14 | 2014-05-28 | 信越化学工業株式会社 | Resin composition set for system-in-package semiconductor devices |
| JP2009260302A (en) * | 2008-03-28 | 2009-11-05 | Toppan Printing Co Ltd | Semiconductor package |
| JP5213736B2 (en) * | 2009-01-29 | 2013-06-19 | パナソニック株式会社 | Semiconductor device |
| JP5261255B2 (en) * | 2009-03-27 | 2013-08-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP5250524B2 (en) * | 2009-10-14 | 2013-07-31 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP5877291B2 (en) * | 2010-05-14 | 2016-03-08 | パナソニックＩｐマネジメント株式会社 | Semiconductor device and manufacturing method thereof |
| CN108088954A (en) * | 2017-11-30 | 2018-05-29 | 郑州宇通重工有限公司 | A kind of used in new energy vehicles high-voltage wiring harness waterproof material experimental rig |
| JP2022181815A (en) * | 2021-05-27 | 2022-12-08 | 株式会社デンソー | Semiconductor device |
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1998
- 1998-03-26 JP JP07972998A patent/JP3443313B2/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| JPH11274375A (en) | 1999-10-08 |
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