JP3438342B2 - Pulse phase difference encoding circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse phase difference coding circuit for coding a phase difference between arbitrary two pulses.

[0002]

2. Description of the Related Art Conventionally, as a device of this type, as disclosed in, for example, Japanese Patent Application Laid-Open No. 3-220814, a pulse circulating circuit in which a plurality of inverting circuits are connected in a ring shape is provided. When the first pulse is input to the circuit at an arbitrary timing to circulate, the number of laps is counted, and subsequently the second pulse having an arbitrary phase difference with respect to the first pulse is input, the pulse circulator circuit Of the two pulses by detecting the orbital position of the first pulse in, and detecting the detected orbital position and the number of times of the counted number of turns, that is, how many turns and how many inversion circuits have performed the inversion operation. A device that detects a phase difference is known.

[0003]

However, when the threshold value of the inverting circuit used in the pulse circulation circuit is not 1/2 of the amplitude of the input / output signal, the input of the inverting circuit changes (threshold value). Time from when the value is reached) to when the output changes,
That is, the delay time of the inverting circuit is different when the rising edge of the signal is input and when the falling edge is input.

For example, the input / output signal of the inverting circuit is 0V to 5V.
When the voltage varies between V and the threshold value is 1.5 V, the outputs of three consecutive inversion circuits (k−1 stage, k stage, k + 1 stage) are represented as shown in FIG. 7. It should be noted that each element is integrated into one chip and has uniform characteristics.

As shown in FIG. 7, when the output of the k−1 stage inverting circuit (the input of the k stage inverting circuit) changes from the low level to the high level and reaches the threshold value (1.5 V), The k-th stage output (k + 1-th stage input) starts changing from the high level to the low level. When the output of the kth stage (input of the k + 1th stage) reaches the threshold value, the output of the k + 1th stage becomes Low.
Start changing from level to High level.

When the signal level of the output of each inverting circuit operating in this manner is identified by the same 1.5V as the threshold value of the inverting circuit, the output of each inverting circuit is High / Lo.
Identified as indicated by w. The time DLk from when the input reaches the threshold to when the output reaches the threshold,
DLk + 1 is the delay time of the k-th and k + 1-th inversion circuits, respectively, which are different.

That is, when the rising edge of the signal is input so that the threshold value for capturing the output of the inverting circuit is lowered (when the signal on the input side changes from the low level to the high level), Since the high level is identified earlier and the low level is identified later on the output side, the delay time in the inverting circuit is increased. On the other hand, when the falling edge of the signal is input (when the signal on the input side changes from High level to Low level),
It will be delayed to be recognized as Low level on the input side,
Since it is quickly identified as a high level on the output side, the delay time in the inverting circuit is reduced. As a result, the delay DL of the kth inverting circuit whose input is rising is
k (that is, the phase difference between the output of the (k-1) th inverting circuit and the output of the kth inverting circuit, which is taken in by the orbital position detecting means)
And the delay DLk + 1 of the k + 1-th inverting circuit whose input is falling (that is, the phase difference between the output of the k-th inverting circuit and the output of the k + 1-th inverting circuit taken in by the orbital position detecting means). ) And will be different. The digital data which is the output value of the pulse phase difference coding circuit is coded into a predetermined value corresponding to the period of the delays (phase differences) DLk and DLk + 1.

Therefore, when the pulse phase difference is measured using such a pulse phase difference encoding circuit, it depends on whether the number of stages of the inverting circuit through which the pulse signal has passed is even or odd, that is, the pulse signal. There is a problem that it is not possible to perform accurate measurement because the magnitude of the measurement error of the encoded digital data differs depending on whether the beginning of the is a rising signal or a falling signal. .

In order to solve this, two inverting circuits are used as a set, and the difference in delay time is offset to cancel the threshold value of the inverting circuit even if it is not 1/2 of the amplitude of the input / output signal. Also, there is a method of making the delay time of each output stage constant depending on whether the rising edge or the falling edge of the signal is input and making the error range in each value of the encoded digital data constant. Although it is known, there is a problem that the delay time of each stage increases and the resolution deteriorates.

In order to solve the above problems, the present invention provides
It is an object of the present invention to provide a pulse phase difference encoding circuit having a uniform error range in each value of encoded digital data and having high accuracy.

[0011]

In order to achieve the above object, the present invention according to claim 1 is such that a plurality of inverting circuits for inverting and outputting an input signal are connected in a ring shape and the inverting circuit is provided. One of the circuits is configured as a starting inverting circuit capable of controlling the inverting operation by a first control signal from the outside, and a pulse signal is generated when the inverting operation of the starting inverting circuit is started by the input of the first control signal. A pulse circulation circuit that circulates, a counter that counts the number of circulations of the pulse signal in the pulse circulation circuit and outputs the count result as binary digital data, and an arbitrary position for the first control signal. When a second control signal having a phase difference is input from the outside, the output of each inversion circuit of the pulse circulation circuit is binarized by a predetermined threshold value determined according to the operating voltage and taken in. Circulating position detecting means for detecting the circulating position of the pulse signal in the pulse circulating circuit on the basis of the output of each inversion circuit which has been binarized and to output a binary digital signal corresponding to the circulating position, The binary digital data from the orbital position detecting means is stored in the lower bit,
A pulse having a data output line for outputting a plurality of bits of binary digital data having the binary digital data from the counter as upper bits as data representing a phase difference between the first control signal and the second control signal. In the phase difference encoding circuit, voltage adjusting means for adjusting the operating voltage of the circulating position detecting means is provided, and the threshold value of the circulating position detecting means is adjusted by adjusting the operating voltage by the voltage adjusting means. The output of each of the inverting circuits binarized by the orbiting position detecting means is adjusted so that the phase difference between the outputs of two consecutive inverting circuits is constant.

The invention described in claim 2 is the same as claim 1.
In the pulse phase difference encoding circuit according to, the circulating position detecting means is provided on each input line for capturing the output of each inverting circuit, and a threshold value for identifying the output level of the inverting circuit is set. The voltage adjustment includes at least a buffer circuit that is determined according to an operating voltage, and a voltage drop unit that is connected between the buffer circuit and a power supply and that drops the operating voltage of the buffer circuit according to a predetermined drive signal. The means drives the voltage drop means to adjust the operating voltage of the buffer circuit.

Next, the invention described in claim 3 is the same as claim 1
3. The pulse phase difference encoding circuit according to claim 2, further comprising an input terminal for inputting predetermined control data from the outside, a storage unit for storing the control data input from the input terminal, Switching means for selectively supplying either the control data stored in the storage means or the control data input from the input terminal to the voltage adjusting means, wherein the voltage adjusting means is supplied from the switching means. It is characterized in that the operating voltage is set according to the control data to be set.

[0014]

In the pulse phase difference encoding circuit according to claim 1 configured as described above, the first
When the control signal is input, the inversion circuit for starting the pulse circulation circuit starts the inversion operation, the outputs of the respective inversion circuits constituting the pulse circulation circuit are sequentially inverted, and the pulse signal circulates on the pulse circulation circuit. .

By the way, since the inverting circuit has a delay from the change of the input level of the inverting circuit to the change of the output level thereof, that is, before the pulse signal passes through the inverting circuit, during this delay time. , The output level and the input level (the output level of the previous stage) become the same level. That is,
The position of the inverting circuit having the same output level as that of the inverting circuit in the subsequent stage is the circulating position of the pulse signal.

Then, the counter counts the number of circulations of the pulse signal in the pulse circulation circuit and outputs the count result as binary digital data. Further, when the second control signal having an arbitrary phase difference with respect to the first control signal is input from the outside, the orbital position detecting means outputs the output signal from each inverting circuit at a predetermined threshold value. The signal is binarized and captured, and the circulation position of the pulse signal in the pulse circulation circuit is detected based on the captured signal, and binary digital data corresponding to the circulation position is generated. And
The data output line outputs, as pulse phase difference data, a plurality of bits of digital data in which the binary digital data from the circulating position detecting means is the lower bit and the binary digital data from the counter is the upper bit.

Here, the operating voltage of the orbiting position detecting means is
The operating voltage is adjusted by the voltage adjusting means. By adjusting the operating voltage, the threshold value when the circulating position detecting means takes in the output of each inverting circuit of the pulse circulating circuit is adjusted. Moreover, the threshold value is adjusted so that the phase difference between the outputs of two continuous inverting circuits among the outputs of the inverting circuits that are binarized and taken in is constant.

Note that the phase difference of the output of the inverting circuit here means from the change of the signal level of the input of the inverting circuit (the output of the preceding inverting circuit) to the change of the output signal level according to the change. It is the time difference. That is, when the rising edge of the signal is input as the threshold value for capturing the output of each inverting circuit to the orbiting position detection means is increased (when the signal on the input side changes from the low level to the high level), Since it is delayed that the input side is identified as being at the high level and is quickly identified as the low level at the output side, the delay time in the inverting circuit is reduced. On the contrary, when the falling edge of the signal is input (the signal on the input side
Change from high level to low level), the input side will identify it as low level sooner and the output side will
Since it is delayed to be identified as being at the high level, the delay time of the inverting circuit becomes large. Therefore, by appropriately adjusting the threshold value, it is possible to make the delay of the inverting circuit (that is, the phase difference between the input signal and the output signal of the inverting circuit) constant regardless of how the input signal level changes. As a result, the phase difference between the outputs of two continuous inverting circuits can be made constant.

Specifically, for example, as shown in FIG.
Considering the case where the input / output signal of the inverting circuit changes between 0V and 5V and the threshold value is 1.5V, the output of three consecutive inverting circuits (k−1 stage, k stage, k + 1 stage) is , Which is exactly the same as that described with reference to FIG. 7, but if the threshold value when the orbital position detecting means captures the output of each of these inverting circuits is set to an appropriate value (here, 2V), the signal level becomes Figure 6
, The delay DLk of the inversion circuit of the k-th stage, which is identified as High / Low, and whose input is rising (that is, the output of the inversion circuit of the (k-1) -th stage taken in by the orbital position detecting means, and k
The phase difference from the output of the inverting circuit of the stage) and the delay DLk + 1 of the inverting circuit of the k + 1th stage where the input is falling (that is, the output of the inverting circuit of the kth stage taken in by the circulating position detecting means,
It can be seen that the phase difference with the output of the (k + 1) th inverting circuit is substantially the same.

As described above, according to the pulse phase difference encoding circuit of the first aspect, by adjusting the operating voltage of the revolving position detecting means, the threshold value of the revolving position detecting means can be adjusted. Therefore, by adjusting the threshold value of the circulating position detecting means so that the phase difference between the outputs of the two continuous inverting circuits is constant, the output having the uniform phase difference can be fetched from the pulse circulating circuit. it can. And
The first control signal and the second control signal are generated by using the signals having the same phase difference.
The pulse phase difference from the control signal can be encoded with high accuracy.

Further, since the pulse phase difference can be encoded with high precision, if applied to, for example, a digital PLL phase comparator, various sensors, measuring instruments, etc., highly accurate measurement and control can be performed. Next, in the pulse phase difference encoding circuit according to claim 2, the voltage adjusting means drives the voltage lowering means connected between the buffer circuit and the power supply to adjust the operating voltage of the buffer circuit. . Moreover, since the threshold value of the buffer circuit is set to a predetermined value according to the operating voltage, the threshold value of the buffer circuit is adjusted by adjusting the operating voltage.

Therefore, according to the pulse phase difference encoding circuit of the second aspect, the threshold value of the buffer circuit is adjusted so that the phase difference between the outputs of the two continuous inverting circuits is constant. With this configuration, similarly to the pulse phase difference encoding circuit according to claim 1, it is possible to capture an output with a uniform phase difference from the pulse circulation circuit, and to use the signal with a uniform phase difference as the first control signal. The pulse phase difference with the second control signal can be accurately encoded.

Further, since only the operating voltage of the buffer circuit is changed, it is sufficient to guarantee the operation for a wide operating voltage only for the buffer circuit, and the circuit design and the like can be simplified. Next, in the pulse phase difference encoding circuit according to claim 3, the switching means is set so that the control data externally input through the input terminal is supplied to the voltage adjusting means, When the control data is input, the voltage adjusting means sets the operating voltage of the circulating position detecting means or the buffer circuit according to the control data input from the input terminal.

At this time, if the control data is stored in the storage means, the switching means is switched thereafter, and the control data stored in the storage means is set to be supplied to the voltage adjusting means. The operating voltage is always set to a predetermined value without inputting more control data.

Therefore, according to the present invention, by changing the control data input through the input terminal, the operating voltage of the circulating position detecting means or the buffer circuit is changed, and the operating characteristics of the pulse phase difference encoding circuit are changed. By storing the control data when the measurement is performed and the optimum operation characteristics are obtained in the storage means, the pulse phase difference encoding circuit is always operated in the optimum state without the need for such adjustment. You can

[0026]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 is a schematic configuration diagram showing a pulse phase difference encoding circuit of a first embodiment to which the present invention is applied.

As shown in FIG. 1, the pulse phase difference encoding circuit 2 of this embodiment has one NAND circuit NAND as a inverting circuit for activation which operates by receiving the pulse signal PA at one input terminal. And a large number of inverters IN as inverting circuits
Pulse circulation circuit 10 formed by connecting Vr in a ring shape
Then, the number of times the pulse signal is circulated in the pulse circulator circuit 10 is counted from the number of times the output level of the inverter INVr provided before the NAND circuit NAND in the pulse circulator circuit 10 is inverted to obtain binary digital data. A counter 12 for generating and a latch circuit 14 for latching digital data output from the counter 12 when receiving a pulse signal PB having an arbitrary phase difference with respect to the pulse signal PA,
When the pulse signal PB is received, the output of each inverting circuit (that is, the NAND circuit NAND and the inverter INVr) forming the pulse circulation circuit 10 is taken in, and the pulse signal circulating in the pulse circulation circuit 10 is extracted from the output level. And a pulse selector 16 for generating a signal indicating the position.
And an encoder 18 for generating digital data corresponding to the output signal from the pulse selector 16, and a latch circuit 1.
Digital data from 4 upper bits, encoder 18
The digital data from the lower bit, pulse signal P
A data output line 20 for outputting binary digital data DO representing the phase difference between A and PB to the outside, and a voltage adjusting circuit 22 for adjusting the operating voltage Vs of the pulse selector 16.

Here, the pulse selector 16 outputs the inverter INVs connected to each input line for taking in the output of each inversion circuit constituting the pulse circulation circuit 10 and the output of the inverter INVs at the rising timing of the pulse signal PB. It is composed of a D flip-flop DFF to be latched and a select circuit 24 which detects a position where the same level continues from the output of each D flip-flop DFF and outputs a signal corresponding to the signal on the preceding stage side to the encoder 18. Has been done.

On the other hand, the voltage adjusting circuit 22 for adjusting the operating voltage of the pulse selector 16 has a DA converter 26 for generating a predetermined voltage according to predetermined control data and an input terminal T for fetching the control data CD from the outside. Of the control data CD input from the input terminal T or the control data CDM stored in the memory 28, the memory 28 storing the control data CD input from the input terminal T by pressing a switch (not shown). Either one is D
It is configured by a selection switch 30 which supplies the A converter 26. The DA converter 26 divides the power supply voltage by, for example, resistors connected in series, and changes the voltage by changing the voltage dividing ratio by variously changing the voltage dividing resistors according to the control data CD / CDM. The power supply necessary for driving the pulse selector 16 can be sufficiently supplied.

In the digital data DO output from the data output line 20, the binary digital data output from the counter 12 is represented as upper bits and the binary digital data output from the encoder 18 is represented as lower bits. The logical product circuit NAND is the first stage, and the number of stages of the inverting circuit passed is represented by binary digital data. However, when the pulse circulation circuit 10 is not configured with 2 ⁿ inversion circuits, in order to actually know the number of passage stages of the pulse signal, the inversion circuit that configures the pulse circulation circuit 10 to the value of the upper bit of the digital data DO. It is necessary to perform the operation of adding the value of the lower bit of the digital data DO to the value obtained by multiplying the number of An arithmetic circuit for performing this arithmetic may be added to the data output line 20.

The pulse phase difference encoding circuit 2 configured as described above operates as follows. That is, first, an odd number of inverting circuits (NAND logic circuit NAND and inverter I
As shown in FIG. 2, the pulse circulating circuit 10 composed of NVr) starts the pulse signal circulating operation when the pulse signal PA is at the high level, and rotates the pulse signal while the pulse signal PA is at the high level. The number of laps is
The pulse signal PB is counted by the counter 12, and the pulse signal PB is Hi.
The count result is latched in the latch circuit 14 at the time of reaching the gh level.

On the other hand, when the pulse signal PB becomes high level, the pulse selector 16 takes in the output of each inversion circuit of the pulse circulation circuit 10 and detects the circulation position of the pulse signal in the pulse circulation circuit 10 based on this. Then, the encoder 18 generates digital data corresponding to the circulating position. As a result, binary digital data DO corresponding to the time Tc from the rise of the pulse signal PA to the rise of the pulse signal PB is output from the data output line 20.

By the way, the operating voltage Vs of the pulse selector 16 is set to the digital data DO by the voltage adjusting circuit 22.
The operating voltage Vs is set in the following manner, although the error range in each value of is adjusted to be constant. That is, first, the selection switch 30 of the voltage adjustment circuit 22 is set so that the control data CD from the input terminal T is input to the DA converter 26, and the DA converter 2
6 output voltage (pulse selector 16 operating voltage Vs)
However, the control data CD having the same value as the power supply voltage VDD of the pulse circulation circuit 10 is input from the input terminal T. In this state, the pulse signals PA and PB having a predetermined phase difference are input and the digital data DO appearing on the data output line 20 is measured. Further, the phase difference between the pulse signals PA and PB is gradually changed, and the digital data DO is repeatedly measured. After that, the control data CD is changed to change the output voltage of the DA converter 26, and the same measurement is repeated several times. From the measurement result thus obtained, the operating voltage Vs at which the range of error in each value of the digital data DO is substantially constant is found, and the control data CD at that time is stored in the memory 28.

After that, the operating voltage of the pulse selector 16 is adjusted based on the control data CDM by switching the selection switch 30 so that the control data CDM stored in the memory 28 is set to be input to the DA converter 26. The pulse selector 16 always operates in the optimum state.

Next, FIG. 3 shows the result of actual measurement performed in this way. For the measurement, pulse signals PA, P
For B, a dedicated tester that can continuously output by automatically changing the phase difference by ΔT (62.5 [psec]) is used.

In the graph of FIG. 3, the horizontal axis represents the phase difference between the pulse signals PA and PB, and the displayed numerical value represents a multiple of ΔT. The vertical axis represents the number of stages of the inverting circuit (NAND circuit NAND and inverter INVr) whose outputs are inverted, that is, the value of the digital data DO encoded by the counter 12 and the encoder 18.

FIG. 3A is a graph showing the measurement results when the operating voltage of the pulse selector 16 is set to 5 V, which is the same as that of the pulse circulating circuit 10. As shown in FIG. 3A, the phase difference between the pulse signals PA and PB is 687.5 (Δ
Until T × 11) [psec], the output of the first stage is not inverted and the number of passing stages is 0. After that, the phase difference is 812.5.
Until (ΔT × 13) [psec], the output of the first stage is inverted, but the output of the second stage is not inverted, and the number of passing stages is one. Similarly, the phase difference is 1312.5 (Δ
Until T × 21) [psec], the output up to the second stage is inverted, and the number of passing stages is 2.

The flat partial length in the graph is the magnitude of the delay in each inverting circuit, that is, the phase difference between the input (the output of the preceding stage) and the output of each inverting circuit, and thus each digital data DO. It represents the range of error in the value. Figure 3
As is apparent from the graph of (a), the delay of the inverting circuits in the odd-numbered stages is 437.5 (ΔT × 7) to 56 except for the first stage.
2.5 (ΔT × 9) [psec], and the delay of the even-numbered inverting circuit is 62.5 (ΔT × 1) to 125 (ΔT × 2) [pse
c], and the average value of the delay of each stage is 299.8 [psec],
The standard deviation value is 213.7 [psec]. In this way, there is a very large variation between the odd-numbered stage delay and the even-numbered stage delay.

On the other hand, FIG. 3B shows the pulse selector 16
3 is a graph showing the measurement results when the operating voltage Vs of 1 is set to 4.3V. The delay of each inverting circuit is 250 (ΔT × 4) to 375 (ΔT) except for the first stage.
X6) [psec], and the average value of the delay of each stage is 301 [pse
c] and the standard deviation value is 36.2 [psec]. As described above, by adjusting the operating voltage Vs, the delay in each stage, that is, the phase difference between the outputs of the two continuous inverting circuits is averaged, and the error range in each value of the digital data DO is substantially constant. You can see that it is.

The delay of the inverting circuit of the first stage has the same large value before and after the correction. The delay of the inverting circuits of the stages other than the first stage is such that the output is delayed after the input reaches the threshold value. The time it takes to reach the threshold is measured, whereas the delay in the first stage inverting circuit is because the time it takes for the output to reach the threshold after the input starts rising. is there.

As described above, the pulse phase difference encoding circuit 2 of this embodiment is constructed so that the operating voltage of the pulse selector 16 can be arbitrarily set, and by adjusting this operating voltage. , Pulse selector 16
Outputs the output of each inverting circuit that constitutes the pulse circulation circuit 10 to 2
It is possible to adjust the threshold when digitizing and importing.

Therefore, the threshold value of the inverting circuit forming the pulse circulating circuit 10 deviates from the center of the operating voltage, so that the delay of each inverting circuit forming the pulse circulating circuit 10 and the rising of the signal are input. Even if the case is different from the case where the falling edge is input, the phase difference between the outputs of two consecutive inverting circuits is adjusted by adjusting the threshold value when the pulse selector 16 takes in the output of the inverting circuit. The output of each inverting circuit can be taken in such that each of the digital data DO becomes
The range of error in each value of can be made uniform.
In addition, since the range of error in each value of the digital data DO is uniform in this way, it is possible to perform accurate measurement of the pulse phase difference.

Further, since the control data CD at that time can be stored in the memory 28 once adjusted, the pulse phase difference can always be measured in an optimum state without adjustment thereafter. Next, a pulse phase difference encoding circuit of the second embodiment to which the present invention is applied will be described.

FIG. 4 is a schematic configuration diagram showing the configuration of the pulse phase difference encoding circuit 32 of this embodiment. As shown in FIG. 4, the pulse phase difference encoding circuit 32 of the present embodiment is similar to the pulse phase difference encoding circuit 2 of the first embodiment in that the pulse circulation circuit 10, the counter 12, the latch circuit 14, the pulse selector. 34, an encoder 18, a data output line 20, and a voltage adjusting circuit 22. The configuration other than the pulse selector 34 is the same as that of the first embodiment, and the description thereof is omitted.

The pulse selector 34 is a buffer B provided in place of the inverter INVs of the first embodiment.
UF and D flip-flop D similar to that of the first embodiment
It is composed of an FF and a select circuit 24. In addition,
The pulse selector 34 is driven by the same power supply VDD as the pulse circulation circuit 10 and the like at the same operating voltage, and the output Vs of the voltage adjusting circuit 22 is connected to each buffer BUF.

As shown in FIG. 5, the buffer BUF inverts the output of each inverting circuit of the pulse circulation circuit 10 and outputs the inverted signal to the D flip-flop DFF. It is connected between TR1 and power supply VDD2, and the voltage adjustment circuit 2
Controlled by the output Vs of the two transistors TR1, T
It is composed of a transistor TR3 for adjusting the operating voltage of the inverter composed of R2.

Since the transistor TR3 generates a predetermined voltage VDS between the drain and the source according to the output Vs of the voltage adjusting circuit 22, the transistors TR1 and T1.
The operating voltage of the inverter composed of R2 is lowered by the voltage VDS from the power supply voltage VDD2. As a result, the threshold value of the inverter that changes depending on the operating voltage can be adjusted by the output Vs of the voltage adjusting circuit 22.

Therefore, according to the pulse phase difference encoding circuit 32 of the present embodiment, the pulse selector 34 continuously outputs the outputs of the respective inversion circuits constituting the pulse circulation circuit 10 as in the case of the first embodiment. The phase difference between the outputs of the two inverting circuits can be taken to be substantially the same, and the range of the error in each value of the digital data DO that encodes the pulse phase difference can be made uniform. it can.

In the structure of this embodiment, the operating voltage of the inverter composed of the transistors TR1 and TR2 can only be set lower than the power supply voltage VDD, so that the threshold value becomes lower than the value determined by the power supply voltage VDD. Buffer BUF.
If the power supply voltage is set to be higher than the power supply voltage VDD of the pulse circulation circuit 10, the threshold value of the buffer BUF can be adjusted to a value higher than that at the time of operating at the power supply voltage VDD.

Further, in the first embodiment, the pulse selector 1
Although it is necessary to guarantee the operation of the entire 6 within the range in which the operating voltage can fluctuate, in this embodiment, only the buffer BUF needs to be guaranteed for a wide operating voltage, and the circuit design and the like can be simplified. . Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments and can be implemented in various modes without departing from the scope of the present invention.

For example, in the above embodiment, the control data CD
Memory is used to store the data, but control data CD can be manually set using the DIP switch, or D
A fuse may be connected to the input terminal of the A converter so that when a specific control data is input, the predetermined fuse is blown to fix the signal level of the input terminal to a predetermined state.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a configuration of a pulse phase difference encoding circuit 2 of a first embodiment.

FIG. 2 is a time chart showing the operation of the pulse phase difference encoding circuit 2 in the first embodiment.

FIG. 3 is a graph showing measurement results when pulse signals PA and PB are changed.

FIG. 4 is a schematic configuration diagram showing a configuration of a pulse phase difference encoding circuit 32 of a second embodiment.

5 is a circuit diagram showing a detailed configuration of a buffer BUF of the pulse selector 34. FIG.

FIG. 6 is an explanatory diagram showing that delay is adjusted by changing a threshold value.

FIG. 7 is an explanatory diagram showing an operation of a conventional device.

[Explanation of symbols]

2, 32 ... Pulse phase difference encoding circuit 10 ... Pulse circulation circuit 12 ... Counter 14 ... Latch circuit 16, 34 ...
Pulse selector 18 ... Encoder 20 ... Data output line 22
... voltage adjusting circuit 24 ... select circuit 26 ... DA converter 28
... Memory 30 ... Selection switch

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-220814 (JP, A) JP-A-3-125514 (JP, A) JP-A-4-232477 (JP, A) JP-A-6- 11527 (JP, A) JP-A-6-51003 (JP, A) JP-A-61-227422 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 25/00 H03K 5 /twenty two

Claims (3)

(57) [Claims] 1. An inverting circuit for inverting an input signal and outputting the inverted signal, wherein a plurality of inverting circuits are connected in a ring shape, and one of the inverting circuits can control the inverting operation by a first control signal from the outside. A circuit, which is a circuit for circulating a pulse signal in response to the start of the inverting operation of the startup inverting circuit by the input of the first control signal, and counts the number of revolutions of the pulse signal in the pulse circuit. A counter for outputting the count result as binary digital data, and a second counter having an arbitrary phase difference with respect to the first control signal.
When the control signal of is input from the outside, the output of each inversion circuit of the pulse circulation circuit is binarized by a predetermined threshold value determined according to the operating voltage, and each inversion is obtained by binarization. Circular position detection means for detecting the circular position of the pulse signal in the pulse circulation circuit based on the output of the circuit and outputting a binary digital signal according to the circular position, and a binary number from the circular position detection means A data output line for outputting digital data of a plurality of bits having digital data as lower bits and binary digital data from the counter as upper bits as data representing a phase difference between the first control signal and the second control signal. And a voltage adjusting means for adjusting the operating voltage of the orbiting position detecting means is provided in the pulse phase difference encoding circuit. With respect to the threshold value of the stage, among the outputs of the respective inverting circuits binarized and taken in by the circulating position detecting means by adjusting the operating voltage by the voltage adjusting means, the outputs of two consecutive inverting circuits are provided. The pulse phase difference encoding circuit is characterized in that the phase difference between the pulse phase difference encoding circuits is adjusted to be constant. 2. The circulating position detecting means is provided on each input line for taking in the output of each inverting circuit, and the threshold value for identifying the output level of the inverting circuit is determined according to the operating voltage. A buffer circuit; and a voltage drop unit that is connected between the buffer circuit and the power supply and drops the operating voltage of the buffer circuit according to a predetermined drive signal. 2. The pulse phase difference encoding circuit according to claim 1, further comprising driving means for adjusting an operating voltage of the buffer circuit. 3. The pulse phase difference encoding circuit according to claim 1, further comprising an input terminal for inputting predetermined control data from the outside, and the control data input from the input terminal. And a switching means for selectively supplying either the control data stored in the storage means or the control data input from the input terminal to the voltage adjusting means. A means for setting the operating voltage according to the control data supplied from the switching means, the pulse phase difference encoding circuit.