JPH07198762A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To exactly evaluate the voltage detected by means of a low-voltage detecting circuit in a short time. CONSTITUTION:A semiconductor integrated circuit device is provided with an internal circuit 1, low-voltage detecting circuit 2, and A/D conversion circuit 3. The detecting circuit 2 inputs the power supply voltage Vcc supplied to the internal circuit 1. The detecting circuit 2 compares the voltage Vcc with a prefixed detecting voltage VDL and changes the level of a resetting signal RES based on the compared result. The A/D conversion circuit 3 inputs the voltage Vcc and converts the voltage Vcc into a digital value. Then the voltage Vcc is gradually dropped so that the conversion by the conversion circuit 3 can be performed based on the level of the resetting signal RES outputted from the detecting circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a low voltage detection circuit for detecting a decrease in power supply voltage and outputting a reset signal based on the detection result.

In recent years, semiconductor integrated circuit devices have been widely used for controlling various electronic devices. Since the semiconductor integrated circuit device may malfunction when the power supply voltage decreases, a low voltage detection circuit for detecting the decrease in the power supply voltage is provided. The low voltage detection circuit compares the power supply voltage with the detection voltage, detects a decrease in the power supply voltage based on the comparison result, and outputs a reset signal to prevent malfunction of the semiconductor integrated circuit device. Therefore, it is required to accurately detect the detection voltage at which the low voltage detection circuit outputs the reset signal in a short time.

[0003]

2. Description of the Related Art FIG. 7 is a partial block circuit diagram showing a conventional semiconductor integrated circuit device. The semiconductor integrated circuit device 50 is provided with an internal circuit 51. The internal circuit 51 is provided with a circuit such as a memory. The internal circuit 5
A power supply voltage Vcc is supplied to 1 and it operates by the power supply voltage Vcc. However, if the power supply voltage Vcc drops for some reason, the internal circuit 51 will not operate normally.

Therefore, some semiconductor integrated circuit devices 50 are provided with a low voltage detection circuit 52. A power supply voltage Vcc is applied to the low voltage detection circuit 52, the voltage of the power supply voltage Vcc is detected, and H level or L is detected based on the detection result.
The reset signal bar RES that becomes the level is output to the internal circuit 51.

That is, the detection voltage VDL at which the internal circuit 51 can operate is preset in the low voltage detection circuit 52 at the design stage. The low voltage detection circuit 52 constantly compares the set power supply voltage Vcc with the detection voltage VDL. Then, as shown in FIG. 6, the power supply voltage Vcc is equal to the detection voltage VD.
When the voltage drops below L, the low voltage detection circuit 52 outputs the H level reset signal bar RES to the internal circuit 51. When the internal circuit 51 receives the H-level reset signal bar RES, the internal circuit 51 suspends its operation and returns to the initial state.

When the power supply voltage Vcc rises again to become higher than a predetermined detection voltage VDH (a voltage higher than the detection voltage VDL and lower than the power supply voltage Vcc), the low voltage detection circuit 52 resets the L level reset signal. Is output. Then, the internal circuit 51 starts to operate from the initial state to prevent malfunction due to a decrease in the power supply voltage Vcc.

[0007]

By the way, it is inspected before shipment whether or not the detection voltage VDL set in the low voltage detection circuit 52 is within the rated range. As this inspection method,
The power supply voltage Vcc is set to an arbitrary voltage, and the reset signal bar RES at that time is inspected depending on whether it is at the H level or the L level. That is, the power supply voltage Vcc is sequentially decreased, and the power supply voltage Vcc applied when the state of the reset signal bar RES changes from the L level to the H level at each time is detected as the detection voltage VDL. for that reason,
The power supply voltage Vcc must be repeatedly changed a plurality of times before the detection voltage VDL is detected, and there is a problem that the inspection is troublesome.

Further, in order to detect the detection voltage VDL accurately, the power supply voltage Vcc must be gradually decreased, so that there is a problem that the inspection takes time. The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor integrated circuit device capable of accurately evaluating a detection voltage of a low voltage detection circuit in a short time. .

[0009]

FIG. 1 is a diagram for explaining the principle of the present invention. The semiconductor integrated circuit device includes an internal circuit 1, a low voltage detection circuit 2 and an A / D conversion circuit 3. The low voltage detection circuit 2 inputs the power supply voltage Vcc supplied to the internal circuit 1. Then, the low voltage detection circuit 2 receives the power supply voltage Vcc.
And a predetermined detection voltage VDL are compared, and a reset signal RES is output based on the comparison result.

The A / D conversion circuit 3 receives the power supply voltage Vcc and converts the power supply voltage Vcc from analog to digital. Then, the power supply voltage Vcc is gradually decreased, and conversion of the A / D conversion circuit 3 is performed based on the level of the reset signal bar RES output from the low voltage detection circuit 2.

[0011]

Therefore, according to the present invention, the A / D conversion circuit 3 for converting the power supply voltage Vcc from analog to digital is converted by the reset signal RES. As a result, the reset signal bar RE output by the low voltage detection circuit 2 is output.
The power supply voltage when the S level is switched, that is, the detection voltage can be detected easily and accurately, and the inspection time can be shortened.

[0012]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 2 is a partial block circuit diagram showing a semiconductor integrated circuit device. The semiconductor integrated circuit device 10 includes a low voltage detection circuit 11, a selection circuit 12, and an A / D converter 13.
And a CPU 14 are provided.

An external terminal 15 is connected to the input terminal of the low voltage detection circuit 11. A test device (not shown) is connected to the external terminal 15. The test device is connected to test the low voltage detection circuit and can output an arbitrary voltage depending on the setting.

In this embodiment, the test device can output any voltage between 5 V and 0 V. Further, the test apparatus can gradually reduce the output voltage and applies the output voltage as the test voltage VT to the low voltage detection circuit 11 via the external terminal 15. Further, in normal use, the external terminal 15 is connected to the high-potential side power supply Vcc, and the power supply voltage Vcc is applied to the low voltage detection circuit 11 via the external terminal 15.

The output terminal of the low voltage detection circuit 11 is connected to the selection circuit 12. The detection voltage VDL is preset in the low voltage detection circuit 11. The low voltage detection circuit 11 receives the test voltage VT, and outputs the test voltage VT and the detection voltage V
Compare with DL. Based on the comparison result, the low voltage detection circuit 11 changes the level of the reset signal bar RES and outputs it. That is, when the test voltage VT is higher than the detection voltage VDL, the low voltage detection circuit 11 outputs L
The level reset signal bar RES is output to the selection circuit 12. On the other hand, when the test voltage VT is equal to or lower than the detection voltage VDL, the low voltage detection circuit 11 outputs the H level reset signal RES to the selection circuit 12 as shown in FIG.

In normal use, the low voltage detection circuit 11 inputs the power supply voltage Vcc and compares the power supply voltage Vcc with the detection voltage VDL. Then, the low voltage detection circuit 11
Outputs a reset signal bar RES at L level when the power supply voltage Vcc is higher than the detection voltage VDL,
When is lower than the detection voltage VDL, an H level reset signal RES is output.

The selection circuit 12 is provided with two input terminals, one of which has the reset signal bar RES.
The external input terminal 16 is connected to the other input terminal, and the conversion start signal ADST is input via the external terminal 16. The selection circuit 12 is provided with two output terminals, one output terminal is connected to the reset terminal RST of the CPU 14, and the other output terminal is connected to the external start input EXT of the A / D converter 13.

The selection circuit 12 is also connected to the output terminal 17 of the CPU 14. The selection circuit 12 receives the switching signal C0 output from the CPU 14, and switches and connects the input terminal and the output terminal based on the switching signal C0. That is, when the switching signal C0 is "0", the selection circuit 1
2 inputs the reset signal bar RES to the reset terminal RST of the CPU 14 and inputs the conversion start signal ADST to the external start input EXT of the A / D converter 13. On the other hand, when the switching signal C0 is "1", the selection circuit 12 inputs the reset signal bar RES to the external start input EXT of the A / D converter 13.

The A / D converter 13 is provided with eight input channels AN0 to AN7. Input channel A
The external terminal 15 is connected to N0, and the test voltage VT
Enter. Sensors such as a temperature sensor and a weight sensor are connected to the other input channels AN1 to AN7 to input a voltage according to temperature and weight.

The A / D converter 13 has a CPU 1
4 is connected. A / D converter 13 is CPU1
When the select signal S0 is input from 4, one of the eight input channels AN0 to AN7 is selected based on the select signal S0. The A / D converter 13 is a conversion start signal ADS input to the internal start or external start input EXT.
The A / D conversion is started based on the rising edge of T, and the voltage input from the selected input channel is converted into digital data having a predetermined number of bits. Then, the A / D converter 13 stores the converted digital data in an internal latch circuit (not shown).

The CPU 14 has a read-only memory (R
An OM) 18 and a random access memory (RAM) 19 are built in. The ROM 18 includes an operation program for operating the semiconductor integrated circuit device 10 and the low voltage detection circuit 1
An inspection program for performing inspection 1 is stored. R
The calculation result of the CPU 14 is temporarily stored in the AM 19 based on both programs.

An inspection start signal ST is input to the CPU 14, and the CPU 14 receives the inspection start signal ST based on the inspection start signal ST.
For example, when the inspection start signal ST is "0", the operation program is executed, and when it is "1", the inspection program is executed. Then, in the inspection program, the CPU 14 outputs a select signal S0 to output A /
The input channel AN0 of the D converter 13 is selected. Further, in the inspection program, the CPU 14 causes the switching signal C0
Is output to control the switching of the selection circuit 12, and the reset signal bar RES output from the low voltage detection circuit 11 is input to the external start input EXT of the A / D converter 13. Therefore, the A / D converter 13 activates the A / D conversion at the rising edge of the reset signal RES, and the test voltage VT input to the input channel AN0
/ D conversion.

Next, the operation of the semiconductor integrated circuit device configured as described above will be described. First, the test apparatus is set so that the test voltage VT becomes 5 V, and the test voltage VT is supplied to the low voltage detection circuit 11 and A / A via the input terminal 15.
It is applied to the D converter 13. Then, the inspection start signal ST is set to "1" and input to the CPU 14.

When the inspection start signal ST of "1" is input, the CPU 14 reads the inspection program stored in the ROM 18 and inspects the low voltage detection circuit 11. That is, C
The PU 14 outputs the select signal S0 to the A / D converter 13, selects the input channel AN0 and inputs the power supply voltage Vcc to the A / D converter 13. Further, the CPU 14 outputs the selection signal C0 to the selection circuit 12, and inputs the reset signal bar RES output from the low voltage detection circuit 11 to the external start input EXT of the A / D converter 13.

Next, the test device is controlled and the test voltage V
Gradually reduce T from 5 volts. At this time, the low voltage detection circuit 11 receives the input test voltage VT and detection voltage VD.
Compare with L. Then, the test voltage VT is the detection voltage V
When it becomes equal to or lower than DL, as shown in FIG.
1 outputs a reset signal RES from L level to H level.

When the reset signal RES becomes H level, the A / D converter 13 starts A / D conversion and converts the test voltage VT input at that time. And A /
The D converter 13 latches the converted data. CP
After the conversion, U14 inputs the digital data Di latched in the A / D converter 13 and stores it in the RAM 19.

This digital data Di corresponds to the actual detection voltage VDL in which the reset signal RES is changed from the L level to the H level by the test voltage VT input to the low voltage detection circuit 11. Therefore, the actual detection voltage VDL of the low voltage detection circuit 11 can be known by reading this digital data Di from the RAM 19.

As described above, in this embodiment, the A / D converter 13 is provided, and the test voltage VT input to the low voltage detection circuit 11 is input to the input channel AN0 thereof. on the other hand,
Reset signal bar R output from the low voltage detection circuit 11
ES is input to the external activation input EXT of the A / D converter 13 via the selection circuit 12. And the test voltage VT
Is gradually decreased, and the A / D conversion is activated by the rise of the reset signal bar RES.

As a result, it is possible to detect the rising edge of the reset signal RES, that is, the test voltage VT when the low voltage detecting circuit 11 detects the drop of the test voltage VT. Therefore, the number of times of detection is only one, and the inspection can be easily performed. In addition, the actual detection voltage VD
The digital data Di obtained by digitizing L is the RAM 1
Since it is stored in 9, the inspection can be performed accurately.
Moreover, since the inspection can be performed by only lowering the test voltage VT once, the inspection time can be shortened.

In addition, the inspection result is used for normal operation A /
The D converter 13 was used. Therefore, the size of the semiconductor integrated circuit device can be reduced by the amount that the A / D converter only for inspection is not used. (Second Embodiment) A second embodiment of the present invention will be described below with reference to FIG.

FIG. 4 is a block circuit diagram showing a semiconductor integrated circuit device. The semiconductor integrated circuit device 20 is provided with a low voltage detection circuit 21, an A / D converter 22 and a CPU 23.

The low voltage detection circuit 21 has input terminals 31, 3
2, output terminals 33 to 35, voltage dividing resistor 36, constant voltage source 37
And a comparator 38 are provided. The input terminal 31 of the low voltage detection circuit 21 is connected to the high potential side power source Vcc,
The input terminal 32 is connected to the low-potential-side power supply Vss (which has a low voltage with respect to the high-potential-side power supply Vcc and is the ground in this embodiment).

A voltage dividing resistor 36 is provided between the input terminals 31 and 32.
Are connected. The voltage dividing resistor 36 is a resistor R1 and a resistor R2.
It is composed of and. The resistors R1 and R2 are formed to have a predetermined resistance value, and the high potential side power source Vcc and the low potential side power source V
The voltage between ss (power supply voltage Vcc in this embodiment) is divided. Therefore, the voltage of the node A fluctuates according to the fluctuation of the power supply voltage Vcc. Then, the voltage of the node A is input to the inverting input terminal of the comparator 38.

A constant voltage source 37 is connected to the non-inverting input terminal of the comparator 38. The constant voltage source 37 is preset so that the voltage of the node B between the comparator 38 and the constant voltage source 37 becomes the detection voltage VDL, and the constant detection voltage VDL is output even if the power supply voltage Vcc changes. Has become.

Further, the comparator 38 has an output terminal 33.
Are connected. Then, the comparator 38 compares the voltage of the node A obtained by dividing the input power supply voltage Vcc with the detection voltage VDL of the node B. And the comparator 3
Reference numeral 8 denotes an L level reset signal bar RES when the voltage of the node A is higher than the detection voltage VDL of the node B, and an H level reset signal bar RES when the voltage of the node A is lower than the detection voltage VDL of the node B. Is output.

The output terminal 34 is connected to the node A, and the output terminal 35 is connected to the node B. Both output terminals 34 and 35 are connected to the A / D converter 22.
The A / D converter 22 has a plurality of analog input terminals (two inputs in this embodiment) AN1 and AN2, and a digital output terminal D _OUT . The analog input terminal AN1 is connected to the output terminal 34 of the low voltage detection circuit 21, and the output terminal 3
The voltage of the node A is input via 4. The analog input terminal AN2 is connected to the output terminal 35 of the low voltage detection circuit 21, and the detection voltage V of the node B is output via the output terminal 35.
It is designed to input DL.

The digital output terminal D _OUT of the A / D converter 22 is connected to the CPU 23, and the A / D converted digital data Di is read by the CPU 23. Further, the A / D converter 22 is adapted to receive the input switching signal C0 from the CPU 23. Then, the A / D converter 22 selects either one of the analog input terminals AN1 and AN2 based on the input switching signal C0, and performs analog-digital conversion on the signals input to the selected analog input terminals AN1 and AN2.

That is, when the input switching signal C0 is L level, the input channel is switched to the analog input terminal AN1, and when the input switching signal C0 is H level, the input channel is switched to the analog input terminal AN2. Then, the converted data is stored in an internal latch circuit (not shown), and the CPU is connected via the digital output terminal D _OUT.
The digital data Di converted by 23 is read out.

Therefore, the CPU 23 uses the A / D converter 2
The divided voltage of the node A of the low voltage detection circuit 21 and the detection voltage VDL of the node B of the low voltage detection circuit 21 can be inputted via the digital data Di, respectively.

Further, the CPU 23 is adapted to input the inspection start signal ST. CPU 23 causes inspection start signal S
When T is input, the input switching signal C0 is output to switch the analog input terminals AN1 and AN2 of the A / D converter 22, and the A / D-converted divided voltage of the node A and the detection voltage VDL of the node B are input. To do.

Then, the CPU 23 compares the input divided voltage of the node A with the detected voltage VDL of the node B. That is, the divided voltage of the node A is a voltage obtained by dividing the power supply voltage Vcc. When the power supply voltage Vcc is set to 5 V and applied to the low voltage detection circuit 21, a voltage corresponding to the power supply voltage Vcc,
That is, the ratio between the resistance R1 and the resistance R2 of the voltage dividing resistor 36 can be obtained. Therefore, the output of the comparator 38 is L
The voltage that changes to the level, that is, the power supply voltage V when the divided voltage of the node A becomes equal to the detection voltage VDL of the node B
cc can be obtained in reverse. Then, the obtained voltage becomes the actual detection voltage VDL of the low voltage detection circuit 21.

Then, the CPU 23 stores the comparison result in the built-in random access memory (RAM) 39. Next, the operation of the semiconductor integrated circuit device configured as described above will be described.

When the inspection start signal ST is input, the CPU 23 sets the input switching signal C0 to L level and outputs it to the A / D converter 22, and switches the input channel of the A / D converter 22 to the analog input terminal AN1. At this time, the power supply voltage Vcc is set to 5 volts.

Then, the A / D converter 22 outputs the node A
The divided voltage is input through the analog input terminal AN1 and A / D converted. Then, the A / D converter 22 latches the converted data and outputs it to the CPU 23. When the CPU 23 inputs the converted data, the RAM
Store in 39.

Next, the CPU 23 sets the input switching signal C0 to H level.
The level is output to the A / D converter 22, and the input channel of the A / D converter 22 is set to the analog input terminal AN2.
Switch to. Then, the A / D converter 22 inputs the detection voltage VDL via the analog input terminal AN2 to input A
/ D conversion. Then, the A / D converter 22 latches the converted data and outputs it to the CPU 23. When the CPU 23 inputs the converted data, the RAM
Store in 39.

Next, the CPU 23 calculates the ratio between the resistance R1 and the resistance R2 of the voltage dividing resistor 36 based on the divided voltage of the node A. Next, the CPU 23 calculates the power supply voltage Vcc when the reset signal bar RES, which is the output of the comparator 38, changes to the H level based on the calculated ratio of the resistors R1 and R2 and the detected voltage VDL. Power supply voltage Vcc of this calculation result
Becomes the detection voltage VDL of the power supply voltage Vcc actually detected by the low voltage detection circuit 21.

As described above, in this embodiment, the power supply voltage V compared by the comparator 38 of the low voltage detection circuit 21.
The divided voltage of the node A obtained by dividing cc and the detection voltage VDL of the node B are input to the A / D converter 22 via the output terminals 34 and 35, and A / D converted. Then, the ratio between the resistors R1 and R2 of the voltage dividing resistor 36 is obtained from the A / D converted data. Based on the obtained ratio of the resistors R1 and R2 and the detection voltage VDL, the power supply voltage Vcc when the reset signal bar RES changes to the H level, that is, the detection voltage VDL actually detected by the low voltage detection circuit 21 You can ask. As a result, the detection voltage VDL can be inspected without actually operating the low voltage detection circuit 21 by changing the power supply voltage Vcc, so that the number of detection times is one and the inspection can be performed easily.

Further, since the divided voltage of the node A and the detection voltage VDL of the node B are stored in the RAM 39 by the CPU 23, it is not necessary to repeat the A / D conversion, and the inspection time can be shortened. (Third Embodiment) A third embodiment of the present invention will be described below with reference to FIG.

FIG. 5 is a block circuit diagram showing a semiconductor integrated circuit device. The semiconductor integrated circuit device 40 includes a low voltage detection circuit 41, a D / A converter 42, and a CPU 43. A transmission gate 44 is connected to the low voltage detection circuit 41, and the power supply voltage Vcc is input via the transmission gate 44. Then, the low voltage detection circuit 41 detects a decrease in the power supply voltage Vcc and outputs a reset signal RES based on the detection result.

The output terminal of the low voltage detection circuit 41 is connected to the reset terminal RST of the CPU 43 via the switching circuit 45 and also to the interrupt terminal INT. C
The PU 43 switches the reset signal bar RES by the switching circuit 45.
Is input to either the reset terminal RST or the interrupt terminal INT.

The inspection start signal ST is input to the CPU 43. The CPU 43 has a ROM 46 and an R as storage devices.
AM47 is built in. In addition, D /
The A converter 42 is connected. The ROM 46 stores an operation program of the CPU 43 that controls the semiconductor integrated circuit device 40 and an inspection program that inspects the low voltage detection circuit 41. Normally, the CPU 43 inputs the power supply voltage Vcc and operates based on the operation program stored in the ROM 46. On the other hand, when the inspection start signal ST is input, the CPU 43 outputs the digital data Do to the D / A converter 42 based on the inspection program stored in the ROM 46.

The output terminal of the D / A converter 42 is connected to the input of the low voltage detection circuit 41 via the transmission gate 48. The D / A converter 42 receives digital data Do of a predetermined number of bits, and outputs an analog output A _OUT (for example, 0 to 5 volts) based on the digital data Do to the low voltage detection circuit 41. There is. That is, the low voltage detection circuit 41 inputs the power supply voltage Vcc via the transmission gate 44 and the analog output A _OUT of the D / A converter 42 via the transmission gate 48.

The transmission gates 44 and 48 are controlled to be turned on and off by the CPU 43. That is, the switching signal C1 output from the CPU 43 is input to the gate terminal of the N-channel MOS transistor forming the transmission gate 44, and P
The switching signal C1 is input to the gate terminal of the channel MOS transistor via the inverter circuit 49. on the other hand,
N channel M that constitutes the transmission gate 48
An inverter circuit 49 is provided at the gate terminal of the OS transistor.
The switching signal C1 is input via the switch, and the switching signal C1 is directly input to the gate terminal of the P-channel MOS transistor. The switching signal C1 of the CPU 43 is input to the switching circuit 45.

The switching signal C1 is the inspection start signal ST described above.
Is output based on. That is, in normal operation, the CPU
43 outputs the switching signal C1 and sets the switching circuit 45 so that the reset signal bar RES of the low voltage detection circuit 41 is input to the reset terminal RST. Further, the CPU 43 sets the transmission gates 44 and 48 so that the power supply voltage Vcc is input to the low voltage detection circuit 41 and the analog output of the D / A converter 42 is not input. At this time, the low voltage detection circuit 41 detects the power supply voltage Vcc and the detection voltage VD.
L is compared and the reset signal bar RES is output based on the comparison result.

On the other hand, when the inspection is started, the CPU 43 outputs the switching signal C1 and sets the switching circuit 45 to input the reset signal bar RES of the low voltage detection circuit 41 to the interrupt terminal INT. Further, the CPU 43 causes the low voltage detection circuit 41 to output the analog output A _OUT of the D / A converter 42.
Is input, and the transmission gates 44 and 48 are set so that the power supply voltage Vcc is not input. At this time,
The low voltage detection circuit 41 has an analog output A _OUT and a detection voltage V
DL is compared, and the reset signal bar RES is output based on the comparison result.

That is, in the normal operation, the low voltage detection circuit 41
Inputs the power supply voltage Vcc to its input terminal and outputs the reset signal bar RES to the reset terminal RST of the CPU 43 based on the power supply voltage Vcc. On the other hand, in the inspection operation,
The low voltage detection circuit 41 inputs the analog output A _OUT of the D / A converter 42 to its input terminal and outputs the reset signal bar RES to the interrupt terminal INT of the CPU 43 based on the analog output A _OUT . .
Next, the operation of the semiconductor integrated circuit device configured as described above will be described.

In the normal operation, the CPU 43 outputs the switching signal C1 to control the ON / OFF of the transmission gates 44 and 48, and the low voltage detection circuit 41 is supplied with the power supply voltage Vcc.
To enter. Further, the CPU 43 controls the selection circuit 12 and inputs the reset signal bar RES output from the low voltage detection circuit 41 to the reset terminal RST.

The low voltage detection circuit 41 monitors the power supply voltage Vcc. Then, the low voltage detection circuit 41 detects the power supply voltage V
When it is detected that cc is lower than the detection voltage VDL, the H level reset signal bar RES is output. CPU43
When an H-level reset signal bar RES is input from the reset terminal RST, the operation is interrupted and initialized.

On the other hand, when the CPU 43 receives the inspection start signal ST, it outputs the switching signal C1 to control the on / off of the transmission gates 44 and 48, and the analog output from the D / A converter 42 to the low voltage detection circuit 41. _Apply output A _OUT . Further, the CPU 43 uses the selection circuit 1
2 to control the reset signal bar R of the low voltage detection circuit 41.
ES is input to the interrupt terminal INT.

Next, the CPU 43 outputs the digital data Do based on the inspection program stored in the ROM 46.
The voltage of the analog output A _OUT that is output to the / A converter 42 is gradually decreased from 5 volts. Low voltage detection circuit 41
Compares the voltage of the analog output A _OUT with the detection voltage VDL. Then, the voltage of the analog output A _OUT is the detection voltage V
When it becomes lower than DL, the low voltage detection circuit 41 outputs the reset signal bar RES at H level.

When the CPU 43 receives the H-level reset signal bar RES from the interrupt terminal INT, the digital data Do output to the D / A converter 42 immediately before the reset signal bar RES is input is stored in the RAM 47, and the inspection is completed. To do. The digital data Do stored in the RAM 47 corresponds to the detection voltage VDL when the low voltage detection circuit 41 actually changes the level of the reset signal bar RES. Therefore, the inspection start signal ST is changed to C
By inputting it to the PU 43 and reading the digital data Do stored in the RAM 47, the low voltage detection circuit 41
It is possible to detect the actual detection voltage VDL.

As described above, in this embodiment, the D / A converter 42 is connected to the input terminal of the low voltage detection circuit 41, and the analog output A _OUT of the D / A converter 42 is input by switching to the power supply voltage Vcc. The CPU 43 outputs the digital data Do to the D / A converter 42 to gradually decrease the voltage of the analog output A _OUT from 5 volts. The low voltage detection circuit 41 changes the level of the reset signal bar RES based on the analog output A _OUT . When the reset signal bar RES goes high, the CPU 43
Output the digital data Do from the actual detection voltage VD
The data corresponding to L is stored in the RAM 47.

As a result, the actual detection voltage VDL of the low voltage detection circuit 41 can be detected without changing the power supply voltage Vcc, so that the inspection can be easily performed.
Further, since the analog output A _OUT of the D / A converter 42 is gradually decreased and the digital data Do when the reset signal bar RES changes to the H level is stored, the actual detection voltage VDL can be accurately detected. it can.

The present invention may be embodied in the following modes in addition to the above embodiments. (1) In the first embodiment, an A / D converter having an input other than the 8-channel A / D converter 13, for example, an A / D converter of 1 channel or the like is used.

Further, the 8-channel A / D converter 13
Instead of 8 channels, a multiplexer of 8 channels and an A / D converter of 1 channel are combined. (2) In the third embodiment, an A / D converter incorporating a D / A converter is provided instead of the D / A converter 42, and the low voltage detection circuit 4 is utilized by using the D / A converter.
The detection voltage VDL of 1 is detected.

(3) ROM or R in each of the above embodiments
The AM is executed by the CPU connected to the outside.

[0068]

As described in detail above, according to the present invention,
There is an excellent effect that the detection voltage of the low voltage detection circuit can be evaluated accurately in a short time.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block circuit diagram illustrating a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 3 is a timing chart explaining the operation of the first embodiment.

FIG. 4 is a block circuit diagram illustrating a semiconductor integrated circuit device of a second embodiment.

FIG. 5 is a block circuit diagram illustrating a semiconductor integrated circuit device of a third embodiment.

FIG. 6 is a waveform diagram illustrating the operation of the low voltage detection circuit.

FIG. 7 is a block circuit diagram illustrating a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1 Internal circuit 2 Low voltage detection circuit 3 A / D conversion circuit Vcc power supply voltage VDL detection voltage bar RES reset signal

Claims (3)

[Claims] 1. A power supply voltage (Vcc) supplied to an internal circuit (1) is input, the power supply voltage (Vcc) is compared with a predetermined detection voltage (VDL), and reset based on the comparison result. In a semiconductor integrated circuit device having a low voltage detection circuit (2) that outputs a signal (RES), the power supply voltage (Vcc) is input, the power supply voltage (Vcc) is analog-digital converted, and the conversion result is obtained. An A / D conversion circuit (3) for storing (Di) is provided, which gradually reduces the power supply voltage (Vcc) and responds to the reset signal (RES) from the low voltage detection circuit (2) at that time. A semiconductor integrated circuit device characterized in that the conversion operation of the A / D conversion circuit (3) is performed. 2. A power supply voltage (Vcc) supplied to the internal circuit (1) is input, the power supply voltage (Vcc) is compared with a predetermined detection voltage (VDL), and reset based on the comparison result. In a semiconductor integrated circuit device including a low voltage detection circuit (2) that outputs a signal (RES), the low voltage detection circuit (2) outputs a divided voltage obtained by dividing the power supply voltage (Vcc). A voltage dividing resistor (36) and a constant voltage source (37) that outputs the detection voltage (VDL).
And a voltage output from the voltage dividing resistor (36) with a detection voltage (VDL) output from the constant voltage source (37), and based on the comparison result, the reset signal (bar RES) is generated. A comparator (38) for outputting the divided voltage of the voltage dividing resistor (36) and the constant voltage source (3
A semiconductor integrated circuit device comprising an A / D conversion circuit (22) for inputting the detection voltage (VDL) of 7) and switching between both voltages to perform A / D conversion. 3. A power supply voltage (Vcc) supplied to the internal circuit (1) is input, the power supply voltage (Vcc) is compared with a predetermined detection voltage (VDL), and reset based on the comparison result. In a semiconductor integrated circuit device including a low voltage detection circuit (2) that outputs a signal (RES), the power supply voltage (Vc is supplied to the low voltage detection circuit (2).
and a D / A conversion circuit (42) for switching the input data (Do) from digital to analog and outputting the converted voltage to the low voltage detection circuit (2). Integrated circuit device.