JP3438225B2 - Transmitter / receiver circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial bus which can be connected to a personal computer, its peripheral equipment, and Audio / Visual equipment.
andard for a High Performance Serial Bus ”, − IEEE
Std. 1394-1995-("IEEE Std. 1394-1995") standardized high-speed serial bus ("1
394 serial bus ”. ) Related to the transceiver circuit used.

[0002]

2. Description of the Related Art A personal computer, a printer,
In order to connect a peripheral device such as a hard disk and a scanner, a video device such as a digital camera and an audio device (hereinafter, such a terminal device is referred to as a "node") to transfer a control signal or a main signal, A network configured using a 1394 serial bus is considered.

Each node has a state machine which is roughly classified into four, and the state machine transits its state by a signal from an adjacent node connected thereto. The four state machines consist of three processes (Bus Reset process, Tree ID process, Self I) that initialize the network.
Process (N process) and node that performs normal communication (N
ormal process) and.

A plurality of states are defined in each process. In the Bus Reset process, R0: Reset Start and R
Two states of 1: Reset Wait are defined. Also, Tr
In the eeID process, T0: Tree ID start, T1: Child Hands
Four states are defined: hake, T2: Parent Handshake, and T3: Root Contention. Similarly, the Self ID process has five states (S0: Self ID start, S1: Self ID Gran
t, S2: Self ID Receive, S3: Send Speed Capabilitie
s, S4: Self ID Transmit), but 7 states (A0: Idle, A1: Request Test, A2: Request Dela) in the Normal process.
y, A3: Request, A4: Grant, A5: Receive, A6: Transmit)
Is defined.

Next, two nodes A and B according to the prior art are used.
The operation of state transition between the two will be described.

FIG. 7 shows the state transition as described above.
The case of the rmal process is shown as an example. As the initial state, the node B is in the A0: Idle state, and the description will be given from the A3: Request state in which the node A issues a transmission request.

First, the node A transmits a transmission request signal request to the node B, and the node B receives the request signal and changes the state of its own node to A4: Grant. Send back the transmission permission signal grant.

Next, the node A receives the grant signal, changes the state of its own node to A6: Transmit, transmits the data_prefix signal indicating the beginning of the data to the node B, and then transmits the data. To start. The node B receives the data_prefix signal and changes the state of its own node to A5: Rece
Change to ive and receive data.

When the node A finishes transmitting the data, it changes the state of its own node to A0: Idle and transmits data_end indicating the end of the data to the node B. When the node B receives the data_end and finishes receiving the data, it changes the state of its own node to A0: Idle.

Next, node A changes from state A3: Request to state
A6: The change in the signal on the cable will be explained, focusing on the case of transition to Transmit.

A conventional transmitting / receiving circuit is IEEE Std. 1394-199.
5 pp76, and is configured as shown in FIG. 8, for example. In the figure, the cable between the nodes A and B is composed of two pairs of signal lines TPA and TPB for transmitting two kinds of signals. In packet transmission, TPA transmits a strobe signal and TPB transmits a data signal. Since TPA and TPB intersect and are connected to the adjacent node, TPA is connected as the TPB of the adjacent node and TPB is connected to the TPA of the adjacent node.

Arbitration signals such as requests and grants at the nodes A and B are represented by three voltage levels (0, Z, 1), specifically three-state signals, and processed in an analog manner. For example, the request transmission signal is (TPA, TPB) =
(Z, 0), the grant transmission signal is (TPA, TPB) = (Z, 0), I
The dle transmission signal is assigned and processed as (TPA, TPB) = (Z, Z).

Further, since TPA and TPB are crossed on the transmitting side and the receiving side and the signals of the node A and the node B are connected so as to collide with each other, the transmission signal level and the voltage level on the cable are Correspondence will be different. For example, Id
When node B in the le state receives the request transmission signal from node A, the idle transmission signal output from node B collides with the request transmission signal from node A where TPA and TPB intersect, resulting in the voltage on the cable. Level is Idle (Z, Z)
+ Request (0, Z) = (0, Z). On the receiving side, such a voltage level (0, Z) is identified by a comparison circuit and re
Interpret as receiving a quest.

Similarly, the node A outputs the request transmission signal (Z, 0) in the state A3: Request, and the voltage level r colliding with the grant transmission signal (Z, 0) transmitted from the node B.
When equest (Z, 0) + grant (0, Z) = (0, 0) is received, the comparator circuit identifies this and interprets it as grant reception, and transits the state of the own node to A6: Transmit.

As described above, in the conventional transmission / reception circuit, the result of collision between the signals output from the two connected nodes is received, the voltage level is identified, and the upper state machine is transited.

[0016]

In the case of adopting the structure in which the arbitration signal is represented in the voltage level in an analog manner and transmitted, the transmission distance of the cable limits the transmission distance of the signal to several meters. It Therefore, in order to perform long-distance signal transmission, the digital signal format used in the state machine is used as it is, and the arbitration signal is digitally expressed by a 0/1 signal with a t-bit width, and transmitted on the transmission line. It is considered that serial transmission is performed after performing road code conversion.

However, the arbitration signal is a digital signal (for example, t = 5, Idle is (11111), and request is (001
00)), the signal generated by the collision of both signals output by the adjacent node has a meaning due to a t-bit width boundary and a clock mismatch at each of the transmitting node and the receiving node. You can't get a signal. Therefore, the receiving side cannot interpret the received signal and cannot correctly transit the state of the state machine.

(Object of the Invention) The present invention has been made in order to solve the above-mentioned problems, and allows the state of a conventional state machine to make a normal transition even when the arbitration signal is expressed in digital form. It is an object of the present invention to provide a transmitting / receiving circuit capable of performing the above.

[0019]

In order to achieve the above object, the transmitting / receiving circuit of the present invention is a state machine (2 in FIG. 1).
A collision signal generation circuit that digitally generates a collision signal using the transmission signal for arbitration output from the receiver and the reception signal output from the reception circuit (4 in FIG. 1) that has received the signal from the adjacent node ( 1) of FIG.

The transmitter / receiver circuit of the present invention digitally converts the signal output from the adjacent node from the received signal from the receiver circuit (4 in FIG. 5) and the signal from the state machine (2 in FIG. 5). A collision signal is digitally generated from the transmission signal generation circuit (5 in FIG. 5) to be generated, the signal from the transmission signal generation circuit, and the signal from the state machine, and the transmission circuit (FIG. 5) is generated.
No. 3), the collision signal generation circuit (1 in FIG. 5) is provided.

(Operation) By using a collision signal generation circuit that digitally generates a collision signal, the signal transmission path is digitized without changing the conventional state machine.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

<First Preferred Embodiment> FIG. 1 is a block diagram showing a transmitting / receiving circuit according to a first preferred embodiment of the present invention. In this embodiment, a transmission / reception circuit is configured so that a collision signal is generated on the signal reception circuit side and is output to a state machine. In FIG. 1, the transmission / reception circuit includes a collision signal generation circuit 1, a state machine 2, a transmission circuit 3 and a reception circuit 4.

The collision signal generation circuit 1 receives the collision signal from the reception circuit 4.
It has a function of generating a collision signal from an n-bit width digital signal and an m-bit width digital signal from the state machine and outputting an r-bit width digital signal.

The state machine 2 includes a collision signal generation circuit 1
It has a function of changing the internal state by an r-bit width digital signal from and outputting the signal transmitted to the adjacent node as an m-bit width digital signal.

The transmission circuit 3 uses the m from the state machine 2.
It has a function of converting a bit-width digital signal into a transmission path code, further converting into a serial signal, and then serially outputting to a transmission medium for serial transmission (for example, an optical fiber).

The receiving circuit 4 has a function of receiving a serial signal from a transmission medium, inversely converting the transmission path code, and outputting an n-bit wide digital signal.

Next, the operation of the transmission / reception circuit of this embodiment will be described by exemplifying the exchange of signals between the nodes A and B shown in FIG. 7, assuming that m = 4, n = 4, r = 4. To do.

FIG. 2 shows digital signals of the present invention having m, n and r bit widths and signals (TPA, TPB) on a conventional cable.
It is a figure which shows the relationship with the voltage level (Z, 0, 1). Below, the m-bit width digital signal output from the state machine is the transmission code Tx_Arb, and the n-bit width digital signal output from the reception circuit is the reception code Rx_Arb,
The r-bit width digital signal output from the collision signal generation circuit 1 is referred to as a collision code Tx_Col. Note that Tx_Arb, Rx_A
The numbers in parentheses of rb and Tx_Col represent the bit numbers.

In FIG. 2, the voltage levels Z, 0, 1 on the conventional cable are all represented as 2-bit digital signals, and (01), (0
0), (11), and (00), (01), (10) in the collision signal. Also, signals on conventional cables (TP
A, TPB) is represented by a 4-bit digital signal that is a combination of these.

FIG. 3 is a diagram showing a correspondence relationship between input / output codes based on code conversion of the collision signal generation circuit 1.
The function of converting to a collision code according to the combination of the input of the transmission code and the reception code is shown together with the conventional display of the voltage level. In the collision signal generation circuit 1, according to FIG. 3, the upper 2 bits (m / 2 bits) of the transmission code and the lower 2 bits of the reception code are
Bits (n / 2 bits) to the upper 2 bits of the collision code (r /
2 bits), and the lower 2 bits (r / 2 bits) of the collision code are generated from the lower 2 bits (m / 2 bits) of the transmitted code and the upper 2 bits (n / 2 bits) of the received code. .

Below, the upper m / 2, n / 2, and r / 2 bits are set to TPB,
The lower m / 2, n / 2, and r / 2 bits will be described in association with the TPA.

The state machine of node A uses state A3: Req
When it is in uest, (00 01) (voltage level (TPA, TPB) of conventional cable = (Z, 0): corresponding to request transmission) is output to the collision signal generation circuit 1 as a transmission code. Further, at this time, if the node A receives the grant signal from the adjacent node, the reception circuit 4 receives the reception code (00 01) (conventional cable voltage level (TPA, TPB) =
(Z, 0): Corresponds to grant transmission. ) Is output to the collision signal generation circuit 1.

The collision signal generation circuit 1 generates the upper 2 bits 01 of the collision code from the upper 2 bits 00 of the transmission code and the lower 2 bits 01 of the reception code. Further, the lower 2 bits 01 of the collision code are generated from the lower 2 bits 01 of the transmission code and the upper 2 bits 00 of the reception code. Therefore, the collision signal generation circuit 1 outputs the collision code (01 01) (corresponding to the conventional cable voltage level (0, 0): grant reception) to the state machine 2. The state machine that received the collision code (01 01) transits the state to A6: Transmit.

The adjacent node B facing the node A also has a transmitting / receiving circuit similar to that shown in FIG. 2, and the transmitting circuit and the receiving circuit of both are connected to each other, and other transmitting / receiving circuits as shown in FIG. The processing is similarly performed by the digital signal in each of the nodes A and B according to FIG. 3, and the transition operation of the state machine is executed in the same manner as in the conventional case.

In the present embodiment, the collision signal generating circuit 1 has a configuration for performing digital processing shown in FIG. 3, but it can be configured to perform analog processing. FIG. 4 shows an example of a circuit that performs such processing.

The collision signal generation circuit shown in FIG. 4 has the two bits (m / 2) output from the state machine 2 and the reception circuit 4.
Bit, r / 2 bit), and the collision signal generation circuit 1 of FIG. 1 is constituted by the pair of circuits shown in FIG.

The collision signal generation circuit uses the lower 2 bits Tx_Arb [0] and Tx_Arb [1] of the digital signal output of the state machine 2.
The inversion signal of the exclusive OR of is used as the enable signal of the transmission driver, and the lower 2 bits of the digital signal output of the reception circuit
The inverted signal of the exclusive OR of Rx_Arb [2] and Rx_Arb [3] is used as the enable signal of the reception driver, the outputs of the transmission and reception drivers are commonly connected, and the comparison circuit is connected to this common connection. Tx for the signal input to the transmission driver
Use _Arb [0] and Rx_ for the signal input to the receiving driver
By using Arb [2], the transmission driver output and the reception driver output collide with each other at the common connection portion, and the collision signals Tx_Col [1] and Tx_Col [0] are detected by the two comparison circuits. Although the lower two bits of the collision encoded by Figure 4 is generated, for the upper 2 bits of the collision code, respectively Tx_Arb [0] in FIG. 4, Tx_Arb [1] to T x_Arb [2], Tx_Arb
Rx_Arb [2], Rx_Arb [3] to Rx_Arb [0], Rx_Arb [1] in [3]
Use the circuit specified in.

<Second Embodiment> FIG. 5 is a block diagram showing a transmitting / receiving circuit according to a second embodiment of the present invention. In the present embodiment, the transmission / reception circuit is configured so that a collision signal is generated on the signal transmission circuit side and output to the opposite node. In the figure, the transmission / reception circuit includes a collision signal generation circuit 1, a state machine 2, a transmission circuit 3, a reception circuit 4, and a transmission signal generation circuit 5.

The collision signal generation circuit 1 includes a state machine 2
M-bit wide digital signal and transmission signal generation circuit 5
It has a function of generating an r-bit width collision signal from an n-bit width digital signal from.

The state machine 2 receives the r signal from the receiving circuit 4.
It has a function of changing the internal state by a bit-width digital signal and outputting a signal transmitted to an adjacent node as an m-bit width digital signal.

The transmitting circuit 3 receives the signal from the collision signal generating circuit 1.
It has a function of converting a digital signal indicating an r-bit width collision code into a serial signal and serially outputting it to a transmission medium for serial transmission (for example, an optical fiber).

The receiving circuit 4 has a function of receiving a serial signal from a transmission medium and outputting a digital signal indicating an r-bit width collision code.

The transmission signal generation circuit 5 includes the state machine 2
From the digital signal indicating the transmission code of m-bit width from and the digital signal indicating the collision code of r-bit width from the receiving circuit 4, the n-bit width digital signal indicating the transmission code output by the state machine of the adjacent node. Has the function of outputting. For the transmission signal generation circuit 5, the conversion function described in Japanese Patent Application No. 08-190743 (Table 3 on pages 11 and 12) can be used.

Next, the operation of the transmission / reception circuit of the present embodiment shown in FIG. 5 will be described with an example of signal exchange involving state transition between nodes A and B shown in FIG. 7, where m = 4, n = 4, Explanation will be made assuming r = 4.

Each of the adjacent nodes A and B has a structure including a transmission / reception circuit as shown in FIG. 5, and the transmission circuit and the reception circuit of each node are connected to each other.

First, assuming that the state machine of the node B is in the A0: Idle state in the initial state and the state machine of the node A has transited to the state A3: Request, the state machine 1 of the node A has a transmission code (00 01 ) (Voltage level (Z, 0) of conventional cable: corresponding to request transmission) is output to the collision signal generation circuit 5. In the transmission signal generation circuit 5, from the collision code (00 00) from the reception circuit 4 (corresponding to the voltage level (Z, Z) of the conventional cable: idle reception) and the transmission code (0001) from the state machine 2, Recognizes that the transmission code output by state machine B is idle, and the reception code (01 01)
(Corresponding to the transmission code of the state machine of the node B) is output to the collision signal generation circuit 1.

The collision signal generation circuit 1 includes a state machine 2
The collision code (00 01) generated according to FIG. 6 from the transmission code from the transmission code and the reception code from the transmission signal generation circuit 5 is output to the transmission circuit. The collision code is transmission line encoded, serialized, and output to the transmission line. Node B is node A
Received a collision code from
4: Transition to Grant.

Next, the state machine of the node B outputs (00 01) (corresponding to the voltage level (Z, 0) of the conventional cable: grant transmission) as a transmission code to the collision signal generation circuit 1. Based on the collision code (00 01) from the reception circuit 4 and the transmission code (00 01) from the state machine 2, the transmission signal generation circuit 5 confirms that the transmission code output by the state machine 2 of the node A is request. It recognizes and inputs the reception code (00 01) (corresponding to the transmission code of the state machine 2 of the node A) to the collision signal generation circuit 1. Collision signal generation circuit 1 uses transmission code (00 01)
And the collision code (01 01) from the reception code (00 01) is output to the transmission circuit 3. The collision code is transmission line encoded, serialized, and output to the transmission line. Node A receives the collision code from node B and changes the state of state machine 2 to A.
6: Transition to Transmit.

Hereinafter, the exchange of signals accompanied by the state transition between the nodes A and B shown in FIG. 7 is similarly performed by digital signals according to FIG. Also in this embodiment, the collision signal generation circuit can be configured as shown in FIG. 4 in which the driver is used to perform analog processing.

In the above embodiments, the processing of the transmission code, the reception code, and the collision code is divided into the high-order bit and the low-order bit, but the division method of each code can be performed arbitrarily. Also, it is possible to perform conversion processing collectively without dividing each code. As a transmission signal from the state machine, a conversion circuit for directly outputting a digital signal in the state machine, or an analog output as in the conventional example, and converting it into a digital signal again at the output end It goes without saying that it is also possible to configure so that.

[0052]

According to the transmission / reception circuit of the present invention, the conventional state machine can be used even in the case of digitally transmitting the arbitration signal conventionally transmitted in analog. In addition, since it is possible to use a digital signal for transmitting a signal between the nodes, the limitation of the transmission distance between the nodes due to the transmission loss of the cable is relaxed.

[0053]

[Brief description of drawings]

FIG. 1 is a block diagram showing a transmission / reception circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a digital signal handled by a state machine and a voltage level of a signal on a conventional cable.

FIG. 3 is a diagram showing a relationship between an input / output code of the collision signal generation circuit according to the first embodiment and a voltage level of a signal in a conventional cable.

FIG. 4 is a diagram showing a modified example of the collision signal generation circuit of the first embodiment.

FIG. 5 is a block diagram showing a transmission / reception circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing the relationship between the input / output code of the collision signal generation circuit of the second embodiment and the voltage level of the signal in the conventional cable.

FIG. 7 is an example showing a relationship between a state transition of a state machine and a transmission / reception signal.

FIG. 8 is a diagram showing a conventional transmission / reception circuit.

[Explanation of symbols]

1 Collision signal generation circuit 2 state machines 3 transmitter circuit 4 Receiver circuit 5 Transmission signal generation circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 25/02 H04L 12/28 H04B 1/04 H04B 1/40

Claims (9)

(57) [Claims] 1. A state transition is performed by a collision signal that is a combination of transmission signals from two opposing transmission / reception circuits, and a binary parametrization is performed.
A state machine for outputting a barrel transmission signal, as a binary type a parallel transmission signal and transmitting circuit for outputting a transmission signal to the transmission line, receives a received signal from the transmission path binary parallel received signal from the state machine A collision signal is synthesized by using a receiving circuit for outputting, a binary parallel transmission signal from the state machine, and a binary parallel reception signal from the receiving circuit, and a binary parallel collision signal is output to the state machine. A transmission / reception circuit comprising a collision signal synthesis circuit. 2. A state machine that outputs a binary parallel transmission signal by causing a state transition by a collision signal that is a combination of transmission signals from two opposing transmission / reception circuits, and a binary parallel transmission signal from the state machine. Then, a transmission circuit that performs transmission line code conversion and serialization and outputs a transmission signal to the transmission line, and a reception signal from the transmission line is received, and parallelization and transmission line code inverse conversion are performed, and a binary parallel reception signal is output. Collision that synthesizes a collision signal using a receiving circuit that performs the above, a binary parallel transmission signal from the state machine, and a binary parallel reception signal from the receiving circuit, and outputs a binary parallel collision signal to the state machine. A transmission / reception circuit comprising a signal generation circuit. 3. The collision signal generation circuit converts a binary parallel transmission signal from the state machine and a binary parallel reception signal from the reception circuit into an analog signal having three or more amplitude levels, The transceiver circuit according to claim 1 or 2, wherein the collision signals are combined by simultaneously driving the drivers that generate the two analog signals, and are then converted into a binary parallel collision signal. 4. The transmission / reception circuit according to claim 3, wherein a three-state signal is used as the analog signal. 5. A state machine that outputs a binary parallel transmission signal by causing a state transition by a collision signal obtained by synthesizing transmission signals from two opposing transmission and reception circuits, and a transmission circuit that outputs the collision signal to a transmission path. From a receiving circuit that receives a collision signal from a transmission line and outputs a binary parallel collision signal to the state machine, a binary parallel collision signal from the receiving circuit, and a binary parallel transmission signal from the state machine, A transmission signal generation circuit that generates a binary parallel transmission signal output by a state machine of an adjacent transmission / reception circuit, a binary parallel transmission signal from the state machine, and a binary parallel transmission output by the transmission signal generation circuit. And a collision signal generating circuit for synthesizing a binary parallel collision signal using the signal and outputting the synthesized parallel collision signal to the transmitting circuit. circuit. 6. A state machine that outputs a binary parallel transmission signal by causing a state transition by a collision signal obtained by synthesizing transmission signals from two opposing transmission / reception circuits, and transmission line code conversion and serialization to a transmission line. A transmission circuit that outputs a collision signal, a reception circuit that receives the collision signal from the transmission line, performs parallelization and transmission line code inverse conversion, and outputs a binary parallel collision signal to the state machine, and a reception circuit from the reception circuit. A transmission signal generation circuit that generates a binary parallel transmission signal output from a state machine of an adjacent transmission / reception circuit from a binary parallel collision signal and a binary parallel transmission signal from the state machine; and a transmission signal generation circuit from the state machine. A binary parallel collision signal is synthesized using the binary parallel transmission signal and the binary parallel transmission signal output from the transmission signal generation circuit, And a collision signal generation circuit for outputting to a transmission circuit. 7. The collision signal generation circuit converts a binary parallel transmission signal from the state machine and a binary parallel transmission signal from the transmission signal generation circuit into an analog signal having three or more amplitude levels. 7. The transceiver circuit according to claim 5, wherein the collision signals are combined by simultaneously driving the drivers that generate the two analog signals, and then converted into a binary parallel collision signal. 8. The transmission / reception circuit according to claim 7, wherein a three-state signal is used as the analog signal. 9. A state machine for transitioning states by a collision signal obtained by combining transmission signals from two opposing transmission / reception circuits and outputting the transmission signal, a transmission circuit for outputting the collision signal to a transmission line, and a transmission line. Receiving a collision signal from the receiving circuit and outputting a collision signal to the state machine, and a collision machine from the receiving circuit and a transmission signal from the state machine, a state machine of an adjacent transmitting / receiving circuit outputs. A transmission signal generation circuit for generating a transmission signal,
A collision signal generation circuit that pseudo-combines a collision signal using a transmission signal from the state machine and a transmission signal output from the transmission signal generation circuit and outputs the collision signal to the transmission circuit. Transceiver circuit.