JP3436018B2 - Programmable element and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically programmable programmable element incorporated in a semiconductor integrated circuit device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the development period of electronic equipment, whether for industrial or consumer use, has exceeded the product life time, and products are required to be multifunctional and diversified. There is an urgent need to shorten the time until manufacturing and reduce manufacturing costs. Therefore, even in the semiconductor device manufacturing industry, FPGA (Fiel) that can program logic at hand can be used as a prototype of the gate array or its substitute.
d-Programmable Gate Array) has been used.
There are two main programming methods of FPGA, a memory method and an anti-fuse method. From the viewpoint of speeding up and high integration of the FPGA, an anti-fuse method using an anti-fuse as a program element is considered promising. The antifuse is usually a high resistance element, and by changing it to a low resistance state by an electrical programming signal, the basic logic element on the chip and the wiring are connected to enable writing in the design or manufacturing site, This is a circuit that allows the user's circuit to be realized in the field.

Among semiconductor integrated circuit devices, a so-called PROM (Programmable ROM) in which contents can be electrically written after purchase by a user is a ROM having desired contents.
(ReadOnly Memory) is widely used because it can be obtained immediately.

In the field of logic circuits, a so-called PLD (Programmable Logic Device), which allows the user to electrically write the contents after purchase, is also used for a similar purpose. In order to configure a PROM or PLD, the memory contents can be electrically written from the outside,
In addition, it is necessary to use a programmable element that can retain its stored contents even when the power is turned off.

FIG. 4 is a cross-sectional view showing the structure of a conventional programmable element, which shows a thick oxide layer 1 on a semiconductor substrate 9.
The lower wiring 2, the lower electrode 3, and the programming insulating film 4 which are patterned to have a desired size in contact with the upper surface of the are sequentially laminated. The lower wiring 2, the lower electrode 3, and the programming insulating film 4 are covered with a thick interlayer insulating film 5, but a portion of the upper surface of the programming insulating film 4 where the thick interlayer insulating film 5 is not formed, That is, the area 6 to be programmed is provided, and the upper electrode 7 and the upper wiring 8 are sequentially laminated so as to cover the area 6 to be programmed.

For programming, a voltage of about 10 V is applied between the upper electrode 7 and the lower electrode 3 to break the insulation of the program insulating film 4 and electrically connect the upper electrode 7 and the lower electrode 3. It is done by

FIG. 5 is a diagram showing a conventional method for manufacturing a programmable element. First, as shown in FIG. 5A, an aluminum alloy film 2a and a titanium nitride film are formed on a thick oxide layer 1 on a semiconductor substrate 9. The film 3a is deposited by the sputtering method, and then the amorphous silicon film 4a is plasma CV.
It is formed by sequentially stacking by the D method.

Next, as shown in FIG. 5B, the amorphous silicon film 4a and the titanium nitride film 3 are formed by using the conventional photolithography technique and dry etching technique.
a, the aluminum alloy film 2a is simultaneously patterned,
The program insulating film 4, the lower electrode 3, and the lower wiring 2 are formed.

Next, as shown in FIG. 5C, after forming a thick insulating film, the surface thereof is flattened to form a thick interlayer insulating film 5.
To provide.

Next, as shown in FIG. 5D, a desired portion of the thick interlayer insulating film 5 located on the upper surface of the program insulating film 4 is subjected to the photolithography technique, the wet etching technique and the dry etching technique. Area to be programmed by etching (hereinafter,
Open the program area 6).

Next, as shown in FIG. 5 (e), a titanium nitride film and an aluminum alloy film are sequentially laminated by a sputtering method, and then patterned into desired dimensions by using a photolithography technique and a dry etching technique. The upper electrode 7 and the upper wiring 8 are formed.

[0012]

However, in the above conventional structure, since the program region 6 is formed by opening the thick interlayer insulating film 5, after the thick interlayer insulating film 5 is etched and the program region 6 is opened. Due to the over-etching, the programming insulating film 4 located immediately below is thinned or damaged, so that the dielectric breakdown voltage of the programming insulating film 4 is lowered, and there is a problem that variations in characteristics are increased. Was there. Also,
Since the program region 6 is formed by opening the thick interlayer insulating film 5, the aspect ratio of the opening of the program region 6 is increased, the coverage of the upper electrode 7 is lowered, and the programming insulating film 4 after programming is formed. There was also a problem that reliability in a conductive state deteriorates.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a higher quality programmable element which can suppress the deterioration of the electrical characteristics of the programming insulating film.

[0014]

To achieve the above object, a programmable element according to the present invention is provided with a lower wiring arranged on an oxide layer formed on a semiconductor substrate and an upper surface of the lower wiring. Programmable lower electrode, a programming insulating film formed on the lower electrode, an upper electrode formed on the upper surface of the programming insulating film, and an upper wiring arranged on the upper surface of the upper electrode. The device is a two-layer structure that covers the peripheral upper surface of the programming insulating film excluding the program region on the programming insulating film from the upper surface of the lower electrode to the side surface of the lower wiring, and between the upper surface of the oxide layer and the upper wiring. It is possible to reduce the absolute amount of overetch applied to the program insulating film by reducing the variation in the overetch amount and to prevent the insulating film for programming from being interrupted. It is possible to suppress the reduction and variation in breakdown voltage.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 is a lower wiring arranged on an oxide layer formed on a semiconductor substrate, and a lower electrode provided on the upper surface of the lower wiring.
An insulating film for programming formed on the lower electrode,
A programmable element having an upper electrode formed on an upper surface of the programming insulating film and an upper wiring arranged on an upper surface of the upper electrode, the programming insulating film excluding a program region of the programming insulating film. From the peripheral upper surface of the lower electrode, covering the side surface of the lower wiring, between the upper surface of the semiconductor substrate or the oxide layer and the upper wiring,
Since the inter-layer insulating film having a two-layer structure is provided, deterioration of the electrical characteristics of the programming insulating film can be suppressed, and a higher quality programmable element can be obtained.

According to a second aspect of the present invention, the interlayer insulating film having the two-layer structure of the programmable element according to the first aspect is composed of a thin interlayer insulating film and a thick interlayer insulating film. By adopting a structure with an interlayer insulating film, it is possible to prevent the breakdown voltage of the programming insulating film from lowering and increase in variation, and improve the reliability in the conductive state after breaking the insulation of the programming insulating film. Can be made.

According to a third aspect of the present invention, a lower wiring provided on an oxide layer formed on a semiconductor substrate, a lower electrode provided on the upper surface of the lower wiring, and a lower electrode of the lower electrode are provided. A thin interlayer insulating film, which is a programmable element having a programming insulating film formed above, an upper electrode formed on an upper surface of the programming insulating film, and an upper wiring arranged on an upper surface of the upper electrode. However, a thick interlayer insulating film covers the surface of the program insulating film excluding the program region and at least the side surface of the program insulating film, the lower electrode and the lower wiring, and An oxide layer formed on the semiconductor substrate including the peripheral portion of the upper electrode, which is provided over the upper surface of the thin interlayer insulating film that is connected to and covers the upper peripheral portion of the programming insulating film, and the upper portion. Since it is formed between the line and the line, the absolute amount of overetch applied to the program insulating film can be reduced, and the variation in the overetch amount can be reduced to reduce or reduce the dielectric breakdown voltage of the program insulating film. Can be suppressed.

According to a fourth aspect of the invention, the thin interlayer insulating film of the programmable element according to the second or third aspect is 50 to 50.
It has a thickness of 500 nm, and this thin film thickness defines a region where a thin interlayer insulating film having a limited film thickness works effectively, and has a dielectric breakdown voltage of the program insulating film. It is possible to suppress the decrease of the resistance and the increase of the variation and to improve the reliability in the conductive state after the insulation of the programming insulating film is broken.

According to a fifth aspect of the present invention, a peripheral corner of a programming insulating film in a three-layer structure composed of a lower wiring, a lower electrode and a programming insulating film of the programmable element according to the second, third or fourth aspect. Section and the portion where the three-layer structure is in contact with the oxide layer form a curved cross-sectional shape of the thin interlayer insulating film, and titanium nitride, which is a constituent material of the upper electrode, is etched on the side wall of the thin interlayer insulating film. It has the effect of not causing the rest.

According to a sixth aspect of the present invention, a step of forming an oxide layer on a semiconductor substrate, a step of forming a lower wiring and a lower electrode on the oxide layer, and a program on the lower electrode. Forming an insulating film for insulation, forming a thin interlayer insulating film on at least the upper surface and the side surface of the insulating film for programming, and the side surface of the lower electrode and the lower wiring, Opening a desired portion of the thin interlayer insulating film to expose the surface of the programming insulating film; and forming an upper electrode on the upper surface of the programming insulating film in the opening of the thin interlayer insulating film. A step of forming a thick interlayer insulating film on the upper electrode, a step of opening a desired portion of the thick interlayer insulating film to expose a surface of the upper electrode, and a step of forming an opening in the thick interlayer insulating film. Dew And a step of forming an upper wiring on the upper surface of the upper electrode, which suppresses a decrease in dielectric breakdown voltage of the programming insulating film and an increase in variations, and after programming the programming insulating film. The reliability in the conducting state can be improved.

An embodiment of the programmable element of the present invention will be described below with reference to the sectional view of FIG.

In FIG. 1, 10 is a semiconductor substrate, 11 is an oxide layer, 12 is a lower wiring, 13 is a lower electrode, 14 is a program insulating film, 15 is a thin interlayer insulating film, 16 is a program region, and 17 is an upper part. Electrodes, 18 is a thick interlayer insulating film,
Reference numeral 19 is an upper wiring.

FIG. 2 is a plan view of this embodiment.
, 13 is a lower electrode, 16 is a program area, 1
Reference numeral 7 is an upper electrode, 19 is an upper wiring, and 20 is an overlap margin.

Programming of the PLD is performed by the upper wiring 19
A voltage of about 10 V is applied between the upper electrode 17 through the lower electrode 13 and the lower electrode 13 through the lower wiring 12 to break the insulation of the programming insulating film 14 and thereby to prevent the upper electrode 17 and the lower electrode 1 from passing.
This is performed by electrically connecting 3 and 3.

The operation of the programmable element configured as described above will be described below.

In the programmable element of the present embodiment, by having a thin interlayer insulating film 15 having a thickness of, for example, about 200 nm, this thin interlayer insulating film 15 is provided.
When the program region 16 is opened by etching the substrate, the amount of overetching during etching is set to 20
It can be reduced to about 1/10 of that in the case of the interlayer insulating film having a thickness of about 00 nm. Therefore, the amount of overetching applied to the program insulating film 14 can be reduced to about 1/10, and as a result, the dielectric breakdown due to the reduction in the film thickness of the program insulating film 14 and the damage applied to the program insulating film 14 is caused. It is possible to suppress a decrease in breakdown voltage. Further, the variation in the film thickness to be etched when opening the program region 16 is, for example, ± 1.
0%, ± 20n for thin interlayer insulating film 15
m, ± 200 nm in the case of the conventional thick interlayer insulating film 5. Therefore, when the same amount of overetch is applied, the variation in the amount of overetch applied to the programming insulating film 14 is also about 1/10, and as a result, the variation in the dielectric breakdown voltage of the programming insulating film 14 can be suppressed. It will be possible.

Further, in the programmable element of the present embodiment, the upper electrode 17 is connected to the upper surface of the program insulating film 14 exposed in the portion of the program region 16, and the program insulating film 14 is exposed. Thin interlayer insulating film 1 covering the surface other than the program area 16
Since the upper surface of No. 5 is also overlapped and covered, there is an effect that it is possible to maintain a structure with a margin against dimensional variations of the lower electrode 13 and the upper electrode 17 and mask misalignment.

Next, an embodiment of a method of manufacturing a programmable element according to the present invention will be described with reference to the process sectional view of FIG.

In FIG. 3A, a thickness of 500 to 100 is formed on the thick oxide layer 11 formed on the semiconductor substrate 10.
Aluminum alloy layer 22 of about 0 nm, thickness 200 to 3
A titanium nitride layer 23 having a thickness of about 00 nm is deposited by a sputtering method, and subsequently, a composite film 24 of a silicon nitride film having a thickness of about 5 to 10 nm and an amorphous silicon film having a thickness of about 50 to 100 nm is sequentially laminated by a plasma CVD method. Form.

Next, as shown in FIG. 3B, a composite film 24 made of a silicon nitride film and an amorphous silicon film, a titanium nitride layer 23 and an aluminum alloy layer 22 are simultaneously formed by using a photolithography technique and a dry etching technique. Etching and programming insulation film 1
4, the lower electrode 13 and the lower wiring 12 are simultaneously patterned and formed.

Next, as shown in FIG. 3C, the thickness 10
After the thin interlayer insulating film 15 of about 0 to 300 nm is grown by the plasma CVD method using TEOS, the corner portions of the thin interlayer insulating film 15 are smoothed by argon sputtering as shown by 15a and 15b in the figure. Let it be a curved surface.
Then, a desired portion of the thin interlayer insulating film 15 located on the upper surface of the program insulating film 14 is etched by using the photolithography technique, the wet etching technique, and the dry etching technique to open the program region 16 for programming. A part of the upper surface of the insulating film 14 is exposed.

Next, as shown in FIG.
After depositing a titanium nitride layer having a thickness of 0 to 300 nm by a sputtering method, a desired pattern is formed by using a photolithography technique, and the titanium nitride layer is isotropically etched by a dry etching technique under predetermined conditions and time. To form the upper electrode 17. At this time, the outer surface 17a of the upper electrode 17 has a taper shape in which the upper part recedes by about 0.2 to 0.3 μm, but almost no etching residue of titanium nitride occurs on the side wall of the thin interlayer insulating film 15.

Next, as shown in FIG.
After growing an insulating film having a thickness of about 00 to 2500 nm by a plasma CVD method using TEOS, a flattening process is performed to form a thick interlayer insulating film 18. Then, an opening to be the program region 16 is provided on the upper electrode 17 by using the photolithography technique and the dry etching technique.
Further, the programmable element is completed by forming the upper wiring 19 made of titanium and aluminum alloy having a thickness of about 700 to 1000 nm.

[0034]

As described above, according to the present invention, the absolute amount of overetch applied to the program insulating film is reduced, and the variation in the overetch amount is also reduced to reduce the dielectric breakdown voltage of the program insulating film. It is possible to suppress an increase in variation and improve the reliability in a conductive state after programming the programming insulating film, and it is possible to realize a higher quality programmable element.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining an embodiment of a programmable element of the present invention.

FIG. 2 is a plan view for explaining the embodiment.

3A to 3E are process cross-sectional views for explaining an embodiment of a method for manufacturing a programmable element of the present invention.

FIG. 4 is a sectional view of a conventional programmable element.

5A to 5E are process cross-sectional views showing a conventional method for manufacturing a programmable element.

[Explanation of symbols]

10 Semiconductor substrate 11 Oxide layer 12 Lower wiring 13 Lower electrode 14 Program insulation film 15 Thin interlayer insulating film 16 program areas 17 Upper electrode 18 thick interlayer insulating film 19 Upper wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Yuasa 1-1 Sachimachi, Takatsuki City, Osaka Prefecture Matsushita Electronic Industrial Co., Ltd. (56) Reference JP-A-7-22513 (JP, A) JP-A 8-264653 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 27/10 H01L 21/822 H01L 27/04

Claims (6)

(57) [Claims] 1. A lower wiring arranged on an oxide layer formed on a semiconductor substrate, a lower electrode provided on an upper surface of the lower wiring, and a programming formed on the lower electrode. A programmable element having an insulating film, an upper electrode formed on the upper surface of the programming insulating film, and an upper wiring arranged on the upper surface of the upper electrode, wherein a programmable region on the programming insulating film is provided. Except for the peripheral insulating upper surface of the programming, the lower electrode and the side surface of the lower wiring are covered, and the lower layer has a two-layer structure between the upper surface of the semiconductor substrate or the oxide layer and the upper wiring.
A programmable device comprising an interlayer insulating film in contact with the peripheral upper surface of the programming insulating film. 2. The programmable element according to claim 1, wherein the interlayer insulating film having a two-layer structure is formed of two layers of a lower thin interlayer insulating film and an upper thick interlayer insulating film. 3. An oxide layer formed on a semiconductor substrate,
A lower wiring disposed on the oxide layer, a lower electrode provided on the upper surface of the lower wiring, a programming insulating film formed on the lower electrode, and an upper surface of the programming insulating film. A thin interlayer insulating film is in contact with a surface of the insulating film for programming except a program region, and a programmable element having an upper electrode formed on the upper electrode and an upper wiring arranged on an upper surface of the upper electrode , A thick interlayer insulating film is formed to cover the program insulating film, the lower electrode, and the side surface of the lower wiring, and a thick interlayer insulating film is connected to the surface of the program region of the program insulating film and is A peripheral portion of the upper electrode provided over the upper surface of the thin interlayer insulating film covering the upper peripheral portion, and between the oxide layer on the semiconductor substrate and the upper wiring; Made is to have a programmable element. 4. The thin interlayer insulating film has a thickness of 50 to 500.
The programmable element according to claim 2 or 3, which has a wavelength of nm. 5. A thin interlayer insulation in a peripheral corner portion of the program insulating film of a three-layer structure composed of a lower wiring, a lower electrode and a program insulating film and a portion where the three-layer structure is in contact with an oxide layer. The programmable element according to claim 2, 3 or 4, wherein the cross-sectional shape of the film forms a curved surface. 6. A step of forming an oxide layer on a semiconductor substrate, a step of forming a lower wiring and a lower electrode on the oxide layer, and a step of forming a programming insulating film on the lower electrode. And contacts the upper surface of the programming insulating film.
As a step of forming a thin interlayer insulating film on a side surface portion of the upper surface and side portions and the lower electrode and the lower wiring of at least the program insulating film, desired of the thin interlayer insulating film on said program insulating film To expose the surface of the program insulating film, a step of forming an upper electrode on the upper surface of the program insulating film in the opening of the thin interlayer insulating film, and a step of forming an upper electrode on the upper electrode. A step of forming a thick interlayer insulating film, exposing a surface of the upper electrode by opening a desired portion of the thick interlayer insulating film, and exposing the upper electrode exposed in the opening of the thick interlayer insulating film. And a step of forming an upper wiring on an upper surface of the programmable element.