JPH08316322A - Anti-fuse element and its production - Google Patents

Abstract

PURPOSE: To reduce the parasitic capacity of an anti-fuse in a wiring. CONSTITUTION: An anti-fuse consisting of a lower electrode 15 that is smaller than a first metallic wiring layer 14, anti-fuse layer 16 and upper electrode 17 is placed on the layer 14, and an interlayer insulation film 18 is formed in the area excluding the electrode 17 on the layer 14 and in a manner to provide a space for a connection hole 24 thereon, then a metallic wiring layer 19 is formed over the layer 18, the inner wall of the hole 24 and the electrode 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antifuse element in a semiconductor integrated circuit and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, as a prototype of a gate array or its substitute, the logic which can be programmed at hand has been developed.
PGA (Field-Programmable Gate Array) is used. In the antifuse method, which is the main programming method of FPGA, the antifuse element is a structure sandwiched between metal wirings as an alternative to the structure sandwiched between polycrystalline silicon and a silicon substrate for high speed and high integration. Is being developed. The antifuse element is
It is normally in a high resistance state, and changes to a low resistance state by an electric programming signal.

A conventional anti-fuse element will be described below with reference to the drawings. FIG. 5 is a sectional view showing a conventional antifuse element. In FIG. 5, 1 is an insulating substrate, 2 is a first metal wiring layer made of an aluminum alloy, 3 is a lower electrode made of titanium nitride, 4 is an antifuse layer made of amorphous silicon, 5 is an upper electrode made of titanium nitride, Reference numeral 6 is an interlayer insulating film, and 7 is a second metal wiring layer made of an aluminum alloy.

The operation of the antifuse element having the above structure will be described below. The anti-fuse element is usually connected to the first metal wiring layer 2 and the second metal wiring layer 2 via the anti-fuse layer 4 sandwiched between the upper electrode 5 and the lower electrode 3.
The metal wiring layers 7 are insulated from each other, and the first metal wiring layer 2 and the second metal wiring layer 7 are not electrically connected. Here, in the case of forming a circuit composed of the first metal wiring layer 1 and the second metal wiring layer 7 which are electrically insulated by the anti-fuse layer 4, first, the first metal wiring layer 2 and the second metal wiring layer 2 are formed. An electrical programming signal is externally provided to the metal wiring layer 7 of FIG. A voltage is applied between the first metal wiring layer 2 and the second metal wiring layer 7 through the antifuse layer 4 sandwiched between the upper electrode 5 and the lower electrode 3 by a programming signal provided from the outside. It First metal wiring layer 2 and second
When the critical value of the voltage applied between the metal wiring layers 7 is established through the antifuse layer 4, the antifuse layer 4 causes a dielectric breakdown. As a result, a low resistance state is created between the first metal wiring layer 2 and the second metal wiring layer 7, and a new circuit including the first metal wiring layer 2 and the second metal wiring layer 7 is formed.

A method of manufacturing the conventional antifuse element shown in FIG. 5 will be described below. 6A to 6E are process cross-sectional views showing the manufacturing process of a conventional antifuse element. 1 is an insulating substrate, 2 is a first metal wiring layer made of an aluminum alloy, 3 is a lower electrode made of titanium nitride, 4
Is an antifuse layer made of amorphous silicon, 5
Is an upper electrode made of titanium nitride, 6 is an interlayer insulating film, 7 is a second metal wiring layer made of an aluminum alloy, 8 is an aluminum alloy film, 9 and 11 are titanium nitride films, and 10 is an antifuse insulation made of amorphous silicon. Membrane, 12
Is a connection hole.

First, after depositing the aluminum alloy film 8 on the insulating substrate 1 by the sputtering method, the titanium nitride film 9 is formed by the sputtering method, the anti-fuse insulating film 10 is formed by the plasma CVD method, and the titanium nitride film 11 is formed by the sputtering method. The layers are sequentially deposited (FIG. 6A). Next, the aluminum alloy film 8, the titanium nitride film 9, the antifuse film 10, and the titanium nitride film 11 are masked with a photoresist and dry-etched to form the upper electrode 5.
Then, the anti-fuse layer 4 and the first metal wiring layer 2 sandwiched between the lower electrodes 3 are formed (FIG. 6B).

Next, an insulating film is deposited by the plasma CVD method and flattened by the resist etch back method to form the interlayer insulating film 6 (FIG. 6C). Next, masking with a photoresist and dry etching are performed to form a connection hole 12 and expose the upper electrode 5 (FIG. 6).
(D)). Next, an aluminum alloy film is deposited by a sputtering method, masked with a photoresist and dry-etched to form a second metal wiring layer 7 (FIG. 6E).

[0008]

However, in the above-mentioned conventional anti-fuse element, the upper electrode 5 and the lower electrode 3 are used.
Is formed to have the same size as the first metal wiring layer 2,
The area of the upper electrode 5 and the lower electrode 3 becomes large, and as a result, the parasitic capacitance becomes large. Therefore, in a semiconductor integrated circuit equipped with an antifuse element, there are many antifuse elements that are not programmed, which causes a problem that the parasitic capacitance between wirings increases and the characteristics of the integrated circuit deteriorate.

An object of the present invention is to solve the above problems of the conventional anti-fuse element, and to provide an anti-fuse element capable of reducing the parasitic capacitance and a manufacturing method thereof.

[0010]

According to another aspect of the present invention, there is provided an antifuse element having a connection between a first metal wiring layer and an area smaller than that of the first metal wiring layer laminated on the first metal wiring layer. An antifuse including a lower electrode having the size of a hole, an antifuse layer, and an upper electrode, and an interlayer insulating film in which a connection hole is provided on the upper electrode by opening and stacking the upper electrode on the first metal wiring layer. And a second metal wiring layer laminated on the interlayer insulating film, the inner wall of the connection hole and the upper electrode.

According to a second aspect of the present invention, there is provided a method of manufacturing an anti-fuse element, which comprises depositing and patterning a conductive film to form a first metal wiring layer, and depositing a first conductor on the first metal wiring layer. A step of depositing an anti-fuse insulator on the first conductor, and a second step on the anti-fuse insulator.
The step of depositing the conductor, and the first conductor, the anti-fuse insulator and the second conductor are etched using the photoresist as a mask to form a lower electrode having a contact hole size smaller than that of the first metal wiring layer. A step of forming an antifuse layer and an upper electrode, and a step of depositing an interlayer insulating film to a thickness such that the upper electrode is buried in the lower electrode, the antifuse layer, the upper electrode and the photoresist and the photoresist is not buried. , A step of exposing the upper electrode by forming a connection hole by removing the photoresist, and a conductive film is deposited and patterned on the interlayer insulating film, the inner wall of the connection hole and the upper electrode to form a second metal wiring layer. And a step of forming.

According to another aspect of the present invention, there is provided an anti-fuse element having a first metal wiring layer and a contact hole having a smaller area than that of the first metal wiring layer laminated on the first metal wiring layer. An antifuse which is composed of a lower electrode, an antifuse layer, and an upper electrode and has an outer peripheral edge of the upper electrode receded inward from an outer peripheral edge of the antifuse layer, and an upper electrode is opened and laminated on the first metal wiring layer. As a result, an interlayer insulating film having a connection hole formed on the upper electrode and a second metal wiring layer laminated on the interlayer insulating film, the connection hole, and the upper electrode are provided.

A method of manufacturing an anti-fuse element according to a fourth aspect of the present invention comprises the steps of depositing and patterning a conductive film to form a first metal wiring layer, and depositing a first conductor on the first metal wiring layer. A step of depositing an anti-fuse insulator on the first conductor, and a second step on the anti-fuse insulator.
And a step of depositing the conductor of the first conductor, the antifuse insulator, and the second conductor are etched using the photoresist as a mask to form a lower electrode having a smaller area than that of the first metal wiring layer and having a size of a substantially contact hole. And a step of forming an antifuse layer and an upper electrode, a step of isotropically etching the photoresist, a step of etching the upper electrode using the isotropically etched photoresist as a mask, an etched upper electrode and an antifuse layer And a step of depositing an interlayer insulating film with a film thickness such that the upper electrode is buried in the lower electrode and the photoresist and the photoresist is not buried, and a connection hole is provided by removing the photoresist to expose the upper electrode. And a step of forming a second metal wiring layer by depositing and patterning a conductive film on the interlayer insulating film, the inner wall of the contact hole and the upper electrode. Including the door.

A method for manufacturing an antifuse element according to a fifth aspect is characterized in that, in the method for manufacturing an antifuse element according to the second or fourth aspect, the interlayer insulating film is deposited by liquid phase growth.

[0015]

According to the antifuse element according to claim 1,
Since the areas of the lower electrode, the antifuse layer, and the upper electrode are the same as the cross-sectional area of the connection hole and smaller than the first metal wiring layer, the parasitic capacitance of the antifuse element is also small. According to the method of manufacturing an antifuse element according to claim 2, the area of the antifuse composed of the lower electrode, the antifuse layer, and the upper electrode is the same as the cross-sectional area of the connection hole, and the first metal wiring is formed. Since it is smaller than the layer, the parasitic capacitance of the unprogrammed antifuse element is also small. Further, since the anti-fuse layer is deposited before forming the connection hole, there is no variation in the thickness of the anti-fuse layer among the anti-fuse elements. Therefore, it is possible to eliminate the variation in the dielectric breakdown voltage during programming due to the variation in the thickness of the antifuse layer, and it is possible to obtain good programming characteristics.

According to the antifuse element of the third aspect, since the area of the upper electrode is the same as the cross-sectional area of the connection hole and is smaller than the first metal wiring layer, the parasitic capacitance of the antifuse element is small. It is possible to Also,
By adopting a structure in which the outer peripheral edge of the upper electrode is recessed inward from the outer peripheral edge of the antifuse layer, the creeping distance between the electrodes at the electrode edge portion becomes large, and the problem of leakage in the antifuse can be solved.

According to the method of manufacturing the antifuse element according to the fourth aspect, since the upper electrode has the same size as the cross-sectional area of the connection hole and is smaller than the first metal wiring layer, the antifuse element not programmed. The parasitic capacitance of is also small. Further, since the outer edge of the upper electrode is recessed inward from the outer edge of the antifuse layer, the creepage distance between the electrodes at the edge portions of the upper electrode and the lower electrode becomes large, and You can eliminate the leak problem. Further, since the anti-fuse layer is deposited before forming the connection hole, there is no variation in the thickness of the anti-fuse layer among the anti-fuse elements. Therefore, it is possible to eliminate the variation in the dielectric breakdown voltage during programming due to the variation in the thickness of the antifuse layer, and it is possible to obtain good programming characteristics.

According to the method of manufacturing an anti-fuse element of the fifth aspect, since the liquid phase growth method is used for forming the interlayer insulating film, the film thickness of the interlayer insulating film is constant over the entire surface of the substrate. Therefore, the step of planarizing the interlayer insulating film, which is usually necessary, can be omitted, and the manufacturing process can be shortened.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An antifuse element according to a first embodiment of the present invention will be described below with reference to the drawings. FIG.
FIG. 3 is a schematic cross-sectional view of the antifuse element according to the first embodiment of the present invention.

In FIG. 1, 13 is an insulating substrate, 14 is a first metal wiring layer made of an aluminum alloy, 15 is a lower electrode made of titanium nitride, 16 is an antifuse layer made of amorphous silicon, and 17 is made of titanium nitride. An upper electrode, 18 is an interlayer insulating film, and 19 is a second metal wiring layer made of an aluminum alloy. The structure of the anti-fuse element according to the first embodiment of the present invention will be described below.

In FIG. 1, the first metal wiring layer 14 and the second metal wiring layer 19 on the insulating substrate 13 are circuit elements of a semiconductor integrated circuit. In addition, the first metal wiring layer 14
The second metal wiring layer 19 includes the interlayer insulating film 18 in a region other than the lower electrode 15, the anti-fuse layer 16, the upper electrode 17 where the anti-fuse element is formed, and a contact required for circuit design. It is insulated by. The lower electrode 15, the anti-fuse layer 16, and the upper electrode 17 have the same shape as the connection hole 24 only at the bottom of the connection hole 24, and are located between the first metal wiring layer 14 and the second metal wiring layer 19. First metal wiring layer 14 and second metal wiring layer 1
9 is insulated.

In other words, this antifuse element has the first
Metal wiring layer 14 and a connection hole 24 having a smaller area than the first metal wiring layer 14 laminated on the first metal wiring layer 14.
A lower electrode 15, an antifuse layer 16 and an upper electrode 17 each having a size of 1 μm, and a connection hole formed on the upper electrode 17 by opening and stacking the upper electrode 17 on the first metal wiring layer 14. Interlayer insulating film 18 provided with 24
And a second metal wiring layer 19 laminated on the interlayer insulating film 18, the inner wall of the connection hole 24 and the upper electrode 17.

Since the areas of the lower electrode 15, the antifuse layer 16 and the upper electrode 17 are the same as the cross-sectional area of the connection hole 24 and smaller than the first metal wiring layer 14,
It is possible to reduce the parasitic capacitance of the anti-fuse element. Next, a method of manufacturing the antifuse element according to the first embodiment of the present invention will be described.

2 (a) to 2 (f) are process sectional views showing the manufacturing method of the first embodiment of the present invention, in which 13 is an insulating substrate, 14 is a first metal wiring layer made of an aluminum alloy, Reference numeral 15 is a lower electrode made of titanium nitride, 16 is an antifuse layer made of amorphous silicon, 17 is an upper electrode made of titanium nitride, 18 is an interlayer insulating film, 19 is a second metal wiring layer made of an aluminum alloy, and 20, 22.
Is a titanium nitride film, 21 is an amorphous silicon film, 23
Is a reverse photoresist pattern for forming connection holes, and 24 is a connection hole.

First, an aluminum alloy is deposited on the insulating substrate 13 by a sputtering method, masked with a photoresist and then dry-etched.
Metal wiring layer 14 is formed, subsequently titanium nitride film 20 is deposited by sputtering, amorphous silicon film 21 is deposited by plasma CVD, and titanium nitride film 22 is deposited by sputtering (FIG. 2).
(A)).

Next, an inverted photoresist pattern 23 for forming a contact hole having an area smaller than that of the first metal wiring layer 14 is formed (FIG. 2B). Next, dry etching is performed using the connection hole forming inverted photoresist pattern 23 as a mask to form an antifuse 39 including the upper electrode 17, the antifuse layer 16 and the lower electrode 15 (FIG. 2).
(C)).

Next, in order to electrically insulate the first metal wiring layer 14, the lower electrode 15, the anti-fuse layer 16 and the upper electrode 17, a connection hole forming inversion photoresist pattern is formed at a height higher than that of the upper electrode 17. The inter-layer insulation film 18 is formed by a liquid phase epitaxy method with a film thickness of 23 or less (see FIG. 2).
(D)). Here, the liquid phase growth method of the insulating film has characteristics of low temperature treatment and selectivity. Therefore, it is possible to form an insulating film at a temperature not higher than the heat resistant temperature of the photoresist, and since the underlayer starts to grow from the insulating film due to the selectivity, the entire surface of the insulating substrate 13 should be formed with the same film thickness. You can

Next, the connection hole forming reverse resist pattern 23 is removed by ashing to form a connection hole 24 to expose the upper electrode 17 (FIG. 2 (e)). Next, an aluminum alloy is deposited on the upper electrode 17 and the interlayer insulating film 18 by a sputtering method, masked with a photoresist, and then dry-etched to form a second metal wiring layer 19 (FIG. 2 (f). )).

The antifuse element according to the first embodiment of the present invention is formed as described above. According to this embodiment, the area of the antifuse 39 composed of the lower electrode 15, the antifuse layer 16 and the upper electrode 17 is equal to the area of the connection hole 2.
4 has the same size as the cross-sectional area of the first metal wiring layer 14
Since it is smaller, it is possible to reduce the parasitic capacitance of the anti-fuse element which is not programmed.
Further, since the anti-fuse layer 16 is deposited before forming the connection hole 24, there is no variation in the film thickness of the anti-fuse layer 16 among the anti-fuse elements. Therefore, it is possible to eliminate the variation in the dielectric breakdown voltage during programming due to the variation in the film thickness of the anti-fuse layer 16, and it is possible to obtain good programming characteristics. further,
Since the liquid phase epitaxy method is used to form the interlayer insulating film 18, the film thickness of the interlayer insulating film 18 becomes constant over the entire surface of the substrate, and the normally required flattening step of the interlayer insulating film can be omitted. Therefore, the manufacturing process can be shortened. Can be planned.

FIG. 3 is a schematic sectional view of an antifuse element according to the second embodiment of the present invention. In FIG. 3, 25 is an insulating substrate, 26 is a first metal wiring layer made of an aluminum alloy, 27 is a lower electrode made of titanium nitride, 28 is an antifuse layer made of amorphous silicon, 29 is an upper electrode made of titanium nitride, Reference numeral 30 is an interlayer insulating film, and 31 is a second metal wiring layer made of an aluminum alloy.

The structure of the antifuse element according to the second embodiment of the present invention will be described below. In FIG. 3, the first metal wiring layer 26 and the second metal wiring layer 31
Are circuit elements of a semiconductor integrated circuit. Further, the first metal wiring layer 26 and the second metal wiring layer 31 were required for the lower electrode 27, the antifuse layer 28, the upper electrode 29 where the antifuse element was formed, and for the circuit design. In the area other than the contact area, insulation is provided by the interlayer insulating film 30. The upper electrode 29 has the same size as the connection hole, and the lower electrode 27 and the antifuse layer 28 have the connection hole 38.
Concentric with and similar in shape to the bottom of the connection hole 38 between the first metal wiring layer 26 and the second metal wiring layer 31, and insulating the first metal wiring layer 26 and the second metal wiring layer 31. ing.

In other words, this antifuse element has the first
Of the metal wiring layer 26 and the substantially contact hole 3 having a smaller area than the first metal wiring layer 26 laminated on the first metal wiring layer 26.
An antifuse 40 having a lower electrode 27 having a size of 8, an antifuse layer 28, and an upper electrode 29, and an outer peripheral edge of the upper electrode 29 receding inward from the outer peripheral edge of the antifuse layer 28; and a first metal wiring. An upper electrode 29 on the layer 26
An interlayer insulating film 30 in which a connection hole 38 is provided on the upper electrode 29 by opening and stacking, and a second metal wiring layer laminated on the interlayer insulating film 30, the connection hole 38, and the upper electrode 29. 31 and 31 are provided.

Here, the area of the upper electrode 29 is equal to the contact hole 38.
Since it has the same size as the cross-sectional area and is smaller than that of the first wiring layer 26, it is possible to reduce the parasitic capacitance of the anti-fuse element. In addition, although there is no problem in the antifuse element of the first embodiment, the structure in which the outer peripheral edge of the upper electrode 29 is recessed inward from the outer peripheral edge of the antifuse layer 28 causes a gap between the electrodes at the electrode edge portion. The creepage distance becomes large, and the problem of leakage in the antifuse 40 can be eliminated.

Next, a method of manufacturing the antifuse element according to the second embodiment of the present invention will be described. Figure 4 (a)
(G) is a process sectional view showing the manufacturing method of the second embodiment of the present invention, 25 is an insulating substrate, 26 is a first metal wiring layer made of an aluminum alloy, and 27 is a lower electrode made of titanium nitride. , 28 is an antifuse layer made of amorphous silicon, 29 is an upper electrode made of titanium nitride,
Reference numeral 30 is an interlayer insulating film, 31 is a second metal wiring layer made of an aluminum alloy, 32 and 34 are titanium nitride films, 33 is an amorphous silicon film, 35 is a reverse photoresist pattern for forming contact holes, 36 is a titanium nitride layer, Reference numeral 37 is an inverted photoresist pattern for forming a contact hole after isotropic etching, and 38 is a contact hole.

First, an aluminum alloy is deposited on the insulating substrate 25 by a sputtering method, masked with a photoresist and then dry-etched.
Of the metal wiring layer 26, a titanium nitride film 32 is deposited by sputtering, an amorphous silicon film 33 is deposited by plasma CVD, and a titanium nitride film 34 is deposited by sputtering (FIG. 4).
(A)).

Next, an inverted photoresist pattern 35 for forming connection holes is formed (FIG. 4B). Next, the first
Using the inverted photoresist pattern 35 for forming a contact hole having a smaller area than the metal wiring layer 26 as a mask, dry etching is performed to form a titanium nitride layer 36, an antifuse layer 28, and a lower electrode 27 (FIG. 4C).

Next, the photoresist is isotropically etched to form an inverted photoresist pattern 37 for forming a contact hole, and the titanium nitride layer 36 is used as a mask.
Is etched to form the upper electrode 29 (FIG. 4).
(D)). Next, the first metal wiring layer 26 and the lower electrode 2
7. In order to electrically insulate the antifuse layer 28 and the upper electrode 29, liquid phase epitaxy is used with a film thickness not less than the height of the upper electrode 29 and not more than the height of the inverted photoresist pattern 37 for forming connection holes. The interlayer insulating film 30 is formed (FIG. 4).
(E)).

Here, the liquid phase epitaxy method of the insulating film has characteristics of low temperature treatment and selectivity. Therefore, it is possible to form an insulating film at a temperature lower than the heat resistant temperature of the photoresist, and because the selectivity starts the growth of the base from the insulating film,
The entire surface of the insulating substrate 25 can be formed with the same thickness. Next, the connection hole forming inversion resist pattern 37 is removed by ashing to form a connection hole 38 to expose the upper electrode 29 (FIG. 4F).

Next, an aluminum alloy is deposited on the upper electrode 29 and the interlayer insulating film 30 by a sputtering method, masked with a photoresist and then dry-etched to form a second metal wiring layer 31 (FIG. 2 (g)). As described above, the antifuse element of the second embodiment of the present invention is formed.

According to this embodiment, since the upper electrode 29 has the same size as the sectional area of the connection hole 38, it is possible to reduce the parasitic capacitance of the anti-fuse element which is not programmed. Further, since the outer peripheral edge of the upper electrode 29 is recessed inward from the outer peripheral edge of the anti-fuse layer 28, the creeping distance between the electrodes at the edge portions of the upper electrode 29 and the lower electrode 27 becomes large, The problem of leakage in the fuse 40 can be eliminated. Further, since the anti-fuse layer 28 is deposited before forming the connection hole 38, there is no variation in the film thickness of the anti-fuse layer 28 for each anti-fuse element. Therefore, it is possible to eliminate the variation in the dielectric breakdown voltage at the time of programming due to the variation in the film thickness of the antifuse layer 28, and it is possible to obtain good programming characteristics. Further, since the liquid phase epitaxy method is used to form the interlayer insulating film 30, the thickness of the interlayer insulating film 30 is constant over the entire surface of the substrate, so that the normally required flattening step of the interlayer insulating film can be omitted, and the manufacturing process It can be shortened.

[0041]

According to the antifuse element of the first aspect of the present invention, the area of the lower electrode, the antifuse layer, and the upper electrode is the same as the cross-sectional area of the connection hole and smaller than the first metal wiring layer. It is possible to reduce the parasitic capacitance of the anti-fuse element. According to the method of manufacturing the antifuse element according to claim 2, the area of the antifuse composed of the lower electrode, the antifuse layer, and the upper electrode is as large as the cross-sectional area of the connection hole, and the first metal wiring layer is formed. Since it is smaller, it is possible to reduce the parasitic capacitance of the anti-fuse element which is not programmed. Further, since the anti-fuse layer is deposited before forming the connection hole, there is no variation in the thickness of the anti-fuse layer among the anti-fuse elements. Therefore, it is possible to eliminate the variation in the dielectric breakdown voltage during programming due to the variation in the thickness of the antifuse layer, and it is possible to obtain good programming characteristics.

According to the antifuse element of the third aspect, since the area of the upper electrode is the same as the cross-sectional area of the connection hole and smaller than that of the first metal wiring layer, the parasitic capacitance of the antifuse element is small. It is possible to Further, by adopting a structure in which the outer peripheral edge of the upper electrode is recessed inward from the outer peripheral edge of the antifuse layer, the creeping distance between the electrodes at the electrode edge portion becomes large, and the problem of leakage in the antifuse can be solved.

According to the method of manufacturing the antifuse element according to the fourth aspect, since the upper electrode has the same size as the cross-sectional area of the connection hole and is smaller than the first metal wiring layer, the antifuse element which is not programmed is not used. It is possible to reduce the parasitic capacitance of. Also, since the outer edge of the upper electrode is recessed inward from the outer edge of the anti-fuse layer, the creeping distance between the electrodes at the edge portions of the upper electrode and the lower electrode becomes large, and the leakage at the anti-fuse portion becomes large. The problem of can be solved. Further, since the anti-fuse layer is deposited before forming the connection hole, there is no variation in the thickness of the anti-fuse layer among the anti-fuse elements. Therefore, it is possible to eliminate the variation in the dielectric breakdown voltage during programming due to the variation in the thickness of the antifuse layer, and it is possible to obtain good programming characteristics.

According to the method of manufacturing an anti-fuse element of the fifth aspect, since the liquid phase growth method is used for forming the interlayer insulating film, the film thickness of the interlayer insulating film is constant over the entire surface of the substrate. Therefore, the step of planarizing the interlayer insulating film, which is usually necessary, can be omitted, and the manufacturing process can be shortened.

[Brief description of drawings]

FIG. 1 is a sectional view of an anti-fuse element that is a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view of the method of manufacturing the antifuse element according to the first embodiment of the present invention.

FIG. 3 is a sectional view of an antifuse element according to a second embodiment of the present invention.

FIG. 4 is a process sectional view of a method for manufacturing an antifuse element, which is a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a conventional antifuse element.

FIG. 6 is a process sectional view of a conventional method for manufacturing an anti-fuse element.

[Explanation of symbols]

1 Insulating Substrate 2 First Metal Wiring Layer 3 Lower Electrode 4 Anti-Fuse Layer 5 Upper Electrode 6 Interlayer Insulating Film 7 Second Metal Wiring Layer 8 Aluminum Alloy Film 9 Titanium Nitride Film 10 Anti-Fuse Insulating Film 11 Titanium Nitride Film 12 Connection Hole 13 Insulating Substrate 14 First Metal Wiring Layer 15 Lower Electrode 16 Anti-Fuse Layer 17 Upper Electrode 18 Interlayer Insulating Film 19 Second Metal Wiring Layer 20 Titanium Nitride Film 21 Amorphous Silicon Film 22 Titanium Nitride Film 23 Inversion for Connection Hole Formation Photoresist pattern 24 Connection hole 25 Insulating substrate 26 First metal wiring layer 27 Lower electrode 28 Antifuse layer 29 Upper electrode 30 Interlayer insulating film 31 Second metal wiring layer 32 Titanium nitride film 33 Amorphous silicon film 34 Titanium nitride film 35 Inverted photoresist pattern for connection hole formation 36 Nitriding Connection hole for reversing photo Tan layer 37 isotropically after etching resist pattern 38 connecting hole 39 antifuse 40 antifuse

Claims (5)

[Claims] 1. A first metal wiring layer, and a lower electrode, an antifuse layer, and an upper portion having a size of a connection hole which has a smaller area than that of the first metal wiring layer laminated on the first metal wiring layer. An antifuse made of an electrode; an interlayer insulating film having the connection hole formed on the upper electrode by opening and stacking the upper electrode on the first metal wiring layer; An anti-fuse element comprising an inner wall of a connection hole and a second metal wiring layer laminated over the upper electrode. 2. A step of depositing and patterning a conductive film to form a first metal wiring layer, a step of depositing a first conductor on the first metal wiring layer, and a step of depositing the first conductor on the first conductor. Depositing an anti-fuse insulator on the substrate, depositing a second conductor on the anti-fuse insulator, and
Of the conductor, the antifuse insulator, and the second conductor are etched using a photoresist as a mask to form a lower electrode, an antifuse layer, and an upper electrode having a contact hole size smaller than that of the first metal wiring layer. A step of forming, and a step of depositing an interlayer insulating film with a thickness such that the upper electrode is buried with respect to the lower electrode, the antifuse layer, the upper electrode, and the photoresist, and the photoresist is not buried. A step of exposing the upper electrode by forming the connection hole by removing the photoresist; depositing a conductive film on the interlayer insulating film, the inner wall of the connection hole and the upper electrode, and patterning the conductive film; And a step of forming a metal wiring layer of the above. 3. A first metal wiring layer, a lower electrode laminated on the first metal wiring layer and having an area smaller than that of the first metal wiring layer, and having a size of a contact hole and an antifuse layer. An antifuse comprising an upper electrode, the outer edge of the upper electrode being receded inward from the outer edge of the antifuse layer;
An interlayer insulating film having the connection hole formed on the upper electrode by opening and stacking the upper electrode on the first metal wiring layer, and the interlayer insulating film, the connection hole, and the upper electrode. An anti-fuse element having a second metal wiring layer laminated over the same. 4. A step of depositing and patterning a conductive film to form a first metal wiring layer, a step of depositing a first conductor on the first metal wiring layer, and a step of depositing a first conductor on the first conductor. Depositing an anti-fuse insulator on the substrate, depositing a second conductor on the anti-fuse insulator, and
Of the conductor, the antifuse insulator, and the second conductor are etched by using a photoresist as a mask, and the lower electrode, the antifuse layer, and the upper electrode are smaller in size than the first metal wiring layer and have a size of a connection hole. A step of forming an isotropic etching of the photoresist, a step of etching an upper electrode using the isotropically etched photoresist as a mask, the etched upper electrode, the antifuse layer and the lower portion. A step of depositing an interlayer insulating film in such a thickness that the upper electrode is buried in the electrode and the photoresist and the photoresist is not buried; and the connection hole is provided by removing the photoresist to form the upper electrode. Exposing the interlayer insulating film, depositing a conductive film on the inner wall of the connection hole, and on the upper electrode. Method for manufacturing antifuse element and a step of forming a second metal interconnection layer is grayed. 5. The method for manufacturing an antifuse element according to claim 2, wherein the interlayer insulating film is deposited by liquid phase growth.