JPH10112505A - Programmable element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the deterioration and the dispersion of insulation destruction resistance and to improve quality in an electrically programmable element which is incorporated in a semiconductor integrated circuit device. SOLUTION: A face excluding the program area 16 of an insulating film for a program 14, and at least the insulating film for program 14, a lower electrode 13 and the side part of a lower wiring 12 are coated with a thin- interlayer insulating film 15, so as to be formed. A thick-interlayer insulating film 18 is formed between an oxide layer 11 and an upper wiring 19, by containing the peripheral part of an upper electrode 17 which is provided on the upper face of the thin-interlayer insulating film 15 that is connected to the face of the program area 16 in the insulating film for the program 14 and covers the upper peripheral part of the insulating film for the program 14. Thus, the absolute amount of over-etching added to the insulating film for the program 14 is reduced, and the dispersion is reduced. Then, the deterioration and the dispersion of the insulating destruction resistance of the insulating film for the program 14 can by suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically programmable device incorporated in a semiconductor integrated circuit device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the development period of electronic equipment, whether industrial or consumer use, has exceeded the product life time, and products have been required to be multifunctional and diversified. There is an urgent need to shorten the period until manufacturing and reduce manufacturing costs. Therefore, even in the semiconductor device manufacturing industry, as a prototype of a gate array or its substitute, an FPGA (Fiel
d-Programmable Gate Array) has been used.
There are two main types of FPGA programming methods, a memory method and an anti-fuse method. From the viewpoint of speeding up and increasing the integration of the FPGA, the anti-fuse method using an anti-fuse as a program element is expected to be promising. An anti-fuse is a high-resistance element, which is usually changed to a low-resistance state by an electrical programming signal, thereby connecting a basic logic element on a chip and wiring to enable writing at a design or manufacturing site. This is to enable the user's circuit to be realized on site.

In a semiconductor integrated circuit device, a so-called PROM (Programmable ROM) in which contents can be electrically written after a user purchases them is a ROM having desired contents.
(Read Only Memory) is widely used because it can be obtained immediately.

In the field of logic circuits, a so-called PLD (Programmable Logic Device), which is also capable of electrically writing contents after purchase by a user, is used for a similar purpose. In order to configure a PROM or PLD, stored contents can be electrically written from outside,
In addition, it is necessary to use a programmable element that can retain the stored contents even when the power is turned off.

FIG. 4 is a cross-sectional view showing the structure of a conventional programmable element, in which a thick oxide layer 1 on a semiconductor substrate 9 is formed.
A lower wiring 2, a lower electrode 3, and a program insulating film 4 patterned in a desired size in contact with the upper surface of the substrate are sequentially laminated. The lower wiring 2, the lower electrode 3, and the program insulating film 4 are covered with a thick interlayer insulating film 5, but a portion of the upper surface of the program insulating film 4 where the thick interlayer insulating film 5 is not formed, That is, an area 6 to be programmed is provided, and an upper electrode 7 and an upper wiring 8 are formed by sequentially laminating the area 6 to be programmed.

In programming, a voltage of about 10 V is applied between the upper electrode 7 and the lower electrode 3 to break the insulation of the insulating film 4 for programming, thereby making the upper electrode 7 and the lower electrode 3 electrically conductive. This is done by:

FIG. 5 shows a conventional method of manufacturing a programmable element. First, as shown in FIG. 5A, an aluminum alloy film 2a and a titanium nitride film are formed on a thick oxide layer 1 on a semiconductor substrate 9. The film 3a is deposited by a sputtering method, and then the amorphous silicon film 4a is
It is formed by sequentially laminating by the method D.

Next, as shown in FIG. 5B, an amorphous silicon film 4a and a titanium nitride film 3 are formed by using a conventional photolithography technique and a dry etching technique.
a, the aluminum alloy film 2a is simultaneously patterned,
The insulating film for program 4, the lower electrode 3, and the lower wiring 2 are formed.

Next, as shown in FIG. 5C, after forming a thick insulating film, the surface thereof is flattened to form a thick interlayer insulating film 5.
Is provided.

Next, as shown in FIG. 5D, a desired portion of the thick interlayer insulating film 5 located on the upper surface of the program insulating film 4 is formed by using a photolithography technique, a wet etching technique and a dry etching technique. The region to be programmed by etching
(Referred to as a program area) 6.

Next, as shown in FIG. 5E, a titanium nitride film and an aluminum alloy film are sequentially laminated by a sputtering method, and then patterned into desired dimensions using a photolithography technique and a dry etching technique. The upper electrode 7 and the upper wiring 8 are formed.

[0012]

However, in the above-mentioned conventional structure, the program region 6 is formed by opening the thick interlayer insulating film 5, and therefore, after the thick interlayer insulating film 5 is etched and the program region 6 is opened. Due to the overetching, the program insulating film 4 located immediately below becomes thinner or damaged, resulting in a problem that the dielectric breakdown voltage of the program insulating film 4 is reduced, and variations in characteristics are increased. I was Also,
Since the program region 6 is formed by opening the thick interlayer insulating film 5, the aspect ratio of the opening of the program region 6 is increased, the coverage of the upper electrode 7 is reduced, and after the programming insulating film 4 is programmed. There is also a problem that the reliability in the conductive state is deteriorated.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a higher quality programmable element which can suppress the deterioration of the electrical characteristics of a program insulating film.

[0014]

In order to achieve the above object, a programmable element according to the present invention is provided on a lower wiring disposed on an oxide layer formed on a semiconductor substrate and on an upper surface of the lower wiring. A lower electrode, a program insulating film formed on the lower electrode, an upper electrode formed on the upper surface of the program insulating film, and an upper wiring disposed on the upper electrode. An element, which covers a lower electrode and a side surface of a lower wiring from a peripheral upper surface of the programming insulating film excluding a program region on the program insulating film, and has a two-layer structure between the upper surface of the oxide layer and the upper wiring. It has an interlayer insulating film consisting of a thin film, which can reduce the absolute amount of overetch applied to the program insulating film, reduce the variation in the amount of overetch, and cut off the program insulating film. It is possible to suppress the reduction and variation in breakdown voltage.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 is a method for manufacturing a semiconductor device, comprising: a lower wiring disposed on an oxide layer formed on a semiconductor substrate; a lower electrode provided on an upper surface of the lower wiring;
An insulating film for programming formed on the lower electrode;
A programmable element having an upper electrode formed on an upper surface of the program insulating film and an upper wiring disposed on the upper surface of the upper electrode, wherein the program insulating film excludes a program area of the program insulating film. The lower electrode from the peripheral upper surface, covering the side surface of the lower wiring, between the upper surface of the semiconductor substrate or the oxide layer and the upper wiring,
Since the semiconductor device includes an interlayer insulating film having a two-layer structure, deterioration of electrical characteristics of the program insulating film can be suppressed, and a higher quality programmable element can be obtained.

According to a second aspect of the present invention, the interlayer insulating film having a two-layer structure of the programmable element according to the first aspect is composed of a thin interlayer insulating film and a thick interlayer insulating film. Adopting a structure with an interlayer insulating film suppresses a decrease in breakdown voltage and an increase in variation of the insulating film for programming, and improves reliability in a conductive state after the insulation of the insulating film for programming is broken. Can be done.

According to a third aspect of the present invention, a lower wiring disposed on an oxide layer formed on a semiconductor substrate, a lower electrode provided on an upper surface of the lower wiring, A programmable element having a program insulating film formed thereon, an upper electrode formed on the upper surface of the program insulating film, and an upper wiring disposed on the upper electrode, and a thin interlayer insulating film. Covers the surface of the program insulating film excluding the program region and at least the side surfaces of the program insulating film, the lower electrode, and the lower wiring, and a thick interlayer insulating film covers the surface of the program insulating film in the program region. An oxide layer formed on a semiconductor substrate, including a peripheral portion of an upper electrode provided over the upper surface of a thin interlayer insulating film connected to and covering an upper peripheral portion of the program insulating film; It is formed between the line and the line, and can reduce the absolute amount of over-etch applied to the program insulating film, reduce the variation of the over-etch amount, and reduce the decrease and the variation of the dielectric breakdown voltage of the program insulating film. Can be suppressed.

According to a fourth aspect of the present invention, in the programmable element according to the second or third aspect, the thin interlayer insulating film has a thickness of 50 to 50 mm.
This thin film has a thickness of 500 nm, and this thin film thickness defines a region where a thin interlayer insulating film having a limited thickness works effectively. Can be suppressed, and the reliability of the program insulating film in a conductive state after the insulation of the insulating film is broken can be improved.

According to a fifth aspect of the present invention, a peripheral angle of a program insulating film in a three-layer structure comprising a lower wiring, a lower electrode, and a program insulating film of a programmable element according to the second, third or fourth aspect of the present invention. The cross-sectional shape of the thin interlayer insulating film at the portion where the portion and the three-layer structure are in contact with the oxide layer forms a curved surface, and the side walls of the thin interlayer insulating film are etched with titanium nitride as a constituent material of the upper electrode. It has the effect of not causing a residue.

According to a sixth aspect of the present invention, there is provided a method for forming an oxide layer on a semiconductor substrate, forming a lower wiring and a lower electrode on the oxide layer, and forming a program on the lower electrode. Forming a thin insulating film on at least the upper surface and side surfaces of the program insulating film and the side surfaces of the lower electrode and the lower wiring; and forming the thin insulating film on the program insulating film. Opening a desired portion of the thin interlayer insulating film to expose the surface of the program insulating film; and forming an upper electrode on the upper surface of the program insulating film in the opening of the thin interlayer insulating film. Forming a thick interlayer insulating film on the upper electrode; opening a desired portion of the thick interlayer insulating film to expose the surface of the upper electrode; Dew Forming an upper wiring on the upper surface portion of the upper electrode, thereby suppressing a decrease in breakdown voltage and an increase in variation of a dielectric breakdown voltage of the program insulating film, and after programming the program insulating film. Can be improved in the conductive state.

Hereinafter, an embodiment of the programmable element of the present invention will be described with reference to the sectional view of FIG.

In FIG. 1, reference numeral 10 denotes a semiconductor substrate, 11 denotes an oxide layer, 12 denotes a lower wiring, 13 denotes a lower electrode, 14 denotes a program insulating film, 15 denotes a thin interlayer insulating film, 16 denotes a program region, and 17 denotes an upper portion. Electrode, 18 is a thick interlayer insulating film,
19 is an upper wiring.

FIG. 2 is a plan view of the present embodiment, and FIG.
, 13 is a lower electrode, 16 is a program area, 1
7 is an upper electrode, 19 is an upper wiring, and 20 is an overlap margin.

The programming of the PLD is performed by the upper wiring 19.
A voltage of about 10 V is applied between the upper electrode 17 via the lower electrode 12 and the lower electrode 13 via the lower wiring 12 to break the insulation of the program insulating film 14 and
3 is made electrically conductive.

The operation of the programmable element configured as described above will be described below.

The programmable element of the present embodiment has a thin interlayer insulating film 15 having a thickness of about 200 nm, for example.
Is etched to open the program region 16, the amount of over-etching during etching is
The thickness can be reduced to about one tenth as compared with the case of an interlayer insulating film having a thickness of about 00 nm. Therefore, the amount of overetch applied to the program insulating film 14 can also be reduced to approximately one-tenth, and as a result, the thickness of the program insulating film 14 decreases and dielectric breakdown due to damage applied to the program insulating film 14 occurs. A decrease in withstand voltage can be suppressed. The film thickness to be etched when opening the program region 16 has a variation of, for example, ± 1.
0%, ± 20 n in the case of the thin interlayer insulating film 15
m, ± 200 nm in the case of the conventional thick interlayer insulating film 5. Therefore, the variation in the amount of overetch applied to the program insulating film 14 when the same amount of overetch is applied is also almost one tenth, and as a result, the variation in the dielectric breakdown voltage of the program insulating film 14 can be suppressed. It becomes possible.

Further, in the programmable element of the present embodiment, the upper electrode 17 is connected to the upper surface of the program insulating film Thin interlayer insulating film 1 covering the surface other than program area 16
5 has an effect that it can maintain a structure with a margin against dimensional variations of the lower electrode 13 and the upper electrode 17 and misalignment of the mask.

Next, an embodiment of a method of manufacturing a programmable element according to the present invention will be described with reference to the cross-sectional views in FIG.

In FIG. 3A, a thick oxide layer 11 formed on a semiconductor substrate 10 has a thickness of 500 to 100
Aluminum alloy layer 22 of about 0 nm, thickness of 200 to 3
A titanium nitride layer 23 having a thickness of about 00 nm is deposited by a sputtering method, and a composite film 24 of a silicon nitride film having a thickness of about 5 to 10 nm and an amorphous silicon film having a thickness of about 50 to 100 nm is sequentially laminated by a plasma CVD method. Form.

Next, as shown in FIG. 3B, a composite film 24 composed of a silicon nitride film and an amorphous silicon film, a titanium nitride layer 23, and an aluminum alloy layer 22 are simultaneously formed by photolithography and dry etching. Etching and programming insulating film 1
4. The lower electrode 13 and the lower wiring 12 are simultaneously patterned and formed.

Next, as shown in FIG.
After growing a thin interlayer insulating film 15 having a thickness of about 0 to 300 nm by a plasma CVD method using TEOS, corner portions of the thin interlayer insulating film 15 are smoothened by argon sputtering as shown by 15a and 15b in the figure. Make it a curved surface.
Then, a desired portion of the thin interlayer insulating film 15 located on the upper surface of the program insulating film 14 is etched using photolithography technology, wet etching technology, and dry etching technology to open the program region 16 so that the program region 16 is opened. A part of the upper surface of the insulating film 14 is exposed.

Next, as shown in FIG.
After depositing a titanium nitride layer of about 0 to 300 nm by a sputtering method, a desired pattern is formed by using a photolithography technique, and the titanium nitride layer is isotropically etched by a dry etching technique under a predetermined condition and time. To form an upper electrode 17. At this time, the outer surface 17a of the upper electrode 17 has a tapered shape in which the upper part is receded by about 0.2 to 0.3 μm, but almost no etch residue of titanium nitride is left on the side wall of the thin interlayer insulating film 15.

Next, as shown in FIG.
After an insulating film of about 00 to 2500 nm is grown by a plasma CVD method using TEOS, a thick interlayer insulating film 18 is formed by performing a planarization process. Then, an opening serving as a program region 16 is provided on the upper electrode 17 by using a photolithography technique and a dry etching technique.
Further, a programmable element is completed by forming an upper wiring 19 made of titanium and an aluminum alloy having a thickness of about 700 to 1000 nm.

[0034]

As described above, according to the present invention, the absolute amount of overetch applied to the program insulating film is reduced, and the variation of the overetch amount is reduced to reduce the dielectric breakdown voltage of the program insulating film and An increase in variation can be suppressed, and the reliability in a conductive state after the programming insulating film is programmed can be improved, so that a higher quality programmable element can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an embodiment of a programmable element of the present invention.

FIG. 2 is a plan view for explaining the embodiment.

FIGS. 3A to 3E are process cross-sectional views illustrating an embodiment of a method for manufacturing a programmable element according to the present invention.

FIG. 4 is a cross-sectional view of a conventional programmable element.

5 (a) to 5 (e) are sectional views showing steps of a conventional method for manufacturing a programmable element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Oxide layer 12 Lower wiring 13 Lower electrode 14 Program insulating film 15 Thin interlayer insulating film 16 Program area 17 Upper electrode 18 Thick interlayer insulating film 19 Upper wiring

 ──────────────────────────────────────────────────の Continuing from the front page (72) Hiroshi Yuasa, Inventor 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation

Claims (6)

[Claims] A lower wiring provided on an oxide layer formed on a semiconductor substrate; a lower electrode provided on an upper surface of the lower wiring; and a program electrode formed on the lower electrode. A programmable element having an insulating film, an upper electrode formed on an upper surface of the program insulating film, and an upper wiring disposed on the upper electrode, wherein a programmable region on the program insulating film is provided. And covering the lower electrode and the side surfaces of the lower wiring from the peripheral upper surface of the program insulating film except for the above, and having an interlayer insulating film having a two-layer structure between the upper surface of the semiconductor substrate or the oxide layer and the upper wiring. Programmable element. 2. The programmable element according to claim 1, wherein the interlayer insulating film having a two-layer structure is formed of two layers, a thin interlayer insulating film and a thick interlayer insulating film. 3. An oxide layer formed on a semiconductor substrate,
A lower wiring disposed on the oxide layer; a lower electrode provided on an upper surface of the lower wiring; a program insulating film formed on the lower electrode; and an upper surface of the program insulating film A programmable element having an upper electrode formed on the upper electrode and an upper wiring disposed on the upper surface of the upper electrode, wherein a thin interlayer insulating film is formed on a surface excluding a program region of the program insulating film and at least the program A thick interlayer insulating film connected to a surface of a program area of the program insulating film, and an upper peripheral portion of the program insulating film. A peripheral portion of the upper electrode provided over an upper surface of the thin interlayer insulating film covering the portion, and formed between the oxide layer on the semiconductor substrate and the upper wiring. And are programmable element. 4. A thin interlayer insulating film having a thickness of 50 to 500
4. The programmable element according to claim 2, wherein 5. A thin interlayer insulating film in a three-layer structure comprising a lower wiring, a lower electrode, and a program insulating film at a peripheral corner of the program insulating film and a portion where the three-layer structure contacts an oxide layer. 5. The programmable element according to claim 2, wherein the cross-sectional shape of the film forms a curved surface. 6. A step of forming an oxide layer on a semiconductor substrate, a step of forming a lower wiring and a lower electrode on the oxide layer, and a step of forming a program insulating film on the lower electrode. Forming a thin interlayer insulating film on at least an upper surface portion and a side surface portion of the program insulating film and a side surface portion of the lower electrode and the lower wiring; and forming a desired one of the thin interlayer insulating film on the program insulating film. Opening a portion to expose the surface of the program insulating film; forming an upper electrode on the upper surface of the program insulating film in the opening of the thin interlayer insulating film; Forming a thick interlayer insulating film, opening a desired portion of the thick interlayer insulating film to expose a surface of the upper electrode, and an upper surface of the upper electrode exposed at an opening of the thick interlayer insulating film Forming an upper wiring in a portion.