JP3432111B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an error correction function.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device, after simultaneously writing information data and parity data in a memory cell, the presence or absence of an error is checked by an operation using both the read information data and the parity data to perform an error check. If so, there is a device having an error correction function of correcting the error and outputting the information data in which the error is corrected (Japanese Patent Laid-Open No. Hei 5
-2898 publication).

FIG. 14 is a block diagram of a main part of a semiconductor memory device having an error correction function disclosed in the above-mentioned Japanese Patent Laid-Open No. 5-2898. In this semiconductor memory device, 32
At the same time as writing the input data signals DA0 to DA31 having a bit configuration to the memory cell array 102, a parity signal calculated by the parity creating circuit 101 based on the input data signal and the Hamming matrix is created, and the parity signal is created in the memory cell array 102. Write. The Hamming matrix used in the parity generation circuit 101 is an information bit.
The number of check bits (parity signal) to be added is determined by the number of bits of (input data signal).

Thus, when reading the input data signal stored in the memory cell array 102, the syndrome creating circuit 104 uses the read data signal and the read parity signal read from the memory cell array 102 by the sense circuit 103. A syndrome signal is created by an operation based on the Hamming matrix.
The syndrome signal is a signal group in which all are 0 if there is no error in the read data signal and the read parity signal, and if there is an error, an error pattern depending on the Hamming matrix appears in the syndrome signal. That is, when the syndrome signals are all 0 and there is no error, the read data signal is output as it is as a corrected output data signal, while when the syndrome signal has an error pattern, the correction signal generation circuit 105 causes an error in the syndrome signal. The pattern is converted into a correction signal indicating the error portion of the read data signal. Thus
The exclusive OR of the correction signal generated by the correction signal generation circuit 105 and the read data signal is calculated by the correction circuit 10
The error of the read data signal is corrected by the calculation by 6, and the corrected read data signal is output as the corrected output data signals D0 to D31.

[0005]

By the way, in the above-mentioned semiconductor memory device, its reliability is further required as the storage capacity increases due to the progress of integration. However, when the number of times of rewriting / reading increases, the value of the threshold voltage Vth (threshold voltage) of the transistor forming the memory cell changes with time due to stress leak caused by deterioration of the oxide film, and the reading is performed. Since the judgment of "1" or "0" of the data signal is erroneously read, reliability is lowered, and particularly in a flash memory or the like, the change with time of the threshold voltage Vth has a great influence.

In such a semiconductor memory device, data "1" read from the memory cell array 102,
The determination of "0" is made by, for example, the sense amplifier shown in FIG. In the sense amplifier, the read voltage vn from the memory cell is input to the input, the inverting amplifier including the transistors Q1 and Q2 to which the determination voltage Vd is input to the output, and the determination voltage Vd to the input and vn to the output. It has an inverting amplifier including the input transistors Q3 and Q4, and amplifies the potential difference between vn and the determination voltage Vd. Then, the voltage read from the memory cell is compared with vn (n = 1, 2, ...) And the judgment voltage Vd to make a judgment. At this time, as shown in FIG. 16, as a characteristic of the sense amplifier, there is a judgment dead region, and the voltage read from the memory cell is the judgment voltage V.
When the voltages v1 (= Vd + va) and v2 (= Vd-va) are very close to d, the voltage v1 may be erroneously determined to be "1" and the voltage v2 may be "0". With the voltages v3 and v4 read from a normal memory cell, the voltage difference between the determination voltage Vd and the voltages v3 and v4 is large, and it is possible to reliably determine the voltage v3 as “0” and the voltage v4 as “1”. The threshold voltage Vth of the above memory cell
Changes with time, a memory cell having a threshold voltage appears in the judgment dead region. Therefore, in the semiconductor memory device described above, when the threshold voltage Vth of the memory cell is in the judgment insensitive region, it is difficult to judge "0" or "1", so that the accuracy of error detection is low and the error correction is not performed. There is a problem that it cannot be done accurately.

Therefore, an object of the present invention is to provide a highly reliable semiconductor memory device capable of improving the accuracy of error detection of data read from a memory cell and performing accurate error correction.

[0008]

In order to achieve the above object, a semiconductor memory device according to a first aspect of the invention has a first bit of 2 bits or more.
A first inversion unit that inverts the logic of all bits of the data signal,
A first parity signal of 2 bits or more is generated based on the first data signal and a predetermined matrix, and the first parity signal is generated.
A parity creation unit that creates a second parity signal of 2 bits or more based on the second data signal from which the logic of all bits of the first data signal is inverted from the inversion unit and the predetermined matrix; A memory cell array storing one data signal, the first parity signal and the second parity signal, and read levels of all bits of the first data signal stored in the memory cell array are inverted with respect to a predetermined reference voltage. And a second inverting unit that outputs a third data signal in which the levels of all bits of the first data signal are inverted, respectively, the first data signal, the first parity signal, and the first data signal stored in the memory cell array. Second above
The parity signal is read out respectively, the first read data signal, the first read parity signal and the second read parity signal are output respectively, and the third data signal from the second inverting section is read out to obtain the second read data. A first syndrome signal is created based on the reading unit that outputs a signal, the first read data signal, the first read parity signal, and the predetermined matrix, and the second read data signal and the second read signal are also generated. A syndrome creating unit that creates a second syndrome signal based on the parity signal and the predetermined matrix, and the first and second syndrome signals from the syndrome creating unit, and the first and second syndrome signals are received. Whether or not they match is determined, and the first and second syndrome signals are used to determine the first and second syndrome signals. A syndrome determination unit that determines whether the read data signal or the first and second read parities is incorrect, and the syndrome determination unit matches the first and second syndrome signals, and
An error correction unit that corrects an error in the first read data signal based on the first syndrome signal and the predetermined matrix when it is determined that the first and second read data signals are erroneous Is characterized by.

According to the semiconductor memory device of claim 1,
The parity creating unit creates a parity signal of 2 bits or more based on the first data signal of 2 bits or more and the predetermined matrix. That is, the first parity signal for correcting one error of the first data signal is created by, for example, a Hamming matrix composed of a code for correcting one random error. Similarly, a second parity signal of 2 bits or more is created based on the second data signal in which the logic of all bits of the first data signal is inverted by the first inverting unit and the predetermined matrix. Then, the first data signal, the first parity signal, and the second parity signal are stored in the memory cell array. Next, the reading unit reads the first data signal, the first parity signal, and the second parity signal stored in the memory cell array. The second inverting section inverts the read levels of all bits of the first data signal stored in the memory cell array with respect to a predetermined reference voltage. At this time, the predetermined reference voltage is set to "0",
By setting the determination voltage to determine “1”, the read level of all bits from the second inversion unit is inverted by the third voltage.
When the data signal is read by the read unit, the second read data in which the logic of all the bits of the first read data is inverted is obtained (the threshold voltage of the transistor forming the memory cell is near the judgment voltage of the read unit, that is, the judgment insensitivity). When not a region). Then, based on the first read data signal and the first read parity signal read by the read unit and a predetermined matrix, the syndrome creating unit represents the first syndrome indicating whether or not there is an error in the first read data signal. Create a signal. The second read data signal read by the read unit and the second read data signal
Based on the read parity signal and the predetermined matrix, the syndrome creating unit creates a second syndrome signal indicating whether or not there is an error in the second read data signal. If the syndrome determination unit determines that the first and second syndrome signals match and that the first and second read data signals or the first and second read parities are incorrect, the syndrome is determined to be the first syndrome. Based on the matrix of
The error correction unit corrects an error in the first read data signal. On the other hand, the above-mentioned syndrome determination unit has the first and second
If it is determined that the syndrome signals do not match, it is determined that the threshold voltage of the transistor of one of the memory cells read by the reading unit is in the determination dead region of the reading unit. Perform processing such as stopping.

Therefore, the first read data signal read from the memory cell array and the second read data signal whose read level is inverted are erroneous using the first parity signal and the second parity and a predetermined matrix. By performing the inspection, the accuracy of the error inspection of the data read from the memory cell can be improved, the accurate error correction can be performed based on the inspection result, and the reliability can be improved.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, wherein the first inverting section is an inverter.

According to the semiconductor memory device of claim 2,
Even if the number of bits forming the first data signal is large, the first inversion unit can be easily formed by an inverter, so that the cost can be reduced.

According to a third aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the second inversion unit sets read levels of all bits of the first data signal stored in the memory cell array. A / D for A / D conversion
An (analog / digital) converter, an arithmetic unit for inverting the read level of each bit of the first data signal A / D converted by the A / D converter by arithmetic operation with respect to the predetermined reference voltage, and D that outputs the third data signal in which the read levels of all bits of the first data signal are inverted based on the calculation result of the calculation unit D
It has a / A (digital / analog) converter.

According to the semiconductor memory device of the third aspect,
The read levels of all bits of the first data signal stored in the memory cell array are respectively A / D converted by an A / D converter, and the A / D converted read levels are then set by the arithmetic unit to the predetermined reference voltage. Flip each against. For example, if the reference voltage is 3V in the voltage range of 0V to 6V, the read level of the memory cell is 1V.
If so, 5V (= 6-1) is calculated, and if 5V, 1V (= 6-5) is calculated. Then, the third data signal obtained by the calculation of the calculation unit and having all bits of the first data signal stored in the memory cell array inverted is output.

Therefore, it is not necessary to configure an analog operation circuit using an inverting amplifier or the like for each bit of the first data signal stored in the memory cell array, and the second inverting section can be realized with a simple configuration.

A semiconductor memory device according to a fourth aspect is the semiconductor memory device according to the first aspect, wherein a Hamming matrix is used as the predetermined matrix.

According to the semiconductor memory device of the fourth aspect,
By using the Hamming matrix having the error correction capability of detecting and correcting one random error, the parity creating unit, the syndrome creating unit, and the correction signal generating unit for performing error detection and correction are particularly easily configured. it can.

A semiconductor memory device according to a fifth aspect is the semiconductor memory device according to the first aspect, wherein the memory cell array is a memory cell array of an EEPROM (electrically erasable and writable read-only memory). .

According to the semiconductor memory device of the fifth aspect,
In the case where the memory cell array is electrically rewritable, for example, a flash memory, when the number of times of rewriting increases, the threshold voltage of the transistor forming the memory cell changes due to deterioration of the oxide film and the read data has an incorrect value. Becomes By applying the present invention to such a nonvolatile semiconductor memory device, it is particularly effective to improve its reliability.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor memory device of the present invention will be described in detail below with reference to the embodiments shown in the drawings.

FIG. 1 is a block diagram of essential parts of a semiconductor memory device according to an embodiment of the present invention. This semiconductor memory device is an electrically erasable and writable EEPROM.

In FIG. 1, reference numeral 1 is a second bit which receives the input data signals DA0 to DA31 having a 32-bit structure, inverts the logic of all bits of the input data signals DA0 to DA31, and inverts the logic of all bits. A first inverting circuit as a first inverting unit that outputs a logically inverted data signal as a data signal, and 2 are the input data signals DA0 to DA31 and the first inverting circuit.
Receiving the inverted data signals DB0 to DB31 from the inverting circuit 1, the parity signals PA0 to PA5 as the 6-bit first parity signals and the inverted parity signals PB0 to PB5 as the second parity signals are given a predetermined Hamming matrix H. (Fig. 3 (A)
The parity creating circuit as a parity creating unit created in accordance with the above), 3 is the input data signals DA0 to DA31,
Parity signals PA0 to PA5 and inverted parity signal PB
0 to PB5 are stored in the memory cell array 4, and 4 are input data signals MDA0 to MDA stored in the memory cell array 3.
The second inversion circuit 5 serving as a second inversion unit which inverts the read level of all the bits of DA31 and outputs a level-inverted data signal as the third data signal in which the read levels of all the bits are inverted, 5 is the memory cell array Input data signals DA0 to DA31 and parity signals PA0 to
The read data signals MDA0 to MDA31 as the first read data signals, the read parity signals MPA0 to MPA5 as the first read parity signals, and the read inversion as the second read parity signals are read by reading PA5 and the inverted parity signals PB0 to PB5, respectively. The parity signals MPB0 to MPB5 are output respectively, and the second signal
Read the level inversion data signal from the inversion circuit 4,
It is a sense circuit as a read unit that outputs read inverted data signals MDB0 to MDB31 as a second read data signal.

Reference numeral 6 is the read data signal MDA.
0 to MDA31 and read parity signals MPA0 to MPA5
Based on the Hamming matrix H, the first syndrome signals SA0 to SA5 are created and output, and the Hamming matrix H based on the read inverted data signals MDB0 to MDB31 and the read inverted parity signals MPB0 to MPB5. According to the second syndrome signal SB0
˜SB5 is created and output as a syndrome creating circuit as a syndrome creating section, and 7 receives the first syndrome signals SA0 to SA5 and the second syndrome signals SB0 to SB5 from the syndrome creating circuit 7 and receives the first syndrome. Signals SA0 to SA5 and second syndrome signal SB
A syndrome determining circuit as a syndrome determining unit for determining 0 to SB5, 8 is a correction signal generating circuit for generating correction signals E0 to E31 based on the determination result of the syndrome determining circuit 7, and 9 is the correction signal generating circuit. A correction circuit that corrects the error of the read data signals MDA0 to MDA31 read from the memory cell array 3 by the sense circuit 5 based on the correction signals E0 to E31 from 8 and outputs corrected output data D0 to D31. is there. The correction signal generation circuit 8 and the correction circuit 9 form an error correction unit.

FIG. 2 shows a circuit diagram of the first inverting circuit 1. The first inverting circuit 1 has an input data signal DA0.
... DA31 are input to the input terminals of the inverters 10, 10, ..., respectively, and the inverted data signals DB0 to DB31 are output from the output terminals of the inverters 10, 10, ..., respectively.

FIG. 4 shows a circuit diagram of the parity generation circuit 2. The parity generation circuit 2 connects the output terminal of an exclusive OR circuit (hereinafter, referred to as XOR) 21 to which input data signals DA10 and DA11 are input to the input terminals to one input terminal of the XOR 23, and to input the input data. X when signals DA12 and DA15 are input to the input terminals respectively
The output terminal of OR22 is connected to the other input terminal of XOR23. In addition, the input data signals DA16, DA17
X to the output terminals of the XOR24 input to the input terminals respectively.
XOR which is connected to one input terminal of OR26 and input data signals DA18 and DA21 are respectively input to the input terminals
The output terminal of 25 is connected to the other input terminal of the XOR 26. The output terminal of the XOR23 is connected to the XOR2
7, and the output terminal of the XOR 26 is connected to the other input terminal of the XOR 27.
Further, the output terminal of the XOR21, to which the input data signals DA22 and DA23 are respectively inputted to the input terminals, is connected to one input terminal of the XOR23, and the input data signal DA2 is inputted.
4, DA26 is connected to the other input terminal of the XOR23 by connecting the output terminal of the XOR22 whose input terminals are input. Also, the output terminal of the XOR 20A, to which the input data signals DA27 and DA28 are respectively input, is connected to one input terminal of the XOR 20B, and the input data signal DA
31 is input to the other input terminal of the XOR 20B. The output terminal of XOR23 is connected to one input terminal of XOR28, and the output terminal of XOR20B is connected to XOR2.
8 is connected to the other input terminal. And the above XO
The output terminal of R27 is connected to one input terminal of XOR29, and the output terminal of XOR28 is connected to the other input terminal of XOR29.
Output A0. That is, XOR21 to XOR29, X
The circuit configured by OR20A and XOR20B performs the exclusive OR operation of the following equation. PA0 = DA10 + DA11 + DA12 + DA15 + DA16 + DA17 + DA18 + DA21 + DA22 + DA23 + DA24 + DA26 + DA27 + DA28 + DA31 (mod2) The above formula is based on addition modulo 2.

The parity creating circuit 2 includes the XORs 21 to 21.
The remaining parity signals PA1 to PA5 are generated and output by a circuit (not shown) similar to the circuit configured by XOR29, XOR20A and XOR20B. Thus
The parity creation circuit 2 creates the parity shown in FIG. 3 (B) and, in the same manner, inverts the parity signal PB0.
~ Create and output PB5.

FIG. 5 shows the syndrome creating circuit 6 described above.
The circuit diagram of is shown. The syndrome creation circuit 6
Connects the output terminal of the XOR 61 to which the read data signals MDA10 and MDA11 are input to the input terminals to one input terminal of the XOR 63, and the XOR to which the read data signals MDA12 and MDA15 are input to the input terminals, respectively.
The output terminal of 62 is connected to the other input terminal of the XOR 63. Further, the read data signals MDA16, MD
A17 connects the output terminal of the XOR64 input to the input terminal to one input terminal of the XOR66, and the output terminal of the XOR65 input the read data signals MDA18 and MDA21 to the other input terminal of the XOR66. Connected to. Then, while connecting the output terminal of the XOR 63 to one input terminal of the XOR 67,
The output terminal of the XOR 66 is connected to the other input terminal of the XOR 67. In addition, the read data signal MDA2
2, the output terminal of the XOR 61 whose MDA 23 is input to each input terminal is connected to one input terminal of the XOR 63, and the output terminal of the XOR 62 whose read data signals MDA 24 and MDA 26 are input to the other input terminal of the XOR 63, respectively. It is connected to the input terminal. Further, the output terminal of the XOR 64, to which the read data signals MDA27 and MDA28 are respectively input, is connected to one input terminal of the XOR 66, and the read data signal MDA31 and the read parity signal MPA0 are input to the input terminals. The output terminal of the XOR 65 is connected to the other input terminal of the XOR 66. The output terminal of the XOR63 is XOR6.
7, and the output terminal of the XOR 66 is connected to the other input terminal of the XOR 67.
Then, the output terminal of the XOR 67 is connected to one input terminal of the XOR 68, the output terminal of the XOR 67 is connected to the other input terminal of the XOR 68, and the first syndrome signal SA0 is output from the XOR 68. That is,
The circuit configured by XOR61 to XOR68 performs the exclusive OR operation of the following equation. SA0 = MDA10 + MDA11 + MDA12 + MDA15 + MDA16 + MDA17 + MDA18 + MDA21 + MDA22 + MDA23 + MDA24 + MDA26 + MDA27 + MDA28 + MDA31 + PA0 (mod2) The above formula is based on addition modulo 2.

The syndrome creating circuit 6 is an XOR6.
1 to XOR68, the remaining first syndrome signals SA1 to SA are generated by the same circuit (not shown).
Create and output 5. In this way, the syndrome creating circuit 6 creates the syndrome shown in FIG. 6, and similarly creates and outputs the second syndrome signals SB0 to SB5.

FIG. 7 shows the syndrome determination circuit 7 described above.
The circuit diagram of is shown. The syndrome determination circuit 7
Connects the output terminal of the XOR71 to which the first syndrome signal SA0 and the second syndrome signal SB0 are input to the input terminals to one input terminal of the XOR73, and the first syndrome signal SA1 and the second syndrome signal SB1.
The output terminals of the XOR72 input to the input terminals respectively
It is connected to the other input terminal of the OR73. In addition, the first syndrome signal SA2 and the second syndrome signal SB
The output terminal of the XOR 71 having 2 input to the input terminals is connected to one input terminal of the XOR 73, and the output terminals of the XOR 72 having the first syndrome signal SA3 and the second syndrome signal SB3 input to the input terminals are XORed.
It is connected to the other input terminal of 73. In addition, the output terminal of the XOR 71 to which the first syndrome signal SA4 and the second syndrome signal SB4 are input to the input terminals is connected to the XOR7.
3 is connected to one of the input terminals, and the output terminal of the XOR 72 to which the first syndrome signal SA5 and the second syndrome signal SB5 are input to the input terminals is connected to the other input terminal of the XOR 73. And each XOR7 above
The output terminal of 3 is an exclusive NOR circuit (hereinafter, XNOR
That is, the output signal C is output from the XNOR 74.

FIG. 8 shows a circuit diagram of the correction signal generating circuit 8. In the correction signal generation circuit 8, the output terminal of a NAND circuit (hereinafter referred to as NAND) 81 to which the syndrome signals / SA0, / SA1, / SA2 whose logic is inverted by an inverter (not shown) is input is a NOR circuit. A syndrome signal / SA3 and a syndrome signal SA, which are connected to one input terminal of 83 (hereinafter referred to as NOR) and whose logic is inverted by an inverter (not shown).
NOR output terminal of NAND82 to which 4, SA5 is input
It is connected to the other input terminal of 83. NOR83 above
Then, the correction signal E0 is output. In addition, a syndrome signal / SA0 whose logic is inverted by an inverter (not shown),
The output terminal of the NAND 81 to which / SA1 and / SA2 are input is connected to one input terminal of the NOR 83, and the syndrome signal / SA4 and the syndrome signals SA3 and SA5 whose logic is inverted by an inverter (not shown) are input to the NAND82. The output terminal is connected to the other input terminal of the NOR 83. A correction signal E1 is output from the NOR 83.

The correction signal generating circuit 8 is a NAND 8
The remaining correction signals E2 to E31 are output by a circuit (not shown) similar to the circuit composed of 1, 82 and NOR 83. Thus, the correction signal generation circuit 8 generates correction signals E0 to E31 based on the first syndrome signals SA0 to SA5 and the Hamming matrix H.

FIG. 9 shows a circuit diagram of the correction circuit 9. The correction circuit 9 includes the correction signal generation circuit 8
The correction signal E0 from XOR90 is input to one input terminal of the XOR90, the read data signal MDA0 from the sense circuit 5 is input to the other input terminal of XOR90, and the corrected output data signal D0 is output from XOR90. Further, the correction signal E1 from the correction signal generating circuit 8 is
Is input to one input terminal of the XOR 90, and the read data signal MDA1 from the sense circuit 5 is input to the XO.
It is input to the other input terminal of R90 and the corrected output data signal D1 is output from XOR90. Further, the correction signal E2 from the correction signal generation circuit 8 is input to one input terminal of the XOR 90, and the read data signal MDA2 from the sense circuit 5 is input to the other input terminal of the XOR 90. The corrected output data signal D2 is output from the XOR 90. In the same manner, the correction circuit 9 outputs the corrected output data signals D3 to D31.

FIG. 10 shows a block diagram of the main part of the second inverting circuit 4. The second inverting circuit 4 includes an A / D converter 41 for A / D converting read levels of all bits of the data signal from the memory cell array 3,
Level-inverted data by D / A converting the subtraction circuit 42 that performs an operation according to the digital data representing the level of each data signal converted by the A / D converter 41 and the digital data representing the operation result of the subtraction circuit 42. It has a D / A converter 43 for outputting signals respectively.

In the semiconductor memory device having the above structure, when the input data signals DA0 to DA31 are stored in the memory cell array 3, parity signals PA0 to PA5 used for error correction are stored.
Is created by the parity creation circuit 2. The parity creation circuit 2 uses the Hamming matrix H shown in FIG. 3A to generate the parity parts PA0 to PA5 and the inverted parity part PB0.
~ Create PB5. In the Hamming matrix H shown in FIG. 3A, the number of check bits (parity) added is determined by the number of information bits (input data). In this embodiment, the number of information bits is 32 bits. However, the check bit number is 6 bits. As shown in FIG. 3 (B), the parity generation circuit 2 follows the Hamming matrix H according to the value (“1”, ”) of each row of the Hamming matrix H.
0 ") and the input data signals DA0 to DA31 are respectively calculated as a product of mod2 (shown by" * "in FIG. 3 (B)) and a sum of mod2 (shown by" + "in FIG. 3 (B)). As a result, 6-bit parity signals PA0 to PA5 are obtained.

The input data signals DA0 to DA31 are also provided.
Is converted into inverted data signals DB0 to DB31 in which the logic of all bits is inverted by the first inversion circuit 1 and the converted inverted data signals DB0 to DB31 are input to the parity generation circuit 2. That is, as shown in FIG. 2, the first inverting circuit 1 causes the inverter 10 to convert all the bits of the input data signals DA0 to DA31 to the logic of "1" and "0" in reverse. For example, as the input data signals DA0 to DA31
When 00110010 ---- "is converted by the first inverting circuit 1, the inverted data signals DB0 to DB31 become" 1100 ".
1101 ---- ”. The above parity signals PA0 to PA5
In the same manner as the calculation of, the parity creation circuit 2 creates the inverted parity signals PB0 to PB5 according to the inverted data signals DB0 to DB31 and the Hamming matrix H. Thereafter, as shown in FIG. 12, the memory cell array 3 stores information of 44 bits / 1 data having a structure of input data signals DA0 to DA31, parity signals PA0 to PA5 and inverted parity signals PB0 to PB5.

FIG. 11 is a diagram for explaining the inversion of the read level of the information stored in the memory cell in the second inversion circuit 4. In FIG. 11, the read voltage v
Reference numerals 1 and v2 respectively represent voltages read from the transistors forming the memory cell, which are inverted with respect to the determination voltage Vd. That is, (Vd + (Vd-v1)) and (Vd + (V
d-v2)) is calculated. In the second inverting circuit 4, the A / D converter 41, the arithmetic circuit 42 and the D / A
Using the converter 43, (2Vd-v1) and (2Vd-v1)
v2) is calculated to obtain a level-inverted data signal whose read level is inverted with respect to the judgment voltage Vd.

Next, when reading the information stored in the memory cell array 3, the sense circuit 5 first reads from the memory cell in which the input data signals DA0 to DA31 are stored and outputs the read data signals MDA0 to MDA31. Then, the parity signals PA0 to PA5 are read from the memory cells in which they are stored, and the read parity signals MPA0 to M are read.
PA5 is output and the inverted parity signals PB0 to PB are output.
5 is read from the memory cell in which it is stored, and read inverted parity signals MPB0 to MPB5 are output. The second inversion circuit 4 receives the level inversion data signal in which the read level of the memory cell is inverted with respect to the read determination voltage Vd, and the sense circuit 5 outputs the read inversion data signals MDB0 to MDB31. The read determination voltage Vd is a reference voltage for comparing the threshold voltages of the constituent transistors of the memory cell to be read by the sense circuit 5, and the read voltage is higher or lower than the read determination voltage. The stored information "0" or "1" is determined by whether or not.

Then, the read data signal MDA is obtained.
0 to MDA31, read parity signals MPA0 to MPA5,
The read inverted data signals MDB0 to MDB31 and the read inverted parity signals PB0 to PB5 are input to the syndrome creating circuit 6. The syndrome creating circuit 6 configures one data by the read data signals MDA0 to MDA31 and the read parity signals MPA0 to MPA5,
As shown in FIG. 3B, the calculation according to the Hamming matrix H is performed. The values of the horizontal rows of the Hamming matrix H and the data composed of the read data signals MDA0 to MDA31 and the read parity signals MPA0 to MPA5 are mod2.
The first syndromes SA0 to SA5 are obtained by calculating the product of and the sum of mod2. Similarly, the syndrome generation circuit 6 uses the read inverted data signals MDB0 to MDB31.
And second from read inverted parity signals MPB0 to MPB5
Syndrome signals SB0 to SB5 are obtained.

The first syndrome signals SA0 to SA5 and the second syndrome signals SB0 to SB5 created by the syndrome creating circuit 6 are compared by the syndrome determining circuit 7 shown in FIG. In the syndrome determination circuit 7, the XOR 71, 72, 73 and the NOR 74
If the first syndrome signals SA0 to SA5 and the second syndrome signals SB0 to SB5 do not match after the exclusive OR for comparing the values of the first syndrome signals SA0 to SA5 and the second syndrome signals SB0 to SB5 is taken. , "0" appears in the output signal C.

The first syndrome signals SA0 to SA5 and the second syndrome signals SB0 to SB5 respectively created by the syndrome creating circuit 6 have the following four possibilities (1) to (4). (1) When the first and second syndrome signals indicate no error (when both the first and second syndrome signals are all “0”) (2) Both the first and second syndrome signals indicate that there is an error, If the values match (3) If the first and second syndrome signals both indicate an error, and if the values do not match (4) If only one of the first and second syndrome signals indicates an error Output signal C of NOR 74 of the syndrome determination circuit 7
Becomes "1" in the case of (1) and (2), and becomes "0" in the case of (3) and (4). When the output signal C is "0", the syndrome determination circuit 7 outputs an error signal (shown in FIG. 1) to notify the memory abnormality to the outside and stop the reading.

On the other hand, NO of the syndrome judgment circuit 7
When the output signal C of R74 is "1", there is a double error check result, no error or an error that can be corrected, and error correction is performed as follows. That is, the read data signals MDA0 to MDA31 and the read parity signal M
Syndrome signal SA0 created from PA0 to MPA5
.About.SA5 generate the correction signals E0 to E31 by the correction signal generating circuit 6 shown in FIG.

The input of the correction signal generation circuit 8 shown in FIG.
This corresponds to the Hamming matrix H shown in FIG. That is, the first syndromes SA0 to SA5 corresponding to the configuration of each column in the vertical direction of the Hamming matrix H of FIG. 3A is input, and for example, in the correction signal E0, the first column from the left side of the Hamming matrix H is the first column. The first syndrome signal / S at "000011"
A0, / SA1, / SA2, / SA3, SA4, SA5 are input. Thereafter, similarly, the first syndromes SA0 to SA5 whose logic is inverted / non-inverted so as to correspond to the configuration of each column of the Hamming matrix H are input, and the correction signals E0 to E31 are created. When the value of the correction signals E0 to E31 is "1" corresponds to the erroneous bit and the first syndrome signals SA0 to SA5 are all "0" and there is no error,
Both correction signals become "0".

Then, the correction signal E0 ...
By calculating the exclusive OR of E31 and the read data signals MDA0 to MDA31, the corrected output data signals D0 to D31 in which the error has been corrected are output. That is, if the correction signal Ex = 0 (x = 0 to 31) has no error, the read data signal MDAx (x = 0 to 31) is output as it is and the correction signal Ex = 1 (x = 0 to 31). If there is an error in 31),
The logic of the read data signal MDAx (x = 0 to 31) is inverted and output.

Next, error correction of the semiconductor memory device will be described.

Now, as the input data signals DA0 to DA31, (0,0,0,0,0, ..., 0) is written to the memory cell array 3, and at the same time, the parity signals PA0 to PA5 and the inverted parity PB0 to PB5 are written.

At the time of reading, the threshold voltage Vth of the bit in which this data is recorded is Vth (v00) = 3.1 [V] Vth (v01) = 3.1 [V] Vth (v02) = 6. .0 [V] Vth (v03) = 6.0 [V] Vth (v04) = 6.0 [V] ... When Vth (v31) = 6.0 [V], the thresholds of the voltages v00, v01 Value voltage Vth is 3.1
It is close to [V] and the judgment voltage Vd (= 3.0 [V]) and is in the judgment dead zone.

Therefore, if the data is erroneously read,
There are three mistakes. When v00, v01 is read incorrectly (1,1,0,0,0, ..., 0) When v01 is read incorrectly (0,1,0,0,0, ..., 0) If v00 is erroneously read (1,0,0,0,0, ..., 0), it is impossible to correct the error because it is a 2-bit error, but if ,, Since it is a 1-bit error, error correction is possible. Which of the two cases, that is, is affected by the ability of the transistor that configures each sense amplifier, so that the memory cell in which the threshold voltage Vd is in the judgment insensitive region can be specified as it is. Can not.

In the above semiconductor memory device, data (0,0,
When writing 0,0,0, ..., 0), data (0,0,
Inverted data obtained by inverting all the logic of 0,0,0, ..., 0)
Using (1, 1, 1, ..., 1), the inverted parity signal PB0
.About.PB5 are stored in the memory cell array 3 together with normal parities PA0 to PA5. Then, for each of the read patterns ,,, as the value read by the sense circuit 5 via the second inverting circuit 4, the following (i)
~ (Iv) is possible. (i) (0,0,1,1,1, ..., 1) (ii) (0,1,1,1,1,1, ..., 1) (iii) (1,0,1,1,1,1, ..., 1) (iv) (1,1,1,1,1,1, ..., 1) This is the voltage v00, v01 passed through the second inverting circuit 4.
Read level (v00 = 3.1 [V], v01 = 3.1
[V]) inverted level (v00 = 2.9 [V], v0 =
2.1 [V]), and the sense circuit 5 determines the memory information “0” and “1” at the inverted level, so the read voltage in the determination dead zone is twice (at different levels). I will check it. Conventionally, the level of memory information "0"
In the case of the judgment of the threshold voltage in the judgment dead zone in (v00 = 3.1 [V]), the read level was inverted with respect to the judgment voltage Vd, whereas the error check was performed by reading once. Since the inverted read level is sensed and the error is checked, the level of the stored information "1" can be checked (v00 = 2.9 [V]).
That is, by checking the two types of data values, the state of the threshold voltage Vth is known, and when the read value of the bit in the judgment insensitive area is the same in the two kinds of read data, it is clearly in the judgment insensitive area. I know there is.

From the above, when the results of the two types of checks are different, it means that the data contained here contains a bit having a threshold voltage in the judgment insensitive area, and this is an error. Can be removed by the syndrome verification circuit 7, and the reliability can be further improved.

Therefore, the inspection result by the conventional method,
By constantly inspecting the threshold voltage Vth in a region that is difficult to determine based on both the inspection result of the value read as converted data and the inverted data, the accuracy of error detection can be improved, accurate error correction can be performed, and reliability can be improved. It is possible to realize a high-performance semiconductor memory device.

Further, even if the number of bits forming the input data signal is large, the first inverter circuit 1 and the inverter 10 are connected.
The cost can be reduced because the configuration is simple.

The second inverting circuit 4 includes an A / D converter 41, an arithmetic circuit 42 and a D / A converter 43.
Therefore, it is not necessary to configure an analog arithmetic circuit using an inverting amplifier or the like for each bit of the input data signals DA0 to DA31 stored in the memory cell array 3,
The second inverting circuit 4 can be realized with a simple configuration.

Further, by using the Hamming matrix H having the error correction capability of detecting and correcting one random error, the parity creation circuit 2, the syndrome creation circuit 6 and the correction signal generation for performing the error detection and correction. The circuit 8 can be constructed in a particularly simple manner.

The semiconductor memory device is an electrically erasable and writable EEPROM, and as the number of times of rewriting increases, the threshold voltage of the transistor forming the memory cell changes due to deterioration of the oxide film, Although error occurs in the read data, the reliability can be particularly improved by applying the present invention.

In the above embodiment, the semiconductor memory device for storing the input data signals DA0 to DA31 of 32-bit structure as the first data signal has been described, but the bit structure of the first data signal is not limited to this. Of course.

Further, in the above embodiment, the second inverting circuit 4 is composed of the A / D converter 41, the arithmetic circuit 42 and the D / A converter 43.
You may comprise with an analog circuit.

Further, in the above-mentioned embodiment, the EEPROM is explained as the non-volatile semiconductor memory device, but the present invention is not limited to this semiconductor memory device, and the present invention is applied to any memory regardless of volatile / non-volatile. May be.

[0058]

As is apparent from the above, in the semiconductor memory device according to the first aspect of the invention, the parity creating unit is configured to have the parity of 2 bits or more based on the first data signal of 2 bits or more and the predetermined matrix. A second signal in which the logic of all bits of the first data signal is inverted by the first inverting unit while the signal is created.
A second parity signal of 2 bits or more is created based on the data signal and the predetermined matrix, and the first data signal, the first parity signal and the second parity signal are stored in the memory cell array, and then the second parity signal is stored. The reading unit reads the first data signal, the first parity signal, and the second parity signal stored in the memory cell array, and the second inverting unit sets the read level of all bits of the first data signal stored in the memory cell array to a predetermined level. The third data signal inverted with respect to each reference voltage is read as the second read data signal by the read unit, and the first read data signal and the first read parity signal read by the read unit are formed into a predetermined matrix. On the basis of the first syndrome, the syndrome creating unit indicates whether the first read data signal has an error. And the presence / absence of an error in the second read data signal by the syndrome creating unit based on the second read data signal and the second read parity signal read by the read unit and a predetermined matrix. When the second syndrome signal is created and the syndrome determination unit determines that the bits of the first and second syndrome signals match and that the first and second read data signals are incorrect, the first syndrome And the first matrix by the error correction unit based on the predetermined matrix
The error in the read data signal is corrected.

Therefore, according to the semiconductor memory device of the present invention, the first read data signal read from the memory cell array and the second read data signal whose read level is inverted from the memory cell array are: By performing an error check using the first parity signal and the second parity and a predetermined matrix, the accuracy of the error check of the data read from the memory cell can be improved, and an accurate error correction can be performed based on the check result. It is possible to realize a highly reliable semiconductor memory device.

The semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the first inverting unit is an inverter, so that the number of bits forming the first data signal is at most. The first reversing unit can be easily configured and the cost can be reduced.

A semiconductor memory device according to a third aspect of the present invention is the semiconductor memory device according to the first aspect, wherein all of the first data signals stored in the memory cell array by the second inverting section A / D converter. A / D conversion is performed for each bit read level and A / D conversion is performed by the A / D converter.
The read level of each bit of the converted first data signal is inverted by the arithmetic unit with respect to the predetermined reference voltage, and the read level of all bits of the first data signal is based on the arithmetic result of the arithmetic unit. Since the D / A converter outputs the inverted third data signal, it is not necessary to configure an analog operation circuit using an inverting amplifier or the like for each bit of the first data signal stored in the memory cell array. The 2-inversion unit can be easily configured.

Further, in the semiconductor memory device of the present invention as defined in claim 4, in the semiconductor memory device according to claim 1, since the Hamming matrix is used as the predetermined matrix, the parity generation section for performing error detection and correction. Therefore, the syndrome creating unit and the error correcting unit can be constructed particularly easily.

The semiconductor memory device according to a fifth aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the memory cell array is an EEPROM memory cell array, but if the number of rewrites increases, the oxide film deteriorates. Even if the threshold voltage of the transistor forming the memory cell changes and an error occurs in the read data, the error can be accurately corrected and the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a first inverting circuit of the semiconductor memory device.

FIG. 3A is a diagram showing a Hamming matrix used in the parity generation circuit of the semiconductor memory device.
(B) is a diagram showing a determinant for creating a parity.

FIG. 4 is a circuit diagram of a parity generation circuit of the semiconductor memory device.

FIG. 5 is a circuit diagram of a syndrome creating circuit of the semiconductor memory device.

FIG. 6 is a diagram showing a determinant for creating a syndrome of the semiconductor memory device.

FIG. 7 is a circuit diagram of a syndrome determination circuit of the semiconductor memory device.

FIG. 8 is a circuit diagram of a correction signal generation circuit of the semiconductor memory device.

FIG. 9 is a circuit diagram of a correction circuit of the semiconductor memory device.

FIG. 10 is a circuit diagram of a second inverting circuit of the semiconductor memory device.

FIG. 11 is a diagram for explaining the operation of the second inverting circuit of the semiconductor memory device.

FIG. 12 is a diagram showing a structure of data stored in a memory cell array of the semiconductor memory device.

FIG. 13 is a truth table of a product of mod2 and a sum of mod2.

FIG. 14 is a block diagram of a main part of a conventional semiconductor memory device.

FIG. 15 is a circuit diagram of a main part of a sense amplifier of the semiconductor memory device.

FIG. 16 is a diagram illustrating a determination dead region of a sense amplifier of the semiconductor memory device.

[Explanation of symbols]

1 ... the first inverting circuit, 2 ... parity creation circuit, 3 ... Memory cell array, 4 ... the second inverting circuit, 5 ... Sense circuit, 6 ... Syndrome creation circuit, 7. Syndrome judgment circuit, 8 ... Correction signal generation circuit, 9 ... Correction circuit.

Claims (5)

(57) [Claims] 1. A first inversion unit for inverting the logic of all bits of a first data signal of 2 bits or more, and a first parity signal of 2 bits or more based on the first data signal and a predetermined matrix. Create the above first
A parity creation unit that creates a second parity signal of 2 bits or more based on the second data signal from which the logic of all bits of the first data signal is inverted from the inversion unit and the predetermined matrix; A memory cell array for storing one data signal, the first parity signal, and the second parity signal; and read levels of all bits of the first data signal stored in the memory cell array are inverted with respect to a predetermined reference voltage. And a second inversion unit that outputs a third data signal in which the levels of all bits of the first data signal are inverted, respectively, the first data signal, the first parity signal, and the first data signal stored in the memory cell array. The second parity signal is read out, and the first read data signal, the first read parity signal and the second read parity signal are output respectively. In addition, based on the read unit that reads the third data signal from the second inversion unit and outputs the second read data signal, the first read data signal, the first read parity signal, and the predetermined matrix. A first syndrome signal, and a syndrome creating unit that creates a second syndrome signal based on the second read data signal, the second read parity signal, and the predetermined matrix, and from the syndrome creating unit, Of the first and second syndrome signals, it is determined whether the first and second syndrome signals match, and the first and second read data signals are generated by the first and second syndrome signals. Alternatively, a syndrome determination unit for determining whether or not the first and second read parities are incorrect, and the syndrome If the determination unit determines that the first and second syndrome signals match and that the first and second read data signals are incorrect, the first and second syndrome signals and the predetermined matrix are used to determine the first and second read signals. 1. A semiconductor memory device comprising: an error correction unit that corrects an error of a read data signal. 2. The semiconductor memory device according to claim 1, wherein the first inversion unit is an inverter. 3. The semiconductor memory device according to claim 1, wherein the second inversion unit A / D-converts read levels of all bits of the first data signal stored in the memory cell array.
D converter, and the first A / D converted by the A / D converter
An operation unit that inverts the read level for each bit of the data signal by operation with respect to the predetermined reference voltage, and the read level of all bits of the first data signal is inverted based on the operation result of the operation unit. And a D / A converter that outputs the second data signal. 4. The semiconductor memory device according to claim 1, wherein a Hamming matrix is used as the predetermined matrix. 5. The semiconductor memory device according to claim 1, wherein the memory cell array is an EEPROM memory cell array.