JPH1116389A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high reliability semiconductor memory device which enables the improvement of the precision of error detection of data read out of a memory cell and the proper error correction. SOLUTION: Reverse parity signals which are generated by a parity generating circuit 2 in accordance with logic reverse data signals from a 1st reverse circuit 1 and a Hamming matrix are stored in a memory cell array 3 with input data signals DA0-DA31 and parity signals. The reading levels of all the bits of the input data signals DA0-DA31 stored in the memory cell array 3 are respectively reversed in relations to the judging voltage of a sensing circuit 5 by a 2nd reverse circuit 4. If a syndrome judgement circuit 7 judges that 1st and 2nd syndrome signals generated by a syndrome generating circuit 6 agree with each other and, further, there are errors in reading data signals and reading reverse data signals, a correction circuit 9 corrects the errors in the reading data signals D0-D31 in accordance with correction signals from a correction signal generating circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having an error correction function.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device, after writing parity data together with information data into a memory cell at the same time, the presence or absence of an error is checked by calculation using both the read information data and the parity data. If there is an error correction function, an error correction function for correcting the error and outputting the information data in which the error has been corrected is disclosed (Japanese Patent Laid-Open Publication No.
-2898).

FIG. 14 is a block diagram of a main part of a semiconductor memory device having an error correction function disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-2898. In this semiconductor memory device, 32
At the same time as writing the bit-structured input data signals DA0 to DA31 to the memory cell array 102, the parity creation circuit 101 creates a parity signal calculated based on the input data signal and the Hamming matrix, and sends the parity signal to the memory cell array 102. Write. The Hamming matrix used in the parity generation circuit 101 is an information bit
The number of bits of the check bit (parity signal) added is determined by the number of bits of the (input data signal).

When the input data signal stored in the memory cell array 102 is read, the syndrome generation circuit 104 uses the read data signal and the read parity signal read from the memory cell array 102 by the sense circuit 103. A syndrome signal is created by an operation based on the Hamming matrix.
The syndrome signal is a group of signals that are all 0 if there is no error between the read data signal and the read parity signal. If there is an error, an error pattern depending on the Hamming matrix appears in the syndrome signal. That is, when the syndrome signal is all zero and there is no error, the read data signal is output as it is as a corrected output data signal, while when the syndrome signal has an error pattern, the error signal of the syndrome signal is output by the correction signal generation circuit 105. The pattern is converted into a correction signal indicating an error portion of the read data signal. Thus,
The exclusive OR of the correction signal generated by the correction signal generation circuit 105 and the read data signal is calculated by the correction circuit 10.
6 to correct the error of the read data signal, and output the corrected read data signal as corrected output data signals D0 to D31.

[0005]

By the way, in the above-mentioned semiconductor memory device, as the integration is advanced and the storage capacity is increased, the reliability is more demanded. However, when the number of times of rewriting / reading increases, the value of the threshold voltage Vth (threshold voltage) of the transistor constituting the memory cell changes with time due to stress leak or the like caused by the deterioration of the oxide film, and the reading is performed. Since the determination of "1" or "0" of the data signal is erroneously read, the reliability is reduced. Particularly, in a flash memory or the like, the influence of the temporal change of the threshold voltage Vth is large.

In such a semiconductor memory device, data "1", "1",
The determination of “0” is made by, for example, the sense amplifier shown in FIG. The sense amplifier has an inverting amplifier composed of transistors Q1 and Q2 each having a read voltage vn input from a memory cell as an input and a determination voltage Vd as an output, a determination voltage Vd as an input, and a vn as an output. It has an inverting amplifier made up of transistors Q3 and Q4, and amplifies the potential difference between vn and the judgment voltage Vd. Then, the determination is performed by comparing the voltage read from the memory cell with vn (n = 1, 2,...) And the determination voltage Vd. At this time, as shown in FIG. 16, as a characteristic of the sense amplifier, a determination insensitive region exists, and the voltage read from the memory cell is equal to the determination voltage V.
In the case of voltages v1 (= Vd + va) and v2 (= Vd-va) which are very close to d, there is a possibility that the voltage v1 is erroneously determined as "1" and the voltage v2 is determined as "0". With the voltages v3 and v4 read from the normal memory cells, the voltage difference between the determination voltage Vd and the voltages v3 and v4 is large, and the voltage v3 can be reliably determined as "0" and the voltage v4 as "1". The threshold voltage Vth of the above memory cell
Changes over time, a memory cell having a threshold voltage appears in the insensitive region. Therefore, in the above-described semiconductor memory device, when the threshold voltage Vth of the memory cell is in the determination insensitive region, it is difficult to determine “0” or “1”. There is a problem that it cannot be done accurately.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor memory device capable of improving the accuracy of error detection of data read from a memory cell and performing accurate error correction.

[0008]

In order to achieve the above object, a semiconductor memory device according to the first aspect of the present invention has a first memory device of 2 bits or more.
A first inverting unit that inverts the logic of all bits of the data signal;
A first parity signal of 2 bits or more is created based on the first data signal and a predetermined matrix, and the first parity signal is generated.
A parity creation unit that creates a second parity signal of 2 bits or more based on the second data signal obtained by inverting the logic of all bits of the first data signal from the inversion unit and the predetermined matrix; A memory cell array for storing one data signal, the first parity signal and the second parity signal, and inverting read levels of all bits of the first data signal stored in the memory cell array with respect to a predetermined reference voltage; A second inverting unit that outputs a third data signal in which the levels of all bits of the first data signal are respectively inverted, the first data signal, the first parity signal, and the first data signal stored in the memory cell array; The second
The first read data signal, the first read parity signal, and the second read parity signal are respectively read out from the parity signal, and the third data signal from the second inverting section is read out. A reading unit for outputting a signal, a first syndrome signal based on the first read data signal, the first read parity signal, and the predetermined matrix, and a second read data signal and a second read signal; A syndrome creation unit for creating a second syndrome signal based on the parity signal and the predetermined matrix, and receiving the first and second syndrome signals from the syndrome creation unit, the first and second syndrome signals are received. It is determined whether or not they match, and the first and second syndrome signals are used in accordance with the first and second syndrome signals. A syndrome determination unit that determines whether the read data signal or the first and second read parities are erroneous, and the syndrome determination unit matches the first and second syndrome signals, and
An error correction unit for correcting an error in the first read data signal based on the first syndrome signal and the predetermined matrix when it is determined that the first and second read data signals are incorrect; It is characterized by.

According to the semiconductor memory device of the first aspect,
The parity creating unit creates a parity signal of 2 bits or more based on the first data signal of 2 bits or more and the predetermined matrix. That is, a first parity signal for correcting one error of the first data signal is created by, for example, a Hamming matrix composed of a code for correcting one random error. Similarly, a second parity signal of 2 bits or more is created based on the second data signal in which the logic of all bits of the first data signal is inverted by the first inverting unit and the predetermined matrix. Then, the first data signal, the first parity signal, and the second parity signal are stored in the memory cell array. Next, the first data signal, the first parity signal, and the second parity signal stored in the memory cell array are read by the reading unit. The second inverting unit inverts the read level of all bits of the first data signal stored in the memory cell array with respect to a predetermined reference voltage. At this time, the predetermined reference voltage is set to “0”,
By setting the determination voltage to determine “1”, the third bit in which the read levels of all the bits from the second inversion unit are inverted.
When the data signal is read by the read unit, second read data in which the logic of all bits of the first read data is inverted is obtained (the threshold voltage of the transistor forming the memory cell is close to the determination voltage of the read unit, that is, the determination is insensitive. When it is not an area). Then, based on the first read data signal, the first read parity signal, and the predetermined matrix read by the read unit, the first syndrome indicating presence / absence of an error in the first read data signal by the syndrome creating unit. Create a signal. Further, the second read data signal read by the read section and the second read data signal
Based on the read parity signal and a predetermined matrix, the syndrome creation unit creates a second syndrome signal indicating whether or not there is an error in the second read data signal. When the syndrome determination unit determines that the first and second syndrome signals match and the first and second read data signals or the first and second read parities are incorrect, the first syndrome is determined to be a predetermined one. Based on the matrix of
The error of the first read data signal is corrected by the error correction unit. On the other hand, the syndrome determination unit determines whether the first
If it is determined that the syndrome signals do not match, it is determined that the threshold voltage of any of the transistors of the memory cell read by the reading unit is in the determination insensitive region of the reading unit. And the like to stop the process.

Therefore, the first read data signal read from the memory cell array and the second read data signal whose read level is inverted are erroneous using the first parity signal and the second parity and a predetermined matrix. By performing the inspection, the accuracy of the error inspection of the data read from the memory cell can be improved, the error can be accurately corrected based on the inspection result, and the reliability can be improved.

Further, a semiconductor memory device according to a second aspect is characterized in that, in the semiconductor memory device according to the first aspect, the first inverting unit is an inverter.

According to the semiconductor memory device of the second aspect,
Even if the number of bits configuring the first data signal is large, the first inverting unit can be simply configured by an inverter, so that the cost can be reduced.

According to a third aspect of the present invention, in the semiconductor memory device of the first aspect, the second inverting unit sets a read level of all bits of the first data signal stored in the memory cell array. A / D for A / D conversion
An (Analog / Digital) converter, an arithmetic unit for inverting a read level of each bit of the first data signal A / D converted by the A / D converter with respect to the predetermined reference voltage, and D that outputs the third data signal in which the read levels of all bits of the first data signal are inverted based on the operation result of the operation unit
/ A (digital / analog) converter.

According to the semiconductor memory device of the third aspect,
After the read levels of all the bits of the first data signal stored in the memory cell array are A / D converted by the A / D converter, the read level obtained by the A / D conversion is calculated by the arithmetic unit to the predetermined reference voltage. , Respectively. For example, if the reference voltage is 3 V in a voltage range from 0 V to 6 V, the read level of the memory cell is 1 V
If so, 5V (= 6-1) is calculated, and if it is 5V, 1V (= 6-5) is calculated. Then, a third data signal in which all bits of the first data signal stored in the memory cell array obtained by the operation of the operation unit are inverted is output.

Therefore, it is not necessary to configure an analog operation circuit using an inverting amplifier or the like for each bit of the first data signal stored in the memory cell array, and the second inverting unit can be realized with a simple configuration.

According to a fourth aspect of the present invention, in the semiconductor storage device of the first aspect, a Hamming matrix is used as the predetermined matrix.

According to the semiconductor memory device of the fourth aspect,
By using the Hamming matrix having the error correction capability of detecting and correcting one random error, the parity creation section, syndrome creation section, and correction signal generation section for performing error detection and correction are particularly simply configured. it can.

According to a fifth aspect of the present invention, in the semiconductor memory device of the first aspect, the memory cell array is a memory cell array of an EEPROM (electrically erasable and writable read only memory). .

According to the semiconductor memory device of the fifth aspect,
In the case where the memory cell array is an electrically rewritable flash memory, for example, when the number of times of rewriting increases, the threshold voltage of the transistor constituting the memory cell changes due to deterioration of an oxide film or the like, and the read data has an incorrect value. Becomes By applying the present invention to such a nonvolatile semiconductor memory device, it is particularly effective to improve its reliability.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to the illustrated embodiments.

FIG. 1 is a main block diagram of a semiconductor memory device according to an embodiment of the present invention. This semiconductor storage device is an electrically erasable and writable EEPROM.

In FIG. 1, reference numeral 1 denotes a second bit which receives input data signals DA0 to DA31 having a 32-bit configuration, inverts the logic of all bits of the input data signals DA0 to DA31, and inverts the logic of all bits. The first inverting circuit 2 as a first inverting unit that outputs a logically inverted data signal as a data signal includes the input data signals DA0 to DA31 and the first
Receiving the inverted data signals DB0 to DB31 from the inverting circuit 1, a 6-bit parity signal PA0 to PA5 as a first parity signal and inverted parity signals PB0 to PB5 as a second parity signal are converted into a predetermined Hamming matrix H. (Fig. 3 (A)
), A parity creation circuit as a parity creation unit created in accordance with the input data signals DA0 to DA31,
Parity signals PA0 to PA5 and inverted parity signal PB
0 to PB5 are stored in the memory cell array 3, and the input data signals MDA0 to MDA stored in the memory cell array 3 are stored in the memory cell array 4.
A second inverting circuit as a second inverting unit for inverting the read level of all bits of DA31 and outputting a level-inverted data signal as a third data signal in which the read levels of all bits are inverted, 5 is the memory cell array 3, the input data signals DA0 to DA31 and the parity signals PA0 to PA3.
PA5 and inverted parity signals PB0 to PB5 are read, respectively, and read data signals MDA0 to MDA31 as first read data signals, read parity signals MPA0 to MPA5 as first read parity signals, and read inversion as second read parity signals. The parity signals MPB0 to MPB5 are respectively output and the second
Read the level inversion data signal from the inversion circuit 4 and
This is a sense circuit as a read unit that outputs read inverted data signals MDB0 to MDB31 as second read data signals.

Reference numeral 6 denotes the read data signal MDA.
0 to MDA31 and read parity signals MPA0 to MPA5
And generates and outputs the first syndrome signals SA0 to SA5 according to the Hamming matrix H, and the Hamming matrix H based on the read inverted data signals MDB0 to MDB31 and the read inverted parity signals MPB0 to MPB5. According to the second syndrome signal SB0
To SB5 for generating and outputting the syndromes. The syndrome generation circuit 7 receives the first syndrome signals SA0 to SA5 and the second syndrome signals SB0 to SB5 from the syndrome generation circuit 7 and receives the first syndrome. The signals SA0 to SA5 and the second syndrome signal SB
A syndrome determination circuit as a syndrome determination unit for determining 0 to SB5, a correction signal generation circuit 8 for generating correction signals E0 to E31 based on the determination result of the syndrome determination circuit 7, and a correction signal generation circuit 9 A correction circuit that corrects errors in the read data signals MDA0 to MDA31 read from the memory cell array 3 by the sense circuit 5 based on the correction signals E0 to E31 from the memory 8 and outputs corrected output data D0 to D31. is there. The correction signal generator 8 and the correction circuit 9 constitute an error correction unit.

FIG. 2 is a circuit diagram of the first inverting circuit 1. The first inverting circuit 1 receives the input data signal DA0
To DA31 are input to the input terminals of the inverters 10, 10,..., Respectively, and inverted data signals DB0 to DB31 are output from the output terminals of the inverters 10, 10,.

FIG. 4 is a circuit diagram of the parity generation circuit 2. The parity creation circuit 2 connects an output terminal of an exclusive OR circuit (hereinafter, referred to as XOR) 21 to which input data signals DA10 and DA11 are respectively input to input terminals to one input terminal of an XOR 23, and X when signals DA12 and DA15 are input to input terminals, respectively.
The output terminal of OR22 is connected to the other input terminal of XOR23. Further, the input data signals DA16, DA17
Are connected to the output terminals of the XOR 24 input to the input terminals, respectively.
The XOR is connected to one input terminal of the OR 26 and the input data signals DA18 and DA21 are respectively input to the input terminals.
25 output terminals are connected to the other input terminal of the XOR 26. The output terminal of the XOR 23 is XOR2
7, and the output terminal of the XOR 26 is connected to the other input terminal of the XOR 27.
Further, the output terminal of the XOR 21 to which the input data signals DA22 and DA23 are respectively input to the input terminals is connected to one input terminal of the XOR 23, and the input data signal DA2
4, the DA26 connects the output terminal of the XOR 22 input to the input terminal to the other input terminal of the XOR 23; The output terminal of the XOR 20A to which the input data signals DA27 and DA28 are input to the input terminals is connected to one input terminal of the XOR 20B, and the input data signal DA
31 is input to the other input terminal of the XOR 20B. The output terminal of the XOR 23 is connected to one input terminal of the XOR 28, and the output terminal of the XOR 20B is connected to the XOR 2
8 is connected to the other input terminal. And the XO
The output terminal of R27 is connected to one input terminal of XOR29, and the output terminal of XOR28 is connected to the other input terminal of XOR29.
A0 is output. That is, XOR21 to XOR29, X
The exclusive OR operation of the following equation is performed by the circuit composed of the OR 20A and the XOR 20B. PA0 = DA10 + DA11 + DA12 + DA15 + DA16 + DA17 + DA18 + DA21 + DA22 + DA23 + DA24 + DA26 + DA27 + DA28 + DA31 (mod2) Note that the above equation is an addition modulo 2.

The parity creation circuit 2 has XORs 21 to
The remaining parity signals PA1 to PA5 are created and output by a circuit (not shown) similar to the circuit composed of XOR29, XOR20A and XOR20B. Thus,
The parity creation circuit 2 creates the parity shown in FIG. 3 (B), and in the same manner, the inverted parity signal PB0
~ PB5 is created and output.

FIG. 5 shows the syndrome creation circuit 6.
FIG. The above-mentioned syndrome creation circuit 6
Connects the output terminal of the XOR 61 to which the read data signals MDA10 and MDA11 are input to the input terminals to one input terminal of the XOR 63, and the XOR to which the read data signals MDA12 and MDA15 are input to the input terminals, respectively.
The output terminal 62 is connected to the other input terminal of the XOR 63. The read data signals MDA16, MD
A17 connects the output terminal of XOR64, which is input to each input terminal, to one input terminal of XOR66, and connects the output terminal of XOR65, to which read data signals MDA18, MDA21 are input to input terminals, to the other input terminal of XOR66. Connected to The output terminal of the XOR 63 is connected to one input terminal of the XOR 67,
The output terminal of the XOR 66 is connected to the other input terminal of the XOR 67. Further, the read data signal MDA2
2. The output terminal of the XOR 61 whose MDA 23 is input to the input terminal is connected to one input terminal of the XOR 63, and the output terminal of the XOR 62 whose read data signals MDA24 and MDA 26 are input to the input terminal is connected to the other terminal of the XOR 63. Connected to input terminal. The output terminal of the XOR 64 to which the read data signals MDA27 and MDA28 are input to the input terminals is connected to one input terminal of the XOR 66, and the read data signal MDA31 and the read parity signal MPA0 are input to the input terminals. The output terminal of the XOR 65 is connected to the other input terminal of the XOR 66. The output terminal of XOR63 is XOR6
7, and the output terminal of XOR 66 is connected to the other input terminal of XOR 67.
The output terminal of the XOR 67 is connected to one input terminal of the XOR 68, and the output terminal of the XOR 67 is connected to the other input terminal of the XOR 68, so that the XOR 68 outputs the first syndrome signal SA0. That is,
The exclusive OR operation of the following equation is performed by the circuit composed of XOR61 to XOR68. SA0 = MDA10 + MDA11 + MDA12 + MDA15 + MDA16 + MDA17 + MDA18 + MDA21 + MDA22 + MDA23 + MDA24 + MDA26 + MDA27 + MDA28 + MDA31 + PA0 (mod2) The above equation is based on addition modulo 2.

The syndrome creation circuit 6 has an XOR6
1 to XOR68 (not shown), the remaining first syndrome signals SA1 to SA1
Create and output 5. Thus, the syndrome creation circuit 6 creates the syndrome shown in FIG. 6 and similarly creates and outputs the second syndrome signals SB0 to SB5.

FIG. 7 shows the syndrome determination circuit 7.
FIG. The syndrome determination circuit 7
Connects the output terminal of the XOR 71, to which the first syndrome signal SA0 and the second syndrome signal SB0 are respectively input to the input terminal, to one input terminal of the XOR 73, and outputs the first syndrome signal SA1 and the second syndrome signal SB1.
Are connected to the output terminals of the XOR 72 input to the input terminals, respectively.
Connected to the other input terminal of OR73. Further, the first syndrome signal SA2 and the second syndrome signal SB
2 connects the output terminal of the XOR 71 input to the input terminal to one input terminal of the XOR 73, and connects the output terminal of the XOR 72 to the input terminal to which the first syndrome signal SA3 and the second syndrome signal SB3 are input, respectively.
73 is connected to the other input terminal. Further, the output terminal of the XOR 71, to which the first syndrome signal SA4 and the second syndrome signal SB4 are input to the input terminals, is connected to XOR7.
3, and the output terminal of the XOR 72, to which the first syndrome signal SA5 and the second syndrome signal SB5 are input to the input terminals, is connected to the other input terminal of the XOR 73. And each of the above XOR7
3 is connected to an exclusive NOR circuit (hereinafter referred to as XNOR).
) 74 to output an output signal C from the XNOR 74.

FIG. 8 is a circuit diagram of the correction signal generating circuit 8. The correction signal generating circuit 8 connects the output terminal of a NAND circuit (hereinafter, referred to as NAND) 81 to which the syndrome signals / SA0, / SA1, / SA2 whose logic is inverted by an inverter (not shown) is input to a NOR circuit. (Hereinafter referred to as NOR) 83 and a syndrome signal / SA3 and a syndrome signal SA whose logic is inverted by an inverter (not shown).
4. The output terminal of NAND 82 to which SA5 is input is NOR
83 is connected to the other input terminal. NOR83 above
The correction signal E0 is output. Further, the syndrome signal / SA0, whose logic is inverted by an inverter (not shown),
The output terminal of the NAND 81 to which / SA1 and / SA2 are input is connected to one input terminal of the NOR 83, and the syndrome signal / SA4 whose logic is inverted by an inverter (not shown) and the NAND 82 to which the syndrome signals SA3 and SA5 are input. The output terminal is connected to the other input terminal of the NOR 83. The NOR 83 outputs a correction signal E1.

The correction signal generating circuit 8 includes a NAND 8
The remaining correction signals E2 to E31 are output by a circuit (not shown) similar to the circuit composed of 1, 82 and NOR 83. Thus, the correction signal generation circuit 8 generates correction signals E0 to E31 based on the first syndrome signals SA0 to SA5 and the Hamming matrix H.

FIG. 9 is a circuit diagram of the correction circuit 9. The correction circuit 9 includes the correction signal generation circuit 8
Is input to one input terminal of the XOR 90, the read data signal MDA0 from the sense circuit 5 is input to the other input terminal of the XOR 90, and the corrected output data signal D0 is output from the XOR 90. The correction signal E1 from the correction signal generation circuit 8 is also used.
Is input to one input terminal of the XOR 90, and the read data signal MDA1 from the sense circuit 5 is input to the XOR 90.
It is input to the other input terminal of R90, and outputs a corrected output data signal D1 from XOR90. Further, the correction signal E2 from the correction signal generation circuit 8 is input to one input terminal of the XOR 90, and the read data signal MDA2 from the sense circuit 5 is input to the other input terminal of the XOR 90. The XOR 90 outputs a corrected output data signal D2. Hereinafter, similarly, the correction circuit 9 outputs corrected output data signals D3 to D31.

FIG. 10 is a block diagram of a main part of the second inverting circuit 4. As shown in FIG. The second inverting circuit 4 includes an A / D converter 41 for A / D converting the read level of all bits of the data signal from the memory cell array 3, respectively;
A subtraction circuit 42 for performing an operation in accordance with digital data representing the level of each data signal converted by the A / D converter 41; and D / A conversion of digital data representing the operation result of the subtraction circuit 42 to obtain level-inverted data And a D / A converter 43 for outputting signals.

In the semiconductor memory device having the above configuration, when input data signals DA0 to DA31 are stored in memory cell array 3, parity signals PA0 to PA5 used for error correction are stored.
Is generated by the parity generation circuit 2. The parity creation circuit 2 uses the Hamming matrix H shown in FIG. 3A to generate the parity parts PA0 to PA5 and the inverted parity part PB0.
Create PB5. In the Hamming matrix H shown in FIG. 3A, the number of bits of the check bits (parity) added is determined by the number of bits of the information bits (input data). In this embodiment, the number of information bits is 32 bits. The number of check bits is set to 6 bits. As shown in FIG. 3B, the parity creation circuit 2 calculates the value (“1”, ”) of each row of the Hamming matrix H according to the Hamming matrix H.
0 ") and the input data signals DA0 to DA31, respectively, to calculate the product of mod2 (indicated by" * "in FIG. 3B) and the sum of mod2 (indicated by" + "in FIG. 3B). Thus, 6-bit parity signals PA0 to PA5 are obtained.

The input data signals DA0 to DA31
Are converted into inverted data signals DB0 to DB31 in which the logic of all bits is inverted by the first inverting circuit 1, and the converted inverted data signals DB0 to DB31 are input to the parity creating circuit 2. That is, as shown in FIG. 2, the first inverting circuit 1 converts all the bits of the input data signals DA0 to DA31 by the inverter 10 to reverse the logic of "1" and "0". For example, as input data signals DA0 to DA31,
When "00110010 ---" is converted by the first inverting circuit 1, the inverted data signals DB0 to DB31 become "1100".
1101 ---- ". The parity signals PA0 to PA5
Similarly, the parity generation circuit 2 generates inverted parity signals PB0 to PB5 in accordance with the inverted data signals DB0 to DB31 and the Hamming matrix H. Thereafter, as shown in FIG. 12, information of 44 bits / 1 data of the configuration of the input data signals DA0 to DA31, the parity signals PA0 to PA5, and the inverted parity signals PB0 to PB5 is stored in the memory cell array 3.

FIG. 11 is a diagram for explaining the inversion of the read level of the information stored in the memory cell in the second inversion circuit 4. In FIG. 11, the read voltage v
Reference numerals 1 and 2 denote voltages read from the transistors constituting the memory cell, respectively, and are inverted with respect to the determination voltage Vd. That is, (Vd + (Vd−v1)) and (Vd + (V
d−v2)) is calculated. In the second inverting circuit 4, the A / D converter 41, the arithmetic circuit 42, and the D / A
Using converter 43, (2Vd-v1) and (2Vd-v1)
v2) is calculated to obtain a level-inverted data signal in which the read level is inverted with respect to the determination voltage Vd.

Next, when reading information stored in the memory cell array 3, the sense circuit 5 first reads data from the memory cells in which the input data signals DA0 to DA31 are stored, and outputs read data signals MDA0 to MDA31. Then, the parity signals PA0 to PA5 are read from the memory cells stored therein, and the read parity signals MPA0 to MPA are read.
PA5 and outputs the inverted parity signals PB0 to PB0.
5 is read from the memory cell in which 5 is stored, and read inverted parity signals MPB0 to MPB5 are output. Further, the second inversion circuit 4 receives a level inversion data signal in which the read level of the memory cell is inverted with respect to the read determination voltage Vd, and the sense circuit 5 outputs read inversion data signals MDB0 to MDB31. The read determination voltage Vd is a reference voltage for comparing the threshold voltage of the constituent transistor of the memory cell to be read by the sense circuit 5, and the read voltage is higher or lower than the read determination voltage. The storage information “0”, “1” is determined according to the above.

Then, the read data signal MDA
0 to MDA31, read parity signals MPA0 to MPA5,
The inverted read data signals MDB0 to MDB31 and the inverted read parity signals PB0 to PB5 are input to the syndrome creation circuit 6. The syndrome creation circuit 6 makes the read data signals MDA0 to MDA31 and the read parity signals MPA0 to MPA5 form one data,
As shown in FIG. 3B, an operation according to the Hamming matrix H is performed. The value of each row in the horizontal direction of the Hamming matrix H and data composed of the read data signals MDA0 to MDA31 and the read parity signals MPA0 to MPA5 are represented by mod2.
And the sum of mod2 to obtain the first syndromes SA0 to SA5. Similarly, the syndrome creation circuit 6 reads the inverted read data signals MDB0 to MDB31.
From the inverted inverted parity signals MPB0 to MPB5.
Obtain the syndrome signals SB0 to SB5.

The first syndrome signals SA0 to SA5 and the second syndrome signals SB0 to SB5 created by the syndrome creation circuit 6 are compared by a syndrome determination circuit 7 shown in FIG. In the syndrome determination circuit 7, XORs 71, 72, 73 and NOR 74 determine
After performing an exclusive OR operation to compare the values of the first syndrome signals SA0 to SA5 and the second syndrome signals SB0 to SB5, if the first syndrome signals SA0 to SA5 do not match the second syndrome signals SB0 to SB5. , "0" appears in the output signal C.

The first syndrome signal SA0 to SA5 and the second syndrome signal SB0 to SB5 respectively created by the syndrome creation circuit 6 have the following four possibilities (1) to (4). (1) When the first and second syndrome signals indicate no error (when both the first and second syndrome signals are all “0”) (2) Both the first and second syndrome signals indicate that there is an error, When the values match (3) Both the first and second syndrome signals indicate an error and when the values do not match (4) When only one of the first and second syndrome signals indicates an error The output signal C of the NOR 74 of the syndrome determination circuit 7
Is "1" in the cases of (1) and (2), and "0" in the cases of (3) and (4). When the output signal C is "0", an error signal (shown in FIG. 1) is output from the syndrome determination circuit 7 to notify the memory abnormality to the outside and stop reading.

On the other hand, if the syndrome determination circuit 7
If the output signal C of R74 is "1", the result of the double error check is that there is no error or an error that can be corrected, and error correction is performed as follows. That is, the read data signals MDA0 to MDA31 and the read parity signal M
Syndrome signal SA0 created from PA0 to MPA5
SA5 generate the correction signals E0 to E31 by the correction signal generating circuit 6 shown in FIG.

The input of the correction signal generating circuit 8 shown in FIG.
This corresponds to the Hamming matrix H shown in FIG. That is, the first syndromes SA0 to SA5 corresponding to the configuration of each column in the vertical direction of the Hamming matrix H in FIG. 3A are input. For example, in the correction signal E0, the first syndrome SA0 to SA5 in the first column from the left of the Hamming matrix H is input. The first syndrome signal / S
A0, / SA1, / SA2, / SA3, SA4, SA5 are input. Hereinafter, similarly, the first syndromes SA0 to SA5 whose logic has been inverted / non-inverted so as to correspond to the configuration of each column of the Hamming matrix H are input to generate correction signals E0 to E31. When the value of the correction signal E0 to E31 is "1", which corresponds to the bit having an error, and when the first syndrome signals SA0 to SA5 are all "0" and there is no error,
Both correction signals become "0".

Then, the correction signals E0 to E0
By calculating the exclusive OR of E31 and the read data signals MDA0 to MDA31, corrected output data signals D0 to D31 in which errors have been corrected are output. That is, if the correction signal Ex = 0 (x = 0 to 31) and there is no error, the read data signal MDAx (x = 0 to 31) is output as it is, and the correction signal Ex = 1 (x = 0 to 31). 31) If there is an error,
The logic of the read data signal MDAx (x = 0 to 31) is inverted and output.

Next, error correction of the semiconductor memory device will be described.

Now, (0, 0, 0, 0, 0,..., 0) are written into the memory cell array 3 as the input data signals DA0 to DA31, and the parity signals PA0 to PA5 and the inverted parities PB0 to PB5 are written.

At the time of reading, the threshold voltage Vth of the bit on which this data is recorded is Vth (v00) = 3.1 [V] Vth (v01) = 3.1 [V] Vth (v02) = 6 2.0 [V] Vth (v03) = 6.0 [V] Vth (v04) = 6.0 [V] When Vth (v31) = 6.0 [V], the threshold of the voltages v00 and v01 is reached. Value voltage Vth is 3.1
[V], which is close to the judgment voltage Vd (= 3.0 [V]), and is in the judgment insensitive region.

Therefore, if the data is erroneously read,
There are three types of errors: When v00 and v01 are erroneously read (1, 1, 0, 0, 0, ..., 0) When v01 is erroneously read (0, 1, 0, 0, 0, ..., 0) If v00 is erroneously read (1,0,0,0,0, ..., 0), it is a 2-bit error, so error correction is not possible. Since the error is a one-bit error, the error can be corrected. ,, Is affected by the capacity of the transistors constituting each sense amplifier, so that it is not possible to specify a memory cell in which the threshold voltage Vd is a determination insensitive region. Can not.

In the above semiconductor memory device, the data (0,0,
When writing (0, 0, 0, ..., 0), the data (0, 0,
(0,0,0, ..., 0) inverted data
Using (1, 1, 1,..., 1), the inverted parity signal PB0
To PB5 are stored in the memory cell array 3 together with the normal parities PA0 to PA5. The values read by the sense circuit 5 via the second inverting circuit 4 for each of the above read patterns,.
To (iv). (i) (0,0,1,1,1, ..., 1) (ii) (0,1,1,1,1,1, ..., 1) (iii) (1,0,1,1,1,1, .., 1) (iv) (1, 1, 1, 1, 1,..., 1) This is the voltage v00, v01 passed through the second inverting circuit 4.
Is the read level (v00 = 3.1 [V], v01 = 3.1
[V] is inverted (v00 = 2.9 [V], v0 =
2.1 [V]), and the sense circuit 5 determines the storage information “0” and “1” at the inverted level. Therefore, the read voltage of the determination insensitive area band is twice (at different levels). Will check. Conventionally, the level of stored information "0"
(v00 = 3.1 [V]) In the case of the judgment of the threshold voltage of the judgment insensitive region, the error level is checked by one reading, but the read level is inverted with respect to the judgment voltage Vd. Then, in order to check for an error after sensing the inverted read level, the level of the stored information "1" can be checked (v00 = 2.9 [V]).
That is, by checking the two types of data values, the state of the threshold voltage Vth can be determined, and when the read values of the bits in the determination insensitive area are the same for the two types of read data, the threshold value is clearly determined in the determination insensitive area. You can see that there is.

As described above, if the results of the two types of checks are different, the data contained here includes a bit having a threshold voltage in the determination insensitive area, which is determined as an error. Can be removed by the syndrome verification circuit 7, and the reliability can be further improved.

Therefore, the inspection result and the
By always checking the threshold voltage Vth in an area that is difficult to determine based on both the result of the conversion and the result read as inverted data, the accuracy of error detection can be improved, accurate error correction can be performed, and reliability can be improved. Semiconductor memory device with high reliability can be realized.

Even if the number of bits constituting the input data signal is large, the first inverting circuit 1 is connected to the inverter 10
, The cost can be reduced.

The second inverting circuit 4 includes an A / D converter 41, an arithmetic circuit 42, and a D / A converter 43.
Therefore, it is not necessary to configure an analog arithmetic circuit using an inverting amplifier or the like for each bit of the input data signals DA0 to DA31 stored in the memory cell array 3,
The second inverting circuit 4 can be realized with a simple configuration.

Further, by using a Hamming matrix H having an error correction capability of detecting and correcting one random error, a parity generation circuit 2, a syndrome generation circuit 6, and a correction signal generation circuit for performing error detection and correction. The circuit 8 can be configured particularly simply.

The semiconductor memory device is an electrically erasable and writable EEPROM. When the number of times of rewriting increases, the threshold voltage of a transistor constituting a memory cell changes due to deterioration of an oxide film or the like. Although an error occurs in the read data, the reliability can be particularly improved by applying the present invention.

In the above embodiment, the semiconductor memory device that stores the 32-bit input data signals DA0 to DA31 as the first data signal has been described. However, the bit configuration of the first data signal is not limited to this. Of course.

In the above-described embodiment, the second inverting circuit 4 is constituted by the A / D converter 41, the arithmetic circuit 42 and the D / A converter 43.
It may be constituted by an analog circuit.

Further, in the above-described embodiment, an EEPROM has been described as a nonvolatile semiconductor memory device. However, the present invention is not limited to this, and the present invention can be applied to any memory regardless of volatile / non-volatile. You may.

[0058]

As is apparent from the above description, in the semiconductor memory device according to the first aspect of the present invention, the parity generation unit is configured to determine the parity of two bits or more based on the first data signal of two bits or more and the predetermined matrix. A second signal in which the logic of all bits of the first data signal is inverted by the first inverting unit
A second parity signal of 2 bits or more is created based on the data signal and a predetermined matrix, and the first data signal, the first parity signal, and the second parity signal are stored in a memory cell array. The first data signal, the first parity signal, and the second parity signal stored in the memory cell array are read by a reading unit, and the read level of all bits of the first data signal stored in the memory cell array is determined by a second inverting unit. The third data signal inverted with respect to the reference voltage is read out as a second read data signal by a read unit, and the first read data signal and the first read parity signal read by the read unit are written in a predetermined matrix. The first syndrome indicating the presence or absence of an error in the first read data signal by the syndrome creation unit based on the first syndrome. A second read data signal, a second read parity signal, and a predetermined matrix read out by the readout unit, and the syndrome creation unit indicates presence / absence of an error in the second readout data signal. When the second syndrome signal is created and the syndrome determination unit determines that the bits of the first and second syndrome signals match and the first and second read data signals are incorrect, the first syndrome is determined. And the predetermined matrix based on
It corrects an error in the read data signal.

Therefore, according to the semiconductor memory device of the first aspect of the present invention, the first read data signal read from the memory cell array and the second read data signal whose read level from the memory cell array is inverted are: By performing an error check using the first parity signal and the second parity and a predetermined matrix, it is possible to improve the accuracy of error check of data read from the memory cell, and to perform accurate error correction based on the check result. A highly reliable semiconductor memory device can be realized.

According to a second aspect of the present invention, in the semiconductor memory device of the first aspect, since the first inverting section is an inverter, the number of bits forming the first data signal is at most. The first reversing section can be simply configured, and the cost can be reduced.

According to a third aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the second inverting section A / D converter controls all of the first data signals stored in the memory cell array. A / D conversion is performed on the read level of each bit, and the A / D converter
The readout level of each bit of the converted first data signal is inverted by the arithmetic unit with respect to the predetermined reference voltage, and the readout level of all bits of the first data signal is calculated based on the arithmetic result of the arithmetic unit. Is output by the D / A converter, so that it is not necessary to configure an analog arithmetic circuit using an inverting amplifier or the like for each bit of the first data signal stored in the memory cell array. The two reversing units can be easily configured.

According to a fourth aspect of the present invention, in the semiconductor memory device of the first aspect, since the Hamming matrix is used for the predetermined matrix, the parity creation unit for performing error detection and correction is provided. Therefore, the syndrome creation unit and the error correction unit can be particularly easily configured.

According to a fifth aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the memory cell array is an EEPROM memory cell array. Even if an error occurs in read data due to a change in the threshold voltage of a transistor included in a memory cell, the error can be accurately corrected and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a main block diagram of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a first inversion circuit of the semiconductor memory device.

FIG. 3A is a diagram showing a Hamming matrix used in a parity generation circuit of the semiconductor memory device.
(B) is a diagram showing a determinant for creating parity.

FIG. 4 is a circuit diagram of a parity creation circuit of the semiconductor memory device.

FIG. 5 is a circuit diagram of a syndrome creation circuit of the semiconductor storage device.

FIG. 6 is a diagram showing a determinant for creating a syndrome of the semiconductor memory device.

FIG. 7 is a circuit diagram of a syndrome determination circuit of the semiconductor memory device.

FIG. 8 is a circuit diagram of a correction signal generation circuit of the semiconductor memory device.

FIG. 9 is a circuit diagram of a correction circuit of the semiconductor memory device.

FIG. 10 is a circuit diagram of a second inverting circuit of the semiconductor memory device.

FIG. 11 is a diagram illustrating an operation in a second inverting circuit of the semiconductor memory device.

FIG. 12 is a diagram showing a configuration of data stored in a memory cell array of the semiconductor memory device.

FIG. 13 is a truth table of the product of mod2 and the sum of mod2.

FIG. 14 is a block diagram of a main part of a conventional semiconductor memory device.

FIG. 15 is a main part circuit diagram of a sense amplifier of the semiconductor memory device.

FIG. 16 is a diagram illustrating a determination insensitive region of a sense amplifier of the semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st inversion circuit, 2 ... Parity creation circuit, 3 ... Memory cell array, 4 ... 2nd inversion circuit, 5 ... Sense circuit, 6 ... Syndrome creation circuit, 7 ... Syndrome judgment circuit, 8 ... Correction signal generation circuit, 9 ... correction circuit.

Claims (5)

[Claims] 1. A first inverting unit for inverting the logic of all bits of a first data signal of 2 bits or more, and a first parity signal of 2 bits or more based on the first data signal and a predetermined matrix. Create the first
A parity creation unit that creates a second parity signal of 2 bits or more based on the second data signal obtained by inverting the logic of all bits of the first data signal from the inversion unit and the predetermined matrix; A memory cell array storing one data signal, the first parity signal, and the second parity signal; and inverting read levels of all bits of the first data signal stored in the memory cell array with respect to a predetermined reference voltage. A second inverting unit that outputs a third data signal in which the levels of all bits of the first data signal are respectively inverted; the first data signal, the first parity signal, and the first data signal stored in the memory cell array; The second parity signal is read, and a first read data signal, a first read parity signal, and a second read parity signal are respectively output. A read unit that reads the third data signal from the second inversion unit and outputs a second read data signal; and a read unit that reads the first read data signal, the first read parity signal, and the predetermined matrix. Generating a first syndrome signal, and generating a second syndrome signal based on the second read data signal, the second read parity signal, and the predetermined matrix; and Receiving the first and second syndrome signals, determining whether the first and second syndrome signals match, and determining the first and second read data signals based on the first and second syndrome signals. Alternatively, a syndrome determination unit that determines whether the first and second read parities are erroneous; When the determination unit determines that the first and second syndrome signals match and the first and second read data signals are incorrect, the determination unit determines the first and second read data signals based on the first syndrome signal and the predetermined matrix. 1. A semiconductor memory device comprising: an error correction unit that corrects an error in one read data signal. 2. The semiconductor memory device according to claim 1, wherein said first inverting unit is an inverter. 3. The semiconductor memory device according to claim 1, wherein said second inverting unit is configured to A / D-convert each read level of all bits of said first data signal stored in said memory cell array.
A D converter, and the first A / D converted by the A / D converter.
An operation unit for inverting the read level of each bit of the data signal by an operation with respect to the predetermined reference voltage, and a read level of all bits of the first data signal being inverted based on the operation result of the operation unit And a D / A converter for outputting the second data signal. 4. The semiconductor memory device according to claim 1, wherein a Hamming matrix is used for said predetermined matrix. 5. The semiconductor memory device according to claim 1, wherein said memory cell array is an EEPROM memory cell array.