JP2003228992A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce circuit scale and to shorten a test time without requiring a data selector for writing data directly to an ECC memory in a semiconductor memory device having an ECC function for data having 32 bits data width. <P>SOLUTION: One exclusive OR circuit is added to a circuit generating each bit of ECC bit data of 6 bits in an ECC bit generating section so that ECC bit data also is made a specific test pattern for a specific test pattern. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an ECC (error detection / correction) function.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor manufacturing processes, the capacity of semiconductor memory devices is increasing, but on the other hand,
As the degree of integration increases, the occurrence of soft errors becomes a problem. Further, in a nonvolatile memory device represented by an EEPROM (electrically erasable and writable read-only memory), the gate of the memory cell has a thin oxide film, which deteriorates due to electrical stress. As the degree of integration is improved, it is becoming difficult to increase the life, that is, the number of rewritable times.

In order to deal with such a problem, it is effective to add an error correction function by ECC to the semiconductor memory device and thereby relieve a bit that exceeds the endurance capacity of rewriting. The ECC will be described below.

The ECC is a combination of ECC bit data (parity bit) added to the data to be recorded and written to the memory, and the ECC added with the written data when reading.
By processing bit data in ECC, an erroneous data bit is detected and further corrected.

FIG. 1 is a functional block diagram showing the overall configuration of a semiconductor memory device. In FIG. 1, an input / output control unit 1 is a circuit that controls data to be recorded and read data, and an ECC circuit 3 performs generation of ECC bit data, which will be described later, and error correction of 32-bit data.
The memory 5 is a memory area for storing data to be recorded, and the ECC memory 6 is a memory area for storing ECC bit data.

In the data write operation, the data 2 to be recorded is input to the ECC circuit 3 via the input / output control unit 1. The data 2 input to the ECC circuit 3 is operated in the ECC circuit 3 to generate ECC bit data 4. Further, the data 2 is stored in the memory 5, and the ECC bit data 4 is stored in the ECC memory 6. As described above, the input data 2 and the ECC bit data 4 are written in the corresponding memory areas.

During the data read operation, the data read from the memory 5 and the ECC memory 6 and the read ECC bit data are input to the ECC circuit 3, and the ECC circuit 3 detects an erroneous bit.・ Correct,
The corrected data is output to the outside via the input / output control unit 1.

The above is a simple flow of error detection / correction by the ECC circuit 3.

Next, the contents of the error correction processing inside the ECC circuit 3 will be described with reference to FIG. Figure 2
FIG. 3 is a functional block diagram showing an internal configuration of the ECC circuit 3 of FIG. 1.

In FIG. 2, the 32-bit data 12 read from the memory 5 is input to the ECC bit generation unit 8 where arithmetic processing is performed and ECC bit data 13 is applied.
Is generated. The generated ECC bit data 13,
ECC bit data 1 read from the ECC memory 6
4 is input to the syndrome generation unit 9, where the exclusive OR is taken and the syndrome 15 is generated.

Here, if there is an error in the 32-bit data 12 read from the memory 5, the ECC bit data 13 generated by the ECC bit generation unit 8
Unlike the ECC bit data 14 read from the ECC memory 6, as a result, the generated syndrome 15 is added with the error bit position information in the 32-bit data 12. The syndrome 15 thus generated is input to the error position detection unit 10 and converted into 32 bits, and then the error correction unit 11 corrects the 32-bit data 12 read from the memory 5.

When writing to the memory, the 32-bit data 2 to be recorded is input to the ECC bit generator 8 and the generated ECC bit data 4 is stored in the ECC memory 6.
Will be stored in.

The above is the contents of the error correction processing at the time of reading in the memory device.

Further, E in the ECC bit generator 8
The contents of the CC bit generation process will be described. The failure in the memory is mainly a random failure (a failure in which the data is randomly incorrect), not a burst failure in the communication (a failure in which the data is continuously incorrect). Therefore, when designing an ECC to be mounted on a memory device, it is common to use a Hamming code composed of a Hamming code. Here, the Hamming code will be described assuming that the data bit width recorded in the memory 5 is 32 bits.

When the data bit width is 32 bits,
The ECC bit width added to this is 6 bits to express the presence or absence of an error and the position of the defective bit. Than this,
The Hamming code used for the error correction processing by the ECC circuit 3 is a matrix of 6 columns × 32 rows. In order to generate this Hamming code, it is a condition that two or more "1" s are included in 6 bits in the row direction and data does not overlap with other 6 bits in the row direction. Further, in order to minimize the scale of the circuit that expresses the generated Hamming code, it is necessary to minimize the number of "1" s in the column direction (Hamming weight) and make the Hamming weights of the respective columns equal. FIG. 7 shows an example of a Hamming code generated by satisfying the above conditions. The ECC bit data 13 is generated by the exclusive OR of the Hamming code and the input data.

In FIG. 8, 6 bits are generated by setting the 32-bit data input to the ECC bit generation unit 8 as D0 to D31.
9 and 10 show an equation representing the ECC bit generation process (where "+" represents an exclusive OR) when the ECC bit data of the bits are E0 to E5.
A specific circuit for performing the CC bit generation processing is shown. In FIG. 9, 32-bit data is input and each ECC is
FIG. 10 shows a block of each processing circuit from which bit data is output, and FIG. 10 shows a detailed configuration of each processing circuit of FIG. 9 based on the equation shown in FIG.

It should be noted here that FIG. 9 and FIG.
It is a factor that determines the circuit scale of the ECC shown in FIG.
The number of elements to be subjected to the exclusive OR in FIG. 8 is 14, which is the same value as the Hamming weight (the number of “1”) in the column direction of the Hamming code in FIG. 7. Further, the smaller the number of elements to be the objects of the exclusive OR in FIG. 8, the smaller the circuit scale in FIGS. 9 and 10. Therefore, by minimizing the Hamming weight of the Hamming code in FIG. 7, the circuit scale of the ECC circuit 3 can be reduced, and it can be said that it is necessary to minimize the Hamming weight as described above. The ECC bit data is generated in the ECC bit generation unit 8 by the above processing.

By the way, in the inspection of each memory area of the memory device having such an ECC circuit 3, both the memory 5 and the ECC memory 6 shown in FIG. 1 are to be inspected. Therefore, it is necessary to inspect the memory area by writing a specific inspection pattern to the memory 5 and the ECC memory 6 and reading it.

[0019]

[Problems to be Solved by the Invention] However, the ECC
In the memory device equipped with the circuit 3, the pattern written in the ECC memory 6 is determined by the input bit data to be recorded.
It is very difficult to write an arbitrary pattern in the C memory 6. Especially in the case of 32-bit bus width data,
Using the Hamming code shown in FIG. 7 generated by the method described above, the ECC bit data calculated according to the equation shown in FIG. 8 is all “1” even if all the 32 bit data is “1”. It is not "1" but all "0".
When all the 32-bit data are "0", all the ECC bit data are "0", but all are "0" in the checker pattern. This allows the ECC
It becomes impossible to write a specific pattern to the ECC memory 6 through the processing.

In order to solve this, there is a method of directly writing data to the ECC memory 6 without performing processing by the ECC circuit 3, but in order to realize this method, it is necessary to add a data selector. Yes, this increases the circuit scale. In addition, the memory 5 and the ECC memory 6
In order to write arbitrary data to each, the number of times of writing is doubled as compared with the normal operation, and the inspection time is increased.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an ECC for data having a 32-bit bus width without requiring a data selector for directly writing data in an ECC memory. It is an object of the present invention to provide a semiconductor memory device with a reduced circuit scale and a shorter inspection time.

[0022]

In order to achieve the above-mentioned object, the semiconductor memory device according to the present invention should be recorded.
What is claimed is: 1. A semiconductor memory device having an ECC circuit including an ECC bit generation unit for processing data having a bit bus width and generating error detection / correction (ECC) bit data having a width of 6 bits. If all the 32-bit bus width data to be written is logical "0", all the 6-bit bus width ECC bit data are also output as logical "0", and all the 32-bit bus width data to be recorded are logical "1". If so, all the ECC bit data of the 6-bit bus width is also output as logic "1", and if the data of the 32-bit bus width to be recorded is a checker pattern (0101 ...), the ECC bit data of the 6-bit bus width is output. Is also output as a checker pattern, and the 32-bit bus width data to be recorded is the checker bar pattern (1010 ...),
It is characterized in that it includes a circuit for performing an exclusive OR on the data of the 32-bit bus width to be recorded so that the ECC bit data of the 6-bit bus width is also output in the checker bar pattern.

In the semiconductor memory device according to the present invention,
When each bit of data of 32 bit bus width is taken in the column direction and each bit of ECC bit data of 6 bit bus width is taken in the row direction and a Hamming code for generating ECC bit data is described, the Hamming weight of each column is described. Is 15, and the ECC bit generation unit includes an exclusive OR circuit that generates each bit of the ECC bit data from the 15-bit data of the 32-bit bus width data.

According to the above configuration, at the time of the ECC memory inspection, it is possible to write a specific inspection pattern (all "0", all "1", checker pattern) in the ECC memory in the normal operation. Since a data selector for directly writing data to the memory is not required, the circuit scale can be reduced, and it is not necessary to separately write to the memory for data to be recorded and the ECC memory.
The inspection time can be shortened.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

The overall block configuration of the semiconductor memory device according to the embodiment of the present invention and the error correction process inside the ECC circuit 3 will be described with reference to FIGS.
Since it is the same as the conventional example shown in FIG.

This embodiment differs from the conventional example in that the ECC
This is in the configuration of the ECC bit generator 8 inside the circuit 3. Therefore, the contents of the ECC bit generation processing in the ECC bit generation unit 8 will be described below.

When the ECC bit generation process is performed on the 32-bit bus width data to be recorded, as described above, 32
A × 6 Hamming code is required, and an arithmetic process is performed using this Hamming code to generate an ECC bit.
In order to generate this Hamming code, it is necessary that the number of "1" s in each row is two or more and that the Hamming weights in each column are aligned and minimized in order to further reduce the circuit scale as described above. Conventionally, an example of the ECC bit generation Hamming code for 32-bit bus width data generated by satisfying the above condition is as shown in FIG. 7, and based on this, the ECC is generated.
When generating bits, the ECC bits are generated according to the equation of FIG. When ECC bits are generated using this formula, all 32-bit bus width data to be recorded is "1".
In this case, all the ECC bits become “0”, and it is impossible to write a specific inspection pattern in the ECC memory 6 through the ECC process.

Therefore, in the prior art, the minimum Hamming weight of each column is 14 when generating a Hamming code.
In the present embodiment, by setting this to 15 and rearranging the Hamming weights, it is possible to realize the specific pattern generation of the ECC bit data in the specific pattern (all "0", all "1", checker pattern). As described above, by setting the Hamming weight of each column to 15 and further aligning the Hamming weight of each column, an example of the Hamming code as shown in FIG. 3 can be generated.

ECC using the Hamming code shown in FIG.
When the input 32-bit data is DO to D31 and the generated 6-bit ECC bit data is E0 to E5 when generating the bit data, the ECC bits are generated by the formula shown in FIG. If ECC bit data is generated using the formula shown in FIG.
Even if all bit bus width data is "0",
The ECC bit data are all "0", and even if the 32-bit bus width data has the checker pattern, the ECC bit data also has the checker pattern. That is, the circuit for expressing the Hamming code shown in FIG. 3 can write the inspection pattern in the ECC memory through the ECC process, and the inspection time can be shortened.

Further, when the Hamming code shown in FIG. 3 is represented by a circuit, the ECC bit generating section 8 has a structure as shown in FIG. 5, and the circuit for generating each ECC bit data in FIG. 5 has a structure as shown in FIG. It will be composed. As shown in FIG. 6, in the present embodiment, as compared with the conventional example, one more exclusive OR circuit is provided in the circuit that generates each ECC bit data. The added exclusive OR circuit 16 shown in FIG. 6 corresponds to this. That is, the problem in the conventional example can be solved by adding one circuit (six in total) that executes the exclusive OR, and the exclusive OR circuit 16 is added directly to the ECC memory. A much smaller circuit can be added than adding a circuit such as a data selector for realizing writing to 6.

[0032]

As described above, according to the present invention,
At the time of ECC memory inspection, a specific inspection pattern can be written in the ECC memory in a normal operation, and a data selector for directly writing data in the ECC memory is not required, so that the circuit scale can be reduced and further recording should be performed. Since it is not necessary to write the data memory and the ECC memory separately, the inspection time can be shortened.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing the overall configuration of a semiconductor memory device.

FIG. 2 is a functional block diagram showing an internal configuration of the ECC circuit 3 of FIG.

FIG. 3 is a diagram showing an example of a Hamming code for generating ECC bit data according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating an ECC bit data generation formula according to an embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of an ECC bit generation unit according to an embodiment of the present invention.

FIG. 6 is a detailed configuration diagram of a circuit that generates each ECC bit data in FIG.

FIG. 7 is a diagram showing an example of a Hamming code for generating ECC bit data in a conventional example.

FIG. 8 is a formula for generating ECC bit data in a conventional example.

FIG. 9 is a circuit configuration diagram of an ECC bit generation unit in a conventional example.

FIG. 10 is a detailed configuration diagram of a circuit that generates each ECC bit data of FIG. 9.

[Explanation of symbols] 1 I / O controller 2 Input 32-bit data 3 ECC circuit 4 ECC bit data 5 memory 6 ECC memory 8 ECC bit generator 9 Syndrome generating part 10 Error position detector 11 Error correction section 12 read 32-bit data 13 Generated ECC bit data 14 Read out ECC bit data 15 Syndrome 16 additional exclusive OR circuits

Claims (2)

[Claims] 1. An ECC including an ECC bit generation unit for processing 32-bit bus width data to be recorded to generate 6-bit bus width error detection / correction (ECC) bit data.
In a semiconductor memory device having a circuit, the ECC bit generation unit is configured such that if all the 32-bit bus width data to be recorded is logical "0", the 6-bit bus width ECC bit data is also logical "0". If 0 "is output and all the 32-bit bus width data to be recorded are logical" 1 ", all ECC bit data of the 6-bit bus width are also output as logical" 1 ", and the 32 bits to be recorded are If the bus width data is a checker pattern (0101 ...), the 6-bit bus width ECC bit data is also output in a checker pattern, and the 32-bit bus width data to be recorded is a checker bar pattern (1010 ...). If so, the ECC bit data having the 6-bit bus width is also output in a checker bar pattern so that the 32-bit bus width to be recorded is set. A semiconductor memory device comprising a circuit for performing exclusive OR on data. 2. A Hamming code for generating ECC bit data is described by taking each bit of the 32-bit bus width data in the column direction and each bit of the 6-bit bus width ECC bit data in the row direction. In this case, the Hamming weight of each column is 15, and the ECC bit generation unit
2. The semiconductor memory device according to claim 1, further comprising an exclusive OR circuit for generating each bit of ECC bit data from 15-bit data of the 32-bit bus width data.