JP3430415B2 - Differential amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier, and more particularly to a differential amplifier having high linearity and stable common mode voltage.

[0002]

2. Description of the Related Art A differential amplifier is used in an input stage of an oscilloscope or the like and amplifies and outputs a signal under measurement while adjusting a common mode voltage of a signal under test which is differentially input.

FIG. 3 is a circuit diagram showing an example of such a conventional differential amplifier, and in FIG. 3, 1, 2, 8, 9, 1
0, 11, 12, 13, 26, 27, 31 and 32 are transistors, 3, 4, 6, 7, 14, 15, 16, 1
7, 24, 25, 29 and 30 are resistors, 5, 20, 2
Reference numerals 1, 22, 23 and 28 are constant current sources, 18 and 19 are buffer circuits, 33 is a capacitance, 100 and 101 are input voltages, and 102 and 103 are output voltages. In addition, 24-
33 constitutes an operational amplifier 50.

Input voltages 100 and 101 are connected to the bases of transistors 1 and 2, the emitters of transistors 1 and 2 are connected to one ends of resistors 3 and 4, the other end of resistor 3 being the other end of resistor 4 and a constant current. Connected to one end of the source 5.

The collector of the transistor 1 is connected to one end of the resistor 6, the emitter of the transistor 8 and the collector of the transistor 10, respectively, and the collector of the transistor 2 is connected to one end of the resistor 7, the emitter of the transistor 9 and the collector of the transistor 13, respectively. It

The collector of the transistor 8 is connected to the input terminal of the buffer circuit 18 and one end of the constant current source 20, and the collector of the transistor 9 is connected to the input terminal of the buffer circuit 19 and one end of the constant current source 23.

The emitters of the transistors 10 and 11 are connected to one ends of the resistors 14 and 15, and the other end of the resistor 14 is connected to the other end of the resistor 15 and one end of the constant current source 21.

Similarly, the emitters of the transistors 12 and 13 are connected to one ends of the resistors 16 and 17, and the other end of the resistor 16 is connected to the other end of the resistor 17 and one end of the constant current application 22.

The output terminal of the buffer circuit 18 has an output voltage of 1
03 is output and is connected to the base of the transistor 10 and one end of the resistor 25. The output terminal of the buffer circuit 19 outputs the output voltage 102 and is connected to the base of the transistor 13 and one end of the resistor 24.

The other end of the resistor 24 is connected to the other end of the resistor 25 and the base of the transistor 26, and the emitter of the transistor 26 is the emitter of the transistor 27 and the constant current source 2.
8 is connected to one end.

The collector of the transistor 26 is connected to the bases of the transistors 31 and 32 and the collector of the transistor 31, and the collector of the transistor 27 is connected to the bases of the transistors 8 and 9, the collector of the transistor 32 and one end of the capacitor 33.

The emitters of the transistors 31 and 32 are connected to one ends of the resistors 29 and 30.

Further, the other ends of the resistors 6, 7, 29 and 30 and the collectors of the transistors 11 and 12 are connected to a positive voltage source, and constant current sources 5, 20, 21, 22, 23 and 28 are connected.
The other end of which is connected to a negative voltage source,
The bases of and 27 and the other end of the capacitor 33 are grounded.

The operation of the conventional example shown in FIG. 3 will be described. Transistors 1, 2, 10, 11, 12 and 13,
Transistors 26 and 27, transistors 31 and 32
Are NPN transistors of the same size, and transistors 8 and 9 are PNP transistors of the same size.

The resistance values of the resistors 3, 4, 14, 15, 16, and 17, the resistance values of the resistors 6 and 7, the resistance values of the resistors 24 and 25, and the resistance values of the resistors 29 and 30 are the same.

The output currents of the constant current sources 5, 21 and 22 are "I1" and the output currents of the constant current sources 20 and 23 are "I1".
0 ″, and the relationship of I1 = I0 × 2 (1) is satisfied.

The base voltage of the transistors 8 and 9 is the bias voltage "Vbias" applied from the operational amplifier 50.
Therefore, the emitter voltages “Ve8” and “Ve9” of the transistors 8 and 9 are Ve8 = Ve9 = Vbias + Vbe (2) when the base-emitter voltage of the transistors 8 and 9 is “Vbe”.

Therefore, since the current values flowing through the resistors 6 and 7 are the same, "Vbias" and the resistance values of the resistors 6 and 7 are appropriately set, and the current values "I6" and "I7" flowing through the resistors 6 and 7 are set. Is I6 = I7 = 3 × I0 (3).

At this time, the collector currents of the transistors 1, 8 and 10 are changed to "Ic1", "Ic8" and "Ic10".
Then, Becomes

Since the collector current of the transistor 8 is the output current itself of the constant current source 20, from the above condition, Ic8 = I0 (5), and the equation (4) is Ic1 + I0 + Ic10 = 3 × I0 Ic1 + Ic10 = 2 × I0 (6 ).

The collector current of the transistor 11 is set to "Ic
If it is 11 ″, then Ic10 + Ic11 = I1 = 2 × I0 (7)

From equations (6) and (7), Ic1 + 2 × I0−Ic11 = 2 × I0 ∴Ic1 = Ic11 (8) Becomes

Similarly, if the collector currents of the transistors 2 and 12 are "Ic2" and "Ic12", then Ic2 = Ic12 (9).

On the other hand, if the collector current of the transistor 13 is "Ic13", then Ic12 + Ic13 = I1 = 2 × I0 (10), and Ic2 + Ic13 = 2 × I0 (11) from the equations (9) and (10). Become.

Here, Ic1 + Ic2 = 2 × I0 (12) Therefore, from equation (11) and equation (12), 2 x I0-Ic1 + Ic13 = 2 x I0 ∴Ic1 = Ic13 (13) Also, from equation (6) and equation (12) 2 x I0-Ic10 + Ic2 = 2 x I0 ∴Ic2 = Ic10 (14) Becomes

From equations (8) and (13) Ic1 = Ic11 = Ic13 (15) Also, from equation (9) and equation (14) Ic2 = Ic10 = Ic12 (16) Becomes

Therefore, when the input voltages 100 and 101 are applied to the bases of the transistors 1 and 2, the negative feedback circuit composed of the transistors 8 and 10 and the buffer circuit 18, the transistors 9 and 13 and the buffer circuit 19 are composed. With the negative feedback circuit, the collector currents of the transistors 1, 11 and 13 are the same, and the collector currents of the transistors 2, 10 and 12 are the same.

At this time, a potential difference "Vin" between the input voltages 100 and 101 appears between the bases of the transistors 10 and 11 and between the bases of the transistors 12 and 13, and the bases of the transistors 11 and 12 are connected to each other. Therefore, a voltage twice the potential difference "Vin" is output between the bases of the transistors 10 and 13.

Further, since the bases of the transistors 11 and 12 are grounded, the output voltage 102 is "+ Vi".
n ”and“ -Vin ”are output to the output voltage 103, respectively.

As a result, it operates as a differential amplifier which doubles the potential difference "Vin" of the input voltage and outputs it.

Further, the operational amplifier 50 operates as a feedback loop which determines the common mode voltage. Output voltages 102 and 103 are connected in series with resistors 24 and 25.
Since it is connected to the common mode voltage, the common mode voltage appears at the point indicated by "a" in FIG.

This common mode voltage is applied to the transistor 26.
Since the base of the transistor 27 is grounded and the base of the transistor 27 is grounded, the operational amplifier 50 adjusts the bias voltage applied to the bases of the transistors 8 and 9 so that the common mode voltage becomes "0V".

As a result, it operates as a differential amplifier which doubles the potential difference "Vin" of the input voltage and adjusts the common mode voltage to "0V".

[0034]

However, the gain of the feedback loop is increased by using the operational amplifier 50 for stabilizing the common mode voltage.
There is a problem in that a large phase compensation capacitance such as the capacitance 33 is required and the response is delayed and the linearity deteriorates. Therefore, the problem to be solved by the present invention is to realize a differential amplifier having high linearity.

[0035]

In order to achieve such a problem, in the first aspect of the present invention, in the differential amplifier, 2
A first differential circuit to which two input voltages are connected, second and third differential circuits to which one output is connected to a positive voltage source, respectively, one end of which is connected to the positive voltage source and the other end of which is A first resistor to which one output of the first differential circuit and the other output of the second differential circuit are connected , and one end of which is connected to a positive voltage source.
Re and a negative <br/> load resistor composed of a second resistor the other output of said first differential circuit and said third differential circuit at the other end is connected, the the load resistor Other than the first and second resistors
A cascode circuit connected to the end, two constant current sources to which outputs of the cascode circuit are respectively connected, outputs of the cascode circuit are connected to output an output voltage, and the second and third differential circuits are provided. Two buffer circuits connected to one input terminal of the circuit, a first voltage source connected to the other input terminals of the second and third differential circuits, and a bias voltage applied to the cascode circuit And a second voltage source that operates.

In order to achieve such a subject, in the second aspect of the present invention, in a differential amplifier, a first differential circuit to which two input voltages are connected, and one end is connected to a positive voltage source.
A first resistor to which one output of the first differential circuit and the other output of the second differential circuit are connected to the other end, and one end
A second resistor but the other output of said first differential circuit and said third differential circuit is connected to the other end is connected to a positive voltage source
And a first load resistance of the load resistance .
And a cascode circuit connected to the other end of the second resistor ,
Two constant current sources to which outputs of the cascode circuit are connected respectively, and outputs of the cascode circuit are connected to output an output voltage and are also connected to one input terminals of the second and third differential circuits. Two buffer circuits, a first voltage source connected to the other input terminals of the second and third differential circuits, and the other output of the second and third differential circuits are connected. A current adjusting means for applying a bias voltage to the cascode circuit is provided.

In order to achieve such a subject, in a third aspect of the present invention, in the first and second aspects of the present invention, the first aspect is used.
Is characterized by using a variable voltage source as the voltage source.

In order to achieve such a subject, in the fourth aspect of the present invention, in the second aspect of the present invention, the second and third aspects are provided.
The other output of the differential circuit is connected to two diode-connected transistors, and the current adjusting means for applying the base voltage of the two transistors to the cascode circuit is used.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration circuit diagram showing an embodiment of a differential amplifier according to the present invention.

1 to 23, 100 and 101 in FIG.
Are denoted by the same reference numerals as in FIG. 3, and 34 is a variable voltage source, 3
5 is a voltage source, and 102a and 103a are output voltages.

Further, 1 to 5 are differential circuits 51, 6 and 7
Is a load resistor 52, 8 and 9 are cascode circuits 53,
10, 11, 14, 15, and 21 are differential circuits 54,
2, 13, 16, 17, and 22 form a differential circuit 55, respectively.

The input voltages 100 and 101 are connected to the bases of the transistors 1 and 2, the emitters of the transistors 1 and 2 are connected to one ends of the resistors 3 and 4, and the other end of the resistor 3 is the other end of the resistor 4 and a constant current. Connected to one end of the source 5.

The collector of the transistor 1 is connected to one end of the resistor 6, the emitter of the transistor 8 and the collector of the transistor 10, respectively, and the collector of the transistor 2 is connected to one end of the resistor 7, the emitter of the transistor 9 and the collector of the transistor 13, respectively. It

The collector of the transistor 8 is connected to the input terminal of the buffer circuit 18 and one end of the constant current source 20, and the collector of the transistor 9 is connected to the input terminal of the buffer circuit 19 and one end of the constant current source 23.

The emitters of the transistors 10 and 11 are connected to one ends of the resistors 14 and 15, and the other end of the resistor 14 is connected to the other end of the resistor 15 and one end of the constant current source 21.

Similarly, the emitters of the transistors 12 and 13 are connected to one ends of the resistors 16 and 17, and the other end of the resistor 16 is connected to the other end of the resistor 17 and one end of the constant current application 22.

The output terminal of the buffer circuit 18 has an output voltage of 1
03a is output and is also connected to the base of the transistor 10, and the output terminal of the buffer circuit 19 outputs the output voltage 102
It outputs a and is connected to the base of the transistor 13.

Further, one end of the variable voltage source 34 is connected to the bases of the transistors 11 and 12, and one end of the voltage source 35 is connected to the bases of the transistors 8 and 9.

Further, the other ends of the resistors 6 and 7 and the collectors of the transistors 11 and 12 are connected to a positive voltage source, and the other ends of the constant current sources 5, 20, 21, 22, and 23 are connected to a negative voltage source, The other ends of the variable voltage source 34 and the voltage source 35 are grounded.

The operation of the embodiment shown in FIG. 1 will be described here. The bias voltage applied from the voltage source 35 is applied to the transistors 1, 1 when the input voltages 100 and 101 are "0V".
The collector currents of 2, 10, 11, 12 and 13 are set to be the same.

In this state, when the input voltages 100 and 101 having the potential difference "Vin" are applied to the bases of the transistors 1 and 2, the transistor 10 is turned on similarly to the conventional example shown in FIG.
The potential difference "Vin" between the input voltages 100 and 101 between the bases of the transistors 11 and 11 and between the bases of the transistors 12 and 13.
Appears.

Since the bases of the transistors 11 and 12 are connected to each other, a voltage twice the potential difference "Vin" is output between the bases of the transistors 10 and 13.

Since the output voltage "Vcom" of the variable voltage source 34 is connected to the bases of the transistors 11 and 12, the output voltage 102a is "+ Vin + Vco".
m "is" -Vin + Vcom "in the output voltage 103a.
Will be output respectively.

Therefore, the common mode voltage can be adjusted by adjusting the output voltage of the variable voltage source 34.

In the embodiment shown in FIG. 1, the operational amplifier 5
Since 0 is not used, the gain in the feedback loop is reduced and a high-speed response is possible, so that the linearity is improved in a wide band.

As a result, by fixing the bias voltage of the cascode circuit 53 and adjusting the voltage at the connection point of the differential circuits 54 and 55, a wide-band differential amplifier with high linearity can be realized.

However, in the embodiment shown in FIG. 1, the common mode voltage fluctuates due to element non-linearity, temperature change, and the like.

FIG. 2 is a constitutional circuit diagram showing another embodiment of the differential amplifier according to the present invention which solves such a problem.

In FIG. 2, 1 to 23, 34, 51 to 5
5, 100 and 101 have the same reference numerals as those in FIG.
36 is a resistor, 37 and 38 are transistors, and 102b and 103b are output voltages. Further, 36 to 38 constitute a current adjusting means 56.

The basic connection relationship is almost the same as that of the embodiment shown in FIG. 1, except that the bases of the transistors 8 and 9 are connected to the bases of the transistors 37 and 38 and the collectors of the transistors 11, 12, 37 and 38. That is, the emitters of the transistors 37 and 38 are connected to the positive voltage source via the resistor 36.

The operation of the embodiment shown in FIG. 2 will be described here. However, the basic operation such as differential amplification is the same as that of the embodiment shown in FIG.

The basic circuit constants are the same as above, and the collector currents of the transistors 37 and 38 are "I".
The resistance values of the resistors 6, 7 and 36 are set so as to be "0".

For example, the current value of the resistors 7 and 8 can be calculated by the equation (3).
As described above, since the current value of the resistor 36 may be "2 × I0", the resistance values of the resistors 6, 7 and 36 are "R6", "R7" and "R36", respectively. R36: R6 = R36: R7 = 3: 2 (17) The following relationship may be satisfied.

In the current adjusting means 56, the collector currents of the transistors 11 and 12 are connected to the diode-connected transistors 37 and 38.
And 38 base voltages are applied to the bases of transistors 8 and 9.

Here, since the collector currents of the transistors 8 and 9 are fixed to the output currents of the constant current sources 20 and 22, the change amount of the current flowing through the resistors 6 and 7 due to the change of the base voltage of the transistors 8 and 9 is determined. Is transistor 1
Appears as a change in collector current of 0 and 13.

That is, when the sum of the collector currents of the transistors 11 and 12 changes, the sum of the collector currents of the transistors 10 and 13 changes. In other words, the sum of the collector currents of the transistors 11 and 12 controls the sum of the collector currents of the transistors 10 and 13.

Therefore, by appropriately setting the resistance values of the resistors 6, 7 and 36, the sum of the collector currents of the transistors 11 and 12 and the sum of the collector currents of the transistors 10 and 13 can be made the same.

That is, the common mode voltage fluctuates due to non-linearity of the element, temperature change, etc.
Even if the sum of the collector currents of 2 fluctuates, the sum of the collector currents of the transistors 10 and 13 also fluctuates in synchronization therewith, so that the change of the common mode voltage is canceled.

As a result, the sum of the collector currents of one of the transistors forming each of the two differential circuits is connected to two diode-connected transistors, and the base voltage of the two transistors is applied to the cascode circuit 53. By providing the adjusting means 56, it is possible to cancel the common mode voltage fluctuation caused by the non-linearity of the element, temperature change, etc., and stabilize the common mode voltage in a wide band.

Although the variable voltage source 34 is used for adjusting the common mode voltage in FIGS. 1 and 2,
It may be a normal voltage source or ground.

[0071]

As is apparent from the above description,
The present invention has the following effects. By fixing the bias voltage of the cascode circuit and adjusting the voltage at the connection point of the two differential circuits, it is possible to realize a differential amplifier with wide band and high linearity.

Further, a current adjusting means for connecting the sum of collector currents of one of the transistors forming each of the two differential circuits to two diode-connected transistors and applying the base voltage of the two transistors to the cascode circuit. By providing the above, it is possible to cancel the common mode voltage fluctuation caused by the non-linearity of the element, the temperature change, etc., and stabilize the common mode voltage in a wide band.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram showing an embodiment of a differential amplifier according to the present invention.

FIG. 2 is a configuration circuit diagram showing another embodiment of the differential amplifier according to the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional differential amplifier.

[Explanation of symbols]

1, 2, 8, 9, 10, 11, 12, 13, 26, 2
7, 31, 32, 37, 38 Transistors 3, 4, 6, 7, 14, 15, 16, 17, 24, 2
5, 29, 30, 36 resistors 5, 20, 21, 22, 23, 28 constant current source 18, 19 buffer circuit 33 capacitance 34 variable voltage source 35 voltage source 50 operational amplifier 51, 54, 55 differential circuit 52 load resistor 53 Cascode circuit 56 Current adjusting means 100, 101 Input voltage 102, 102a, 102b, 103, 103a, 10
3b output voltage

Claims (4)

(57) [Claims] 1. In a differential amplifier, a first differential circuit to which two input voltages are connected, second and third differential circuits to which one output is respectively connected to a positive voltage source, and one end Is connected to a positive voltage source and the other end is connected to one output of the first differential circuit and the other output of the second differential circuit.
First resistor and a second resistor having one end and the other output of <br/> the connected to the other end to a positive voltage source first differential circuit and said third differential circuit is connected to be And a cascode circuit connected to the other ends of the first and second resistors of the load resistor , two constant current sources to which outputs of the cascode circuit are respectively connected, Two buffer circuits that are connected to the outputs of the cascode circuit and output an output voltage and that are connected to one of the input terminals of the second and third differential circuits; and the second and third differential circuits. A differential amplifier comprising: a first voltage source connected to the other input terminal; and a second voltage source for applying a bias voltage to the cascode circuit. 2. In a differential amplifier, a first differential circuit to which two input voltages are connected, one end connected to a positive voltage source and the other end to one output of the first differential circuit and the The other output of the second differential circuit is connected
First resistor and a second resistor having one end and the other output of <br/> the connected to the other end to a positive voltage source first differential circuit and said third differential circuit is connected to be And a cascode circuit connected to the other ends of the first and second resistors of the load resistor , two constant current sources to which outputs of the cascode circuit are respectively connected, Two buffer circuits that are connected to the outputs of the cascode circuits and output an output voltage and that are connected to one input terminals of the second and third differential circuits; and the second and third differential circuits. A first voltage source connected to the other input terminal; and a current adjusting unit connected to the other output of the second and third differential circuits to apply a bias voltage to the cascode circuit. Characteristic differential amplifier. 3. The differential amplifier according to claim 1, wherein a variable voltage source is used as the first voltage source. 4. The current adjusting means for connecting the other output of the second and third differential circuits to two diode-connected transistors, and applying the base voltage of the two transistors to the cascode circuit. The differential amplifier according to claim 2, which is used.