JP3428191B2 - Data communication method, transmitting device, and receiving device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication method, a transmitter and a receiver for realizing this communication method.

[0002]

2. Description of the Related Art In recent years, a control device for controlling various devices has a built-in arithmetic logic operation processing circuit such as a microcomputer (hereinafter, referred to as a microcomputer) and has been made intelligent. In addition, as such a control device, there has been proposed a device that performs control independently, and shares data with other control devices and centralizes data through a common signal line. For example, in a vehicle, a fuel injection control device, a suspension control device, a constant speed traveling control device, an automatic transmission control device, etc., which are mounted on the vehicle, are coupled via a common signal line to share vehicle speed data or the like. There is a system in which abnormal information (trouble code) from the control device is collected in the diagnosis control device, and these are collectively handled.

Transmission data and the like need to be exchanged between such a plurality of control devices or between a plurality of microcomputers within the same control device. As a method for realizing this, a transmission data communication method based on an asynchronous method is used. The receiver used is shown in Japanese Utility Model Laid-Open No. 2-1943. This is based on an integral multiple of a clock pre-arranged between transmitters and receivers for communication, and the transmission data is sampled and transmitted bit by bit. However, this method takes time to transmit and receive, and it is necessary to match the clock cycles of the transmitting side and the receiving side, so it was necessary to use high-precision oscillators such as crystal oscillators and ceramic oscillators. .

Therefore, as shown in JP-A-1-194599, a predetermined transmission clock is used to determine the pulse width (hereinafter, also simply referred to as the width) of one transmission data as a whole. A method has been proposed in which the signal is converted into a pulse signal and transmitted, and the receiving side decodes it into transmission data by measuring how many cycles of a predetermined reception clock the width of the received pulse signal corresponds to. There is. Further, in this method, the transmission data to be actually transmitted is arranged in the upper bits and the compensation data is arranged in the lower bits to form the transmission data. Therefore, transmission / reception can be performed in a shorter time than the start / stop synchronization method, and the transmission data can be accurately restored even if a measurement error that changes the portion corresponding to the lower bit of the transmission data, that is, the compensation data occurs.

Further, as a method different from this, Japanese Patent Laid-Open No.
There is one disclosed in Japanese Patent Publication No. 154428. This is also a method in which one transmission data is converted into a pulse signal having a pulse width corresponding to that value using a predetermined clock and then transmitted, and the receiving side measures the pulse width and decodes it into transmission data. , Here, the transmitting side transmits a pulse signal at a constant period, the receiving side measures not only the pulse width but also the transmitting period, and the ratio between the measured value and the reference value of the transmitting period is decoded. The clock error is corrected by multiplying the transmission data. According to this method, the difference between the transmission clock and the reception clock (hereinafter referred to as clock error) can be compensated.

[0006]

However, when performing data communication as described above, an error that does not depend on the clock error occurs. This is caused by the configuration existing on the signal line and causing a time delay.

In order to explain this, an example of the configuration of a communication device for performing the above-mentioned data communication is shown in FIG. The transmission side circuit of the communication device includes a microcomputer 79, a transistor 81,
It is composed of a base current control resistor 83 and an output protection resistor 85, and the microcomputer 79 has a timer output port 86. The receiving side circuit has pull-up resistors 87 and 8
9, a noise filter including a capacitor 91, a buffer 93 including an inverting circuit with hysteresis, a microcomputer 9
The microcomputer 94 includes a timer input port 95. Then, in both of these circuits, data communication becomes possible by connecting the output protection resistor 85 and the noise filter resistor 89 with the signal line 96. This communication device transmits and receives pulse signals by the following operations.

That is, when transmission data is set in the timer output port 86 of the transmission side microcomputer 79, the output value of the port rises and the transistor 81 connected via the base current control resistor 83 is turned on. Since the signal line 96 is connected to the power supply via the pull-up resistor 87 in the receiving side circuit, when the transistor 81 is off, the signal line 96 is maintained at substantially the power supply voltage and becomes a high level as a transmission signal. However, when the transistor 81 is turned on, a current flows through the path of the pull-up resistor 87, the signal line 96, and the transistor 81, so that the voltage of the signal line 96 decreases to the ground level and the transmission signal becomes low level. Then, when the time corresponding to the transmission data set in the timer output port 86 has elapsed, the output value of that port falls, the transistor 81 is turned off, and the transmission signal returns to the high level.

On the other hand, on the receiving side, the transmission signal thus changing is input to the buffer 93 via the noise filter. Since the buffer 93 is composed of a judgment circuit with hysteresis, the transmission signal is
Is binarized and inverted at. As a result, a pulse signal having the same polarity as the pulse signal output by the transmitting microcomputer 79 for turning on / off the transistor 81 is input to the receiving microcomputer 94. Receiving side microcomputer 9
4 has a timer input port 95 for receiving this pulse signal.
The timer input port 95 detects rising and falling edges of an input pulse and sequentially sets the time at that time in a register. Then, in the microcomputer 94, when the rising edge and the falling edge of the pulse signal (that is, the transmission signal) are detected by the timer input port 95, the rising edge time and the falling edge time stored in the register are detected by so-called edge interrupt processing. The transmission signal is restored to data by reading each and obtaining the difference between these times.

However, since a noise filter or the like is arranged in such a data transmission system, the pulse signal input to the buffer 93 is distorted as shown in FIG. 6 (b). When the signal is distorted, the signal input to the microcomputer 94 is as shown in FIG.
As shown in (c), the pulse width tin becomes longer than the pulse width tR at the time of transmission (hereinafter, this lengthened amount is called a delay error).

The magnitude of this delay error depends on the height of the pulse signal, the output protection resistor 85, the pull-up resistor 87,
Since it is determined by the thresholds of the resistor 89 / capacitor 91 for the noise filter and the buffer 93, it does not fluctuate according to the clock error.
Compensation cannot be performed by the method disclosed in Japanese Patent Publication No. 154428. Further, since the signal line 96 also has the stray capacitance 97, this also affects the degree of distortion. As described above, since many factors that delay the reception of the pulse signal are uncertain, the time constant of the entire communication path cannot be specified.

Further, since the delay error is determined by the height of the pulse signal, the output protection resistance 85, ..., And the like, compared with the clock error caused by the accuracy error of the oscillator such as a crystal oscillator, the delay error of each communication device is increased. The variation is large. Therefore, if the delay error is to be compensated by the method disclosed in Japanese Patent Laid-Open No. 1-194599, the number of digits of the compensation data generated in the lower bits of the transmission data must be increased, and the data to be transmitted must be increased. The ratio of transmitted data to the total is reduced, resulting in poor efficiency. In addition, the number of digits of compensation data is 1
If the number of pulses is increased, the entire pulse width becomes twice as long, and there is a possibility that the transmission cycle is extended, that is, the transmission speed is reduced.

The present invention has been made in view of the above problems, and a data communication method and a transmission / reception method capable of accurately compensating for a clock error and a delay error that occur when communication is performed between different microcomputers, and performing accurate pulse width communication. An object is to provide a receiving device.

[0014]

In order to solve the above-mentioned problems, the invention according to claim 1 has a width on the transmission side, in which the transmission data has a width corresponding to the value thereof, based on a predetermined transmission clock. In the data communication method of converting the transmission pulse signal and transmitting it, the receiving side measures the width of the received transmission pulse signal with reference to a predetermined reception clock, and restores the transmission data from the measurement result. , At least prior to the transmission of the transmission data, first and second correction pulse signals corresponding to first and second correction data having different preset values are generated, and these are arranged in this order. Then, the receiving side discriminates whether the received pulse signal is the first correction pulse signal, the second correction pulse signal, or the transmission pulse signal, and the received pulse signal is received. When the loose signal is the first correction pulse signal, the first correction data is generated from the pulse width of the first correction pulse signal, and the received pulse signal is the second correction pulse signal. In this case, the second correction data is generated from the pulse width of the second correction pulse signal, and the generated first and second correction data and the reference value of the first and second correction data are generated. Based on the above, a clock error indicating the degree of mismatch between the transmission clock and the reception clock is obtained, and based on the clock error, the generated first or second correction data, and the reference value of the correction data,
Obtain the delay error representing the delay of the data transmission system, and if the received pulse signal is the transmission pulse signal,
It is characterized in that the pulse width of the received transmission pulse signal is corrected on the basis of the clock error and the delay error obtained as described above to restore the transmission data.

The invention according to claim 2 is the same as that of A in FIG.
As illustrated in the section, using the transmission clock generating means for generating a predetermined transmission clock and the transmission clock generated by the transmission clock generating means, the transmission data is converted into a transmission pulse signal having a width corresponding to the value. In a transmitting device comprising: an encoding unit for transmitting the transmission pulse signal generated by the encoding unit to a signal line, a transmission device for transmitting the transmission pulse signal from the pulse signal transmitting unit. Prior to the above, the encoding means sequentially outputs the first and second correction data that can be discriminated from the transmission data, and the encoding means converts both of them into first and second correction pulse signals. Correction data generating means for sequentially transmitting the first and second correction pulse signals from the pulse signal transmitting means.

The invention according to claim 3 is a receiving device which receives a pulse signal by being connected to the transmitting device according to claim 2 via a signal line, as illustrated in the section B of FIG. A pulse signal receiving means for receiving the pulse signal, a reception clock generating means for generating a predetermined reception clock,
Decoding means for measuring the pulse width of the pulse signal received by the pulse signal receiving means using the reception clock generated by the reception clock generating means, and restoring data from the measurement result, and restoration by the decoding means Pulse signal determining means for determining whether the pulse signal received by the pulse signal receiving means is the first correction pulse signal, the second correction pulse signal, or the transmission pulse signal based on the result;
When the pulse signal determination means determines that the pulse signal is the second correction pulse signal, the decoding means restores the first and second correction pulse signals to the first and second correction pulse signals, respectively. And a clock error calculating means for calculating a clock error indicating a degree of disagreement between the transmission clock and the reception clock based on the correction data and the preset reference values of the first and second correction data. A delay error representing a delay of the data transmission system is calculated based on the clock error calculated by the means, the first or second correction data restored by the decoding means, and the reference value of the correction data. When the delay error calculating means and the pulse signal determining means determine that the pulse signal is a transmission pulse signal, the decoding means restores the transmission pulse signal. The transmission data, characterized by comprising a transmission data correcting means for correcting, based on the calculated clock error and delay error in each error calculation means.

Next, the invention of claim 4 is the same as that of claim 3.
In the receiving device described in the above item (1), the clock error calculating means calculates a deviation between the first correction data and the second correction data restored by the decoding means from a reference value of the first correction data and a second value. The clock error is calculated by dividing the correction data by the deviation from the reference value, and the delay error calculating means corrects the clock error from the first or second correction data restored by the decoding means. The delay error is calculated by subtracting the product of the reference value of the data and the calculated clock error.

On the other hand, the invention described in claim 5 is the invention according to claim 2.
In the transmitting device described in the paragraph 1,
As the first and second correction data, the encoding means 2
ⁿ , 2 ^n-1 It is characterized by outputting a value corresponding to.
The invention according to claim 6 is the transmission according to claim 5.
Connected to the device via signal line to receive pulse signal
The receiving device according to claim 4, wherein the clock error is
The difference calculating means is the first decoder restored by the decoding means.
The deviation between the correction data of 2 and the correction data of
By shifting in the direction of lower bits by
The delay error calculating means for calculating the clock error
Is the first correction data restored by the decoding means.
Data, the clock error calculated above is increased by n bits.
By subtracting the data that is shifted in the order of bits,
It is characterized in that the delay error is calculated.

Next, the invention according to claim 7 is the invention according to claim 2.
Alternatively, in the transmitting device according to claim 5, the correction data generating means generates a value larger than the maximum value of the transmission data as the first correction data. Further, the invention according to claim 8 is connected to the transmitting device according to claim 7 via a signal line to receive a pulse signal, and the transmitting device according to claim 3, claim 4, or claim 6. In the receiving device, the pulse signal determination means, when the restored data restored by the decoding means is larger than a preset maximum value of the transmission data,
The pulse signal receiving means has first pulse determining means for determining that the pulse signal received is the first correction pulse signal, and the pulse signal receiving means receives the pulse signal immediately after the first pulse determining means determines the first correction pulse signal. It is characterized in that the generated pulse signal is determined as a second correction pulse signal, and the pulse signals received after the second correction pulse signal are transmission pulse signals.

[0020]

In the data communication method according to the first aspect of the present invention, the transmitting side precedes the transmission of the transmission data by the first correction data having different preset values, After converting the second correction data into a first correction pulse signal and a second correction pulse signal each having a width corresponding to each value, these are converted into a first correction pulse signal and a second correction pulse signal.
The correction pulse signals are transmitted in the order.

On the receiving side, it is discriminated whether the received pulse signal is the first correction pulse signal, the second correction pulse signal or the transmission pulse signal. If it is the first correction pulse signal, the first correction data is generated by measuring the pulse width, and if it is the second correction pulse signal, the pulse width is measured. The second correction data is generated and transmitted based on the generated second correction data, the first correction data generated at the time of determining the first correction pulse signal, and the reference value of each of these correction data. Based on the clock error, the clock error, the first or second correction data generated from the received pulse signal, and the reference value of the correction data,
Obtain the delay error that represents the delay of the data transmission system, and if the received pulse signal is the control pulse signal, measure the pulse width of the transmission pulse signal and calculate the pulse width, clock error, and delay error. Restore the transmitted data based on.

This is because the transmission data from the transmission side is tR,
When the data received and restored on the receiving side is tin, the relationship between these values is based on the following equation (1) using the clock error Eclk and the delay error Edly. . tin = tR.Eclk + Edly (1) That is, the clock error Eclk and the delay error Edly are different for each communication system and cannot be uniquely specified, but two transmission data whose data values are known from the transmission side are known. If tR1 and tR2 are transmitted and the receiving side receives and restores them, the restored data Tin1 and Tin2 and the transmission data t
From R1 and tR2, the clock error Eclk and the delay error Edly can be calculated by the following equations (2) and (3).

Eclk = (Tin1−Tin2) / (tR1−tR2) (2) Edly = Tin1−tR1 · Eclk = Tin2−tR2 · Eclk (3) Therefore, in the present invention, it is preset from the transmission side. By sequentially transmitting pulse signals having pulse widths corresponding to the first and second correction data tR1 and tR2 and restoring the first and second correction data tin1 and tin2 from these pulse signals on the receiving side, respectively. , The parameters for obtaining the clock error Eclk and the delay error Edly are obtained, and the clock error Eclk and the delay error Edly are used by using these parameters.
To identify. Then, the value tin obtained by restoring the transmission data transmitted from the transmission side thereafter is set to each of these values E
By using clk and Edly for correction as in the following equation (4), the receiving side can obtain accurate data Tin corresponding to the transmission data tR from the transmitting side.

Tin = tR = (tin−Edly) / Eclk (4) Therefore, according to the present invention, the error component (due to the deviation between the transmission clock and the reception clock and the delay of the data transmission system on the receiving side ( Accurate transmission data can be restored by removing the clock error and delay error. Therefore, it is possible to use inexpensive and low-precision devices for generating the transmission clock and the reception clock on the transmitting side and the receiving side, respectively. Further, since the error component due to the delay error can be removed, it is not necessary to consider the stray capacitance of the signal line forming the data transmission system, and the wiring having a high degree of freedom can be realized. Further, by compensating for the delay error in this way, the time constant of the noise filter can be freely selected, and a communication device resistant to noise can be realized.

In the transmitting device according to the second aspect, the encoding means converts the transmission data into a pulse signal having a width corresponding to the value by using the transmission clock generated by the transmission clock generating means, and the pulse signal is generated. The signal transmitting means sends the pulse signal to the signal line. Further, the correction data generation means, prior to the transmission of the transmission pulse signal from the pulse signal transmission means,
The first and second correction data that can be distinguished from the transmission data are sequentially output to the encoding means. As a result, the encoding means sequentially converts the first and second correction data into the first and second correction pulse signals, and the pulse signal transmitting means
The first and second correction pulse signals are sequentially transmitted.

That is, in the transmitting device according to the second aspect, the transmission data is converted into a pulse signal having a width corresponding to the value and transmitted to the signal line, and the transmission data is transmitted prior to the transmission of the transmission data. The first correction data and the second correction data which can be discriminated from are sent as the first correction pulse signal and the second correction pulse signal, respectively.

On the other hand, the receiving device described in claim 3 is connected to the transmitting device described in claim 2. The pulse signal receiving means receives the pulse signal transmitted from this transmitting device, and the encoding means measures the pulse width of this pulse signal using the reception clock generated by the reception clock generating means. Thus, the data corresponding to the pulse width is restored.

Further, as described above, the transmitter first sequentially transmits the first and second correction pulse signals corresponding to the first and second correction data as the pulse signal, and then the transmission data is converted into the transmission data. Corresponding pulse signals are transmitted, but in the receiving apparatus, the pulse signal determination means uses the received pulse signal as the first correction pulse signal and the second correction pulse based on the data obtained by the decoding means. It is determined whether it is a pulse signal or a transmission pulse signal.

When the pulse signal determining means determines that the received pulse signal is the second correction pulse signal, the clock error calculating means causes the decoding means to determine the first and second correction pulse signals. The clock error is calculated based on the first and second correction data restored from the above and the preset reference values of the first and second correction data, and the delay error calculating means further calculates the clock error. The recovered clock error and the first or second restored by the decoding means.
Based on the correction data of and the reference value of this correction data,
The delay error is calculated.

Further, when the pulse signal determination means determines that the received pulse signal is the transmission pulse signal obtained by encoding the transmission data, the transmission data correction means restores the decoding means from the transmission pulse signal. The generated transmission data is corrected based on the clock error and the delay error previously calculated by the clock error calculating means and the delay error calculating means.

That is, the data communication method according to claim 1 can be realized by combining the transmitting device according to claim 2 and the receiving device according to claim 3, and the transmission data restored on the receiving device side. Therefore, the clock error and the delay error can be reliably removed. Therefore, even if there is a clock generation error between the transmission clock generation means on the transmission device side and the reception clock generation means on the reception device side, data communication can be satisfactorily performed, and each of these clock generation means can operate. It is not necessary to use a high-precision oscillator and can be realized at low cost. Further, since the error component due to the delay error is also removed, it is not necessary to consider the stray capacitance existing in the signal line connecting the transmission device and the reception device, and the wiring with a high degree of freedom becomes possible.

Next, in the receiving apparatus according to the fourth aspect, the clock error calculating means calculates the deviation between the first correction data and the second correction data restored by the decoding means as the first correction data. Of the second correction data and the reference value of the second correction data, the clock error is calculated, and the delay error calculating means calculates the clock error from the first or second correction data restored by the decoding means. The delay error is calculated by subtracting the product of the reference value of this correction data and the clock error. That is, the receiving apparatus of the present invention calculates the clock error and the delay error by directly using the equations (2) and (3).

Therefore, the clock error and the delay error can be accurately calculated. Further, even if the first and second correction data (correction pulse) is changed due to a change in the specifications of the connected transmission device, it can be easily dealt with by simply changing the value of the reference value in the above equation. , For example,
Compared with the case where the clock error and the delay error are obtained by using the error calculation maps corresponding to the above equations (2) and (3), the capacity of the storage element for storing the calculation data is Not only can it be reduced, but the versatility of the receiving device can be improved.

On the other hand, in the transmitting apparatus according to the fifth aspect, the correction data generating means outputs the values corresponding to 2 ⁿ and 2 ^n-1 to the encoding means as the first and second correction data. To do. As a result, in the encoding means, pulse signals having pulse widths corresponding to 2 ⁿ and 2 ^n-1 are generated as the first and second correction pulse signals, and the pulse signals are sequentially output from the correction data generating means. Will be output.

Further, in the receiving device according to claim 6 which receives the pulse signal from the transmitting device according to claim 5, the clock error calculating means includes the first correction data and the first correction data restored by the decoding means. The deviation from the second correction data is shifted by n−1 bits in the lower bit direction to calculate the clock error, and the delay error calculation means uses the first correction data restored by the decoding means to obtain: The delay error is calculated by subtracting the data obtained by shifting the calculated clock error by n bits in the upper bit direction.

That is, when a pulse signal having a pulse width corresponding to 2 ⁿ , 2 ^n-1 is transmitted from the transmitting device as the first and second correction pulse signals, the first and second correction data of The deviation of the standard value is 2 ^n-1 (= 2 ⁿ -2 ^n-1 )
Becomes Then, the division by 2 ^n-1 is only required to shift the value (data) to be divided by n−1 bits in the lower bit direction. Therefore, in calculating the clock error using the above equation (2), the clock error calculating means calculates the deviation between the first and second correction data by n-1.
It shifts by the amount of bits toward the lower bits.

Further, when the delay error is calculated from the clock error, the first correction data and the reference value thereof using the equation (3), it is necessary to multiply the clock error and the reference value. but the reference value of the first correction data is 2 ^n, the multiplication of 2 ^n, since to be multiplied value (data) need only be shifted to the upper bit direction n bits,
The delay error calculating means shifts the clock error by n bits in the upper bit direction in calculating the delay error using the above equation (3), thereby multiplying the clock error by the reference value of the first correction data. Is obtained, and this value is subtracted from the first correction data restored by the decoding means.

Therefore, by combining the transmitting device described in claim 5 and the receiving device described in claim 6, it becomes possible to easily calculate the clock error and the delay error by using the shift operation. , The calculation can be performed at high speed. Further, the load on the arithmetic circuit such as the CPU used for this arithmetic can be reduced.

Next, in the transmitting device according to the seventh aspect, the correction data generating means sets the first correction data as
A value larger than the maximum value of the transmission data is generated. That is, the pulse signal generated from this transmitting device can determine the first correction data by measuring the pulse width and determining whether the restored data is larger than the maximum value of the transmission data. . The second correction data can be determined because it is transmitted after the first correction data, and the transmission data can be determined because it is further received after that.

On the other hand, in the receiving device described in claim 8, the first pulse judging means connected to the transmitting device described in claim 7 and provided in the pulse signal judging means is restored by the decoding means. When the restored data is larger than the maximum value of the transmission data, it is determined that the received pulse signal is the first correction pulse signal, and the pulse signal determination means makes the first correction by the first pulse determination means. The pulse signal received immediately after determining the pulse signal is the second correction pulse signal,
The pulse signal received after the second correction pulse signal is determined as the transmission pulse signal.

Therefore, if the communication device according to claim 7 and the receiving device according to claim 8 are combined, the receiving device restores the restored data restored by the restoring means and the maximum value of the transmitted data. It is possible to determine the first correction pulse signal, the second correction pulse signal, and the transmission pulse signal very simply by only comparing the order of reception and the order of reception.

[0042]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows an engine control device 1 according to the communication method of the present invention.
It is a schematic block diagram which shows the whole structure of the apparatus which performs data communication between (hereinafter, engine ECU1) and transmission control apparatus 3 (henceforth transmission ECU3).

The engine ECU 1 is a well-known CPU, RA
A microcomputer 11 mainly composed of M and ROM for performing arithmetic logic operation processing, an AD converter 13 for converting an analog signal into a digital pulse signal sequence, and a rectangular wave for an external signal within an allowable voltage range of the microcomputer 11. An input circuit 14 for converting the output of the microcomputer 11, an output circuit 15 for amplifying the output of the microcomputer 11, a crystal oscillator 16 for generating a reference clock defining the operation timing of the microcomputer 11, a communication circuit 17, A power supply voltage VDD is supplied to each of these parts, and a power supply circuit 18 that generates a reset signal for the microcomputer 11 when the power is turned on is provided.

Of these, the microcomputer 11 has an AD
A serial port 21 connected to the converter 13 for exchanging signals, an input / output port 23 connected to the input circuit 14 and the output circuit 15 for exchanging data, and an operation of the microcomputer 11 connected to the crystal oscillator 16. A clock generator 25 that generates a reference clock that defines timing, and a timer port 27 that is connected to the communication circuit 17.
Is equipped with.

Engine ECU 1 having such a configuration
Is an air flow meter 53 that detects the intake air amount, a water temperature sensor 57 that detects the engine cooling water temperature, an intake air temperature sensor 59 that detects the intake air temperature, an oxygen concentration sensor 61 that detects the oxygen concentration in the exhaust gas, and a throttle opening degree. The detection signal from the throttle opening sensor 63 or the like for detection is fetched through the AD converter 13, and the distributor 55
The output pulse from the rotation speed sensor provided in the engine, the detection signal from the idle switch provided in the throttle opening sensor, etc. are fetched through the input circuit 14, and the microcomputer 11
Then, using these detection signals, the fuel injection amount from the injector 65 for injecting fuel into the engine and the high voltage generation timing of the igniter 67 for applying the high voltage for ignition to the spark plug of the engine (ignition timing ) Is calculated, and a control signal corresponding to the calculation result is output to the injector 65 and the igniter 67 via the output circuit 15.

On the other hand, the transmission ECU 3 is mainly composed of a CPU, a RAM, and a ROM, similar to the engine ECU 1, and has a microcomputer 31 for performing arithmetic logic operation processing.
An input circuit 34 for converting an external signal into a rectangular wave in the allowable voltage range of the microcomputer 31, an output circuit 35 for amplifying the output of the microcomputer 31, and a reference clock for defining the operation timing of the microcomputer 31. For this purpose, a crystal oscillator 36, a communication circuit 37, and a power supply circuit 38 that supplies a power supply voltage VDD to each of these parts and that generates a reset signal for the microcomputer 11 when the power is turned on are provided.

Among them, the microcomputer 31 is internally connected to the input circuit 34 and the output circuit 35 for exchanging data and the crystal oscillator 36, and defines the operation timing of the microcomputer 31. There is provided a clock generator 45 for generating a reference clock to be operated, and a timer port 47 connected to the communication circuit 37.

Then, the transmission ECU 3
Pattern select switch 6 for changing the shift pattern
9. Signals from the range changeover switch 71 for changing the range of the transmission, the vehicle speed sensor 73 for detecting the speed of the vehicle, etc. are taken in through the input circuit 34, and the microcomputer 31 uses the signals to detect the automatic transmission. The shift position, the necessity of lockup, etc. are calculated, and drive signals corresponding to the calculation results are output to the shift solenoid valve 75 and the lockup solenoid valve 77 via the output circuit 35, respectively.

The engine ECU 1 uses the various detection signals as described above when calculating the fuel injection amount and the ignition timing, and also based on the shift position of the automatic transmission calculated by the transmission ECU 3 and the like. The timing may be corrected. On the other hand, the transmission ECU 3
In addition to the above input signals, the throttle opening and cooling water temperature values input to the engine ECU 1 are used to determine the shift position and the necessity of lockup. Therefore, the engine ECU 1 and the transmission ECU 3 are connected by a signal line 5 for exchanging information such as gear shift position, throttle opening, cooling water temperature and the like. In addition,
This signal line 5 is used for communication circuits 17, 3 in each ECU 1, 3.
7, the communication circuits 17 and 37 are configured as shown in FIG.
Although it is configured as a bidirectional communication circuit including both the transmitting side circuit and the receiving side circuit shown in FIG. 5, each circuit for transmitting and receiving is the same as that in FIG.
By the way, in such a system, if an attempt is made to transmit the throttle opening from the engine ECU 1 to the transmission ECU 3, for example, the throttle opening encoded in the pulse signal by the engine ECU 1 and the transmission ECU 3 via the signal line 5 It does not usually match the received and decoded throttle opening. This is because the throttle opening decoded on the transmission ECU 3 side has an error (clock error) in the frequency of the reference clock in each ECU 1, 3 and the stray capacitance of the signal line 5 and a noise filter in the communication circuit. This is because it is affected by a data transmission delay (delay error) caused by.

Therefore, in this embodiment, the engine ECU 1
The transmission ECU 3 compensates for these errors by performing the following transmission / reception processing. In the following explanation,
The transmission side will be described as the engine ECU 1 and the reception side as the transmission ECU 3, but these ECUs 1, 3 will be described.
Are capable of bidirectional communication with each other, and therefore, in reality, the following transmission / reception processing is executed in each of the ECUs 1 and 3.

First, in the initialization process shown in the flowchart of FIG. 3, the flag fcor indicating that the correction pulse signal is being input is cleared (step 100: the step is hereinafter referred to as S) and the flag indicating the end of the correction pulse signal output. finit1,
Flag finit2 indicating the end of output of the first correction pulse signal
Is set to 0 (S200). This processing is executed in each of the microcomputers 11 and 31 after reset release.

After that, the engine ECU 1 transmits a pulse signal having a width corresponding to the value of the data to be transmitted in the timer interrupt processing routine executed at regular intervals. That is, first, in S200, it is determined whether the flag finit1 is in the reset (0) state. If the flag finit1 is reset, the process proceeds to S210, and the flag fin
Check the state of it2. Then, if the flag finit2 is reset, in S220, the first correction data tR1 stored in advance in the RAM of the microcomputer 11 is set in the timer port 27 in order to output the first correction pulse signal. In subsequent S230, the flag finit2 is set (1).

On the other hand, if it is determined in S210 that the flag finit2 is set, in S240, the second correction pulse signal stored in advance in the RAM of the microcomputer 11 is output in order to output the second correction pulse signal. The correction data tR2 is set in the timer port 27, and the flag finit1 is set in S250.

If it is determined in S200 that the flag finit1 is set, in S260, data (transmission data) such as the throttle opening to be transmitted to the transmission ECU 3 is set in the timer port 27,
The timer interrupt processing routine ends.

Here, the first and second correction data tR1,
tR2 is the transmission EC from the engine ECU1
This is for setting the pulse widths of the first and second correction pulse signals transmitted to U3, and is set to different values in advance so that the pulse widths of these pulse signals have different predetermined values. The first correction data tR1 is input to the transmission ECU 3 when the delay error and the clock error also become maximum when the data (transmission data) such as the throttle opening that should be originally transmitted to the ECU 3 is maximum. The pulse width of the first correction pulse signal is set to be longer than the pulse width (maximum pulse width) tmax of the pulse signal to be generated.

Further, the values of these correction data tR1 and tR2 are used as the reference values of the correction data obtained by restoring the first correction pulse signal and the second correction pulse signal on the transmission ECU 3 side, respectively. 31 RA
It is stored in M. Then, as described above, S220,
When the first correction data tR1, the second correction data tR2, or the transmission data indicating the throttle opening is set in the timer port 47 in S240 or S260, the output signal of the timer port 27 changes to that The set data value and the output cycle of the reference clock from the clock generator 25 are held at a high level for a predetermined time, and the communication circuit 17 outputs a pulse having a pulse width corresponding to the set data value. The signal is sent to the signal line 5.

That is, according to the timer interrupt processing routine on the transmitting side, first, the first correction pulse signal corresponding to the first correction data tR1 is output at regular intervals.
Then, the second correction pulse signal corresponding to the second correction data tR2 is output, and thereafter, the transmission pulse signal corresponding to the transmission data such as the throttle opening is output.

In this embodiment, when the engine ECU 1 operates as a transmitter as described above, the crystal oscillator 16 and the clock generator 25 are transmission clock generating means, the timer port 27 is an encoding means, and a communication circuit. Reference numeral 17 serves as a pulse signal transmitting means, and the series of processes for transmitting the correction pulse in steps 200 to 250 corresponds to the correction data generating means.

On the other hand, on the transmission ECU 3 side that receives the transmission data from the engine ECU 1, the received pulse signal is decoded by the processing shown in the flowchart of FIG. Note that this process is performed by the timer port 47.
Is an edge input interrupt process, which is activated each time the edge detection circuit provided in is detected an edge of the pulse signal received by the communication circuit 37 as the pulse signal receiving means. Further, when the edge detection circuit detects an edge of the received signal, the timer port 47 causes the timer built in the microcomputer 31 to count the reference clock from the clock generator 47 serving as the received clock generating means to keep the normal time. The present time which is present is stored in the register as the interrupt occurrence time.

As shown in FIG. 4, when this process is activated, it is determined whether the edge of the received pulse detected by the edge detection circuit is a rising edge. If it is a rising edge, the process proceeds to S310. Then, the interrupt occurrence time stored in the register is stored in the RAM as the rising time Zr.

On the other hand, if it is determined in S300 that the edge of the received pulse is not the rising edge (that is, if it is the falling edge), in S320, the interrupt generation time corresponding to this falling edge is set from the register. The pulse width tin of the received pulse signal is obtained by reading and subtracting the rising time Zr previously stored in the RAM from this interrupt occurrence time, and stored in the RAM. Note that the processing of these steps 300 to 320 corresponds to the decoding means on the receiving device side.

Then, in the following S330, the flag fcor is checked to determine whether the correction pulse signal is being input. If the flag fcor is reset, it is determined that the correction pulse signal is not being input, and the process proceeds to S340. In order to determine whether or not the pulse signal input this time is the first correction pulse signal, the pulse width tin of the reception pulse stored in the RAM in S320 is the maximum pulse of the transmission data stored in advance in the RAM. Determine if it is greater than the width tmax,
The processing as the first pulse determination means is executed.

At S340, the pulse width tin of the received pulse
Is determined to be larger than the maximum pulse width tmax, it is determined that the pulse signal received this time is the first correction pulse signal, and the pulse width tin is stored in the RAM as the first correction data Tin1 in S350. , S360, after setting the flag fcor, the process is once ended.

On the other hand, if it is determined in S330 that the flag fcor is set, it is determined in S370 that the pulse signal received this time is the second correction pulse signal, and obtained in S320. The pulse width tin is stored in the RAM as the second correction data Tin2.

Then, in S380, based on the second correction data Tin2, the first correction data Tin1 already stored in the RAM, and the preset reference values tR1 and tR2 of these correction data. The clock error Eclk is calculated by using the above equation (2), and the clock error Eclk is calculated, and the calculated clock error Eclk and the first correction data Tin1 in the RAM and its Based on the reference value tR1, the processing as the delay error calculating means for calculating the delay error Edly using the above-mentioned formula (3) is executed. And then S39
At 0, the flag fcor is reset, and the processing is once ended.

On the other hand, if it is determined in S340 that the pulse width tin of the received pulse signal is less than or equal to the maximum pulse width tmax of the transmission data, the process proceeds to S400. And
In S400, it is determined that the pulse signal received this time is transmission data representing the throttle opening degree, and the pulse width tin of this pulse signal and the clock error E obtained in S380.
Based on the clk and the delay error Edly, the pulse width tin is corrected by using the above-mentioned equation (4), and the processing as the transmission data correcting means for restoring the transmission data is executed, and the processing is once ended.

As described above, in the transmission ECU 3 which receives the transmission pulse from the engine ECU 1, after the system is started, the engine ECU 1 side
First, a first correction pulse signal having a pulse width larger than that of a normal transmission pulse signal is transmitted, then a second correction pulse signal is transmitted, and then a transmission pulse signal corresponding to transmission data such as throttle opening. Will be sent,
The first correction pulse signal is determined by determining whether the pulse width tin of the received pulse is greater than or equal to the maximum pulse width tmax (S340), and the pulse signal received next is determined as the second pulse signal.
Of the correction pulse signals, the pulse widths of these correction pulse signals are the first correction data Tin1 and the second correction data T
Once stored in RAM as in2 (S350, S37
0), based on these correction data Tin1 and Tin2 and the preset reference values tR1 and tR2, the clock error E
clk and delay error Edly are obtained (S380), and the pulse width tin of the pulse signal received thereafter is corrected by these error components Eclk and Edly (S400) to restore the transmission data tR.

Therefore, according to this embodiment, on the transmission ECU 3 side, the transmission data representing the throttle opening etc. transmitted from the engine ECU 1 is accurately restored without being affected by the clock error and the delay error. be able to. Therefore, according to this embodiment, each E
Even if the reference clocks cannot be matched due to variations in the oscillation periods of the crystal oscillators 16 and 36 used to generate the reference clocks in the CUs 1 and 3 and the characteristics of the clock generators 25 and 45, Communication can always be performed accurately, and inexpensive, low-precision parts can be used for these parts.

Further, according to this embodiment, the delay error influenced by the characteristics of the data transmission system such as the signal line 5 and the communication circuits 17 and 37 is also calculated to correct the data on the receiving side. Therefore, the communication accuracy can be compensated even for the delay error, the consideration of the stray capacitance of the communication line 5 becomes unnecessary, and the degree of freedom of wiring in the vehicle increases. Moreover, since the time constant of the filter of the input circuit 34 can be freely selected, the noise resistance of the communication system can be improved.

In the above embodiment, the case where the first correction pulse signal and the second correction pulse signal are transmitted once after reset release is explained. However, depending on the temperature characteristic of the time constant of the filter of the communication circuit. If the amount of change has a significant effect that cannot be ignored, the correction pulse signal should be corrected multiple times, for example, when the engine is in idle operation, and it is determined that the region in which the amount of change in the series of data is small is small. May be sent to. In this way, accurate communication can be performed regardless of changes in the outside world.

Further, for example, the first and second correction data
2 for tR1 and tR2, respectivelyⁿ , 2 ^n-1 The value corresponding to
By setting, the transmitter (in the above description, the engine
From the ECU1) side, set the reference clock cycle to 2ⁿ Double, 2
^n-1 The doubled pulse signal is used for the first and second correction pulse signals.
If each is sent as a signal, the receiving device (the above
In the case of Ming, the clock error on the transmission ECU 3) side
And high-speed processing operation when calculating the delay error.
I can.

That is, with this configuration, the receiving device
Side, measure the pulse width of the first and second correction pulse signals.
And calculate the clock error using the above equation (2).
In this case, the deviation of the reference value of the first and second correction data (tR1
-TR2) is 2^n-1 Therefore, the pulse width of each correction pulse
Deviation (Tin1-Tin2) of the lower order by n-1 bits.
Calculation of clock error.
Can be done easily. Also, this clock error
And the first correction data Tin1 and its reference value tR1
In calculating the delay error using the above equation (3),
Therefore, when multiplying the clock error and the reference value tR1,
Shifts the clock error by n bits in the upper bit direction.
You can easily calculate the delay error because you only need to shift
Can be done. Therefore, the first and second correction data
As tR1 and tR2, 2 respectivelyⁿ , 2 ^n-1 The value corresponding to
By setting, the clock error and delay error can be calculated.
It can be performed at high speed, and the receiver side C
It is possible to reduce the load on the PU.

In the above embodiment, the clock error is calculated using the arithmetic expression (2), but a table for reference to the clock error is created in advance based on the arithmetic expression (2). Incidentally, at the time of actual communication, the clock error may be obtained using this table instead of using the arithmetic expression (2). In this way, the clock error can be obtained at high speed only with the time required to refer to the table. Similarly, a table may be created for the delay error and the delay error may be obtained from this table.

In the above embodiment, the engine ECU 1
The case where the data communication is performed between the transmission ECU 3 and the transmission ECU 3 has been described.
Any system can be applied as long as it is a system that performs data communication with a pulse width in between. For example, it can be applied to communication between the engine ECU and the control control device of the engine valve, communication between the engine ECU and the control device of the air conditioner, and the like. Further, the communication is applicable not only to bidirectional communication but also to unidirectional communication.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a transmitter and a receiver according to the present invention.

FIG. 2 is a schematic configuration diagram showing an overall configuration of a communication system according to an embodiment.

FIG. 3 is a flowchart showing an initialization process and a timer interrupt process executed for data transmission on the transmitting device side of the embodiment.

FIG. 4 is a flowchart showing an edge input interrupt process executed for data reception on the receiving device side of the embodiment.

FIG. 5 is an explanatory diagram showing a configuration of a conventional and a communication circuit.

FIG. 6 is an explanatory diagram showing an output signal from a transmitting side microcomputer and a change in pulse width when this signal is input to a receiving side microcomputer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Engine ECU 3 ... Transmission ECU 5 ... Signal line 11, 31 ... Microcomputer 26, 56 ... Crystal oscillator 17, 37 ... Communication circuit 27, 47 ... Clock generator

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-3-154428 (JP, A) JP-A-1-194599 (JP, A) JP-A-5-199125 (JP, A) JP-A-6- 216946 (JP, A) Actual development 2-1943 (JP, U) Actual development 3-6352 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/00 H04L 7 / 02 H04L 25/03 H04L 25/49 H03M 5/08

Claims (8)

(57) [Claims] 1. A transmission side converts transmission data into a transmission pulse signal having a width corresponding to the value based on a predetermined transmission clock and transmits the transmission pulse signal, and a reception side uses a predetermined reception clock as a reference. In the data communication method of measuring the width of the received transmission pulse signal and restoring the transmission data from the measurement result, on the transmission side, at least prior to the transmission of the transmission data, the preset values are different from each other. 1st and 2nd
The first and second correction pulse signals corresponding to the correction data are generated and transmitted in this order. At the receiving side, the received pulse signal is the first correction pulse signal and the second correction pulse signal. It is determined which of the pulse signal and the transmission pulse signal, and if the received pulse signal is the first correction pulse signal, the first pulse width is determined from the pulse width of the first correction pulse signal.
Correction data is generated, and if the received pulse signal is the second correction pulse signal, the pulse width of the second correction pulse signal is changed to the second correction pulse signal.
And a clock error indicating the degree of mismatch between the transmission clock and the reception clock based on the first and second correction data generated above and the reference value of the first and second correction data. Further, based on the clock error, the generated first or second correction data, and the reference value of the correction data, a delay error indicating a delay of the data transmission system is calculated, and the received pulse signal is In the case of a transmission pulse signal, the pulse width of the received transmission pulse signal is corrected based on the clock error and the delay error thus obtained, and the transmission data is restored. 2. A code for converting transmission data into a transmission pulse signal having a width corresponding to the value by using transmission clock generation means for generating a predetermined transmission clock and transmission clock generated by the transmission clock generation means. And a pulse signal transmitting means for transmitting the transmission pulse signal generated by the encoding means to a signal line, prior to transmission of the transmission pulse signal from the pulse signal transmitting means. First and second correction data that can be discriminated from the transmission data are sequentially output to the encoding means, and both are converted into first and second correction pulse signals by the encoding means. A transmitter, comprising correction data generating means for sequentially transmitting the first and second correction pulse signals from the pulse signal transmitting means. 3. A receiving device, which is connected to the transmitting device according to claim 2 through a signal line to receive a pulse signal, comprising pulse signal receiving means for receiving the pulse signal, and a predetermined receiving clock. Generated reception clock generation means and decoding means for measuring the pulse width of the pulse signal received by the pulse signal reception means using the reception clock generated by the reception clock generation means and restoring the data from the measurement result. And a pulse for determining whether the pulse signal received by the pulse signal receiving means is the first correction pulse signal, the second correction pulse signal, or the transmission pulse signal based on the restoration result by the decoding means. The signal determining means and the pulse signal determining means determine that the pulse signal is the second correction pulse signal, and the decoding means outputs the first and the second correction pulse signals. A clock representing the degree of disagreement between the transmission clock and the reception clock, based on the first and second correction data restored from the respective correction pulse signals and the preset reference values of the first and second correction data. A clock error calculating means for calculating an error; a clock error calculated by the clock error calculating means; a first or second correction data restored by the decoding means; and a reference value of the correction data. Based on the delay error calculating means for calculating a delay error representing the delay of the data transmission system and the pulse signal determining means, when the pulse signal is determined to be the transmission pulse signal, the decoding means determines the transmission pulse signal. And transmission data correcting means for correcting the transmission data restored from the above based on the clock error and the delay error calculated by the respective error calculating means. A receiving device comprising: 4. The clock error calculating means calculates a deviation between the first correction data and the second correction data restored by the decoding means from a reference value of the first correction data and a second correction data. The clock error is calculated by dividing by the deviation from the reference value of the data, and the delay error calculating means calculates the correction data from the first or second correction data restored by the decoding means. The receiver according to claim 3, wherein the delay error is calculated by subtracting a product of a reference value and the calculated clock error. 5. The correction data generating means outputs a value corresponding to 2 ⁿ , 2 ^n-1 to the encoding means as the first and second correction data. Transmitter. 6. A receiving device connected to the transmitting device according to claim 5 via a signal line to receive a pulse signal, wherein the clock error calculating means is restored by the decoding means. The deviation between the first correction data and the second correction data is shifted in the lower bit direction by n-1 bits to calculate the clock error, and the delay error calculating means is restored by the decoding means. 5. The receiving apparatus according to claim 4, wherein the delay error is calculated by subtracting data obtained by shifting the calculated clock error by n bits in the upper bit direction from the first corrected data obtained. . 7. The transmission according to claim 2 or 5, wherein the correction data generating means generates a value larger than the maximum value of the transmission data as the first correction data. apparatus. 8. A receiving device connected to the transmitting device according to claim 7 through a signal line to receive a pulse signal, wherein the pulse signal determining means is restored by the decoding means. A first pulse determining means for determining that the pulse signal received by the pulse signal receiving means is a first correction pulse signal when the restored data is larger than a preset maximum value of the transmission data, The pulse signal received immediately after the first pulse determination means determines the first correction pulse signal is a second correction pulse signal, and the pulse signals received after the second correction pulse signal are transmission pulse signals, and claim 3, wherein the determining, receiving apparatus according to claim 4 or claim 6.