SU1659909A1 - Measuring converter for capacitive sensors - Google Patents

Abstract

The invention relates to measuring, controlling and controlling means and can be used as a measuring device when working with capacitive and other converters of physical quantities into a phase shift of electrical oscillations. The transmitter can increase the sensitivity and resolution of the sensor capacitance measurement by scaling the phase shift value by transferring the information signal to the low frequencies and using a digital method for measuring the phase shift. The transfer of the information signal to the low frequency region is accomplished by subtracting the frequencies of the oscillations generated by dividing the frequency of the oscillations produced by the generator, frequency dividers with close division factors. The device contains a generator, frequency dividers 2 and 3, measuring circuit 4, driver 5, frequency subtraction blocks 6 and 7, AND 8, EXCLUSIVE OR 9 / OR 10 elements, keys 11 and 12, control unit 13, reversible counter 14, register 15 and a display unit 16. 2 Il. SO with

Description

o ate yoo o yu

The invention relates to measuring, controlling and controlling means and can be used as a measuring device when working with capacitive and other converters of physical quantities into a phase shift of electrical oscillations.

The aim of the invention is to increase the sensitivity and resolution when measuring small changes in sensor capacitance.

FIG. 1 is a block diagram of a transducer for a capacitive sensor; FIG. 2 shows timing diagrams for his work.

The measuring transducer for a capacitive sensor (Fig. 1) contains a generator 1, first 2 and second 3 frequency dividers, measuring circuit 4 (containing a capacitive sensor), driver 5, first 6 and second 7 subtraction frequency blocks, element AND 8, element EXCLUSIVE OR 9, the OR element 10, the first 11 and the second 12 keys, the control unit 13, the reversible counter 14, the register 15 and the display unit 16. The generator 1 is connected to the inputs of the first 2 and second 3 frequency dividers and the second inputs of the first 11 and second 12 keys. The output of the first frequency divider 2 is connected to the input of the measuring circuit 4 and the second input of the frequency subtraction unit 7. The output of measuring circuit 4 is connected via shaper 5 to the second input of the first frequency subtraction unit 6. The output of the second frequency divider 3 is connected to the first input of the first 6 and second 7 frequency subtractors, the outputs of which are respectively connected to the first and second inputs of AND 8, EXCLUSIVE OR 9 and OR 10. The outputs of AND 8 elements and EXCLUSIVE OR 9 are connected to the first inputs keys 11 and 12. The output of the element OR 10 is connected to the input of the control unit 13, the first output of which is connected to the installation input of the reversible counter 14, and the second to the control input of the register 15, the outputs of the bits of the reversible counter 14 through the register 15 are connected to input I will give the bits of the display unit 16.

The device works as follows.

Oscillator 1 generates oscillations with a predetermined frequency, for example 10 MHz. The first 2 and second 3 frequency dividers with close division factors (for example, 200 and 198) oscillate at frequencies of 50 and 50.5 kHz, respectively. The oscillations from the output of the first divider (50 kHz) are fed to the input of the measuring circuit 4 and to the second input of the second frequency subtraction unit 7.

The oscillations shifted in phase from the output of the measuring circuit through the shaper 5 are fed to the second input of the first frequency subtraction unit 6. The oscillations from the output of the second divider 3 frequencies (50.5 kHz) are fed to the first inputs of both frequency subtraction blocks. Oscillations with a difference frequency (0.5 kHz) and a phase shift determined by the parameters of the measuring circuit are generated at the outputs of the frequency subtraction blocks. 4 (capacitive sensor). In this case, the relative magnitude of the phase shift D # is preserved, but due to the transfer of the carrier to the region of lower frequencies, the absolute value of the time shift increases. This is done in the following example. Suppose that for a given change in the capacitance of the sensor by 1 pF, the change in the phase shift is D 1 °, the absolute value of the change in the delay of the signal at the output of the measuring circuit relative to the input signal

At Ap T / 2 L 3 µs, where E is the oscillation period for a frequency of 50 kHz 5 (T 20 µs).

When measuring the change in phase shift by the digital method, this interval can be filled with 30 clock pulses of 10 MHz, i.e. resolution 0 phase shift measurement ability is 1 ° / 30 0.033 The sensitivity of the capacitance measurement is 30 pulses / pF.

At a difference frequency of 0.5 kHz, the same 5 relative phase shift of 1 ° is due to the delay t

At Dr T / 2 30 µs, where T is the period of the difference frequency (for a frequency of 0.5 kHz T 2 µs). 0 At the same clock frequency of 10 MHz, this interval can be filled with 3000 clock pulses, which gives a resolution at 1 ° / 3000 or 0.00033 °, and the sensitivity of measurement of 5 changes in capacitance is 3000 imp./fF, i.e. 100 times higher.

Thus, due to the transfer of the carrier to the lower frequency region, carried out using a frequency subtraction unit, the sensitivity and resolution 5 are increased proportionally to the carrier ratio and the difference frequencies. Since oscillations with similar frequencies are formed from the same signal produced by the generator, 0, a high stability of oscillation fronts of the difference frequency is ensured.

At the inputs of the elements AND 8, EXCLUSIVE OR 9 and OR 10 are shifted

phase variation frequency difference (plot a, b, fig, 2). In this case, at the output of the element I, a pulse is formed, the duration of which is equal to the interval between the leading edge of one signal and the falling front of the other (plot in figure 2). At the output of the EXCLUSIVE OR element, pulses are formed with durations equal to the intervals between the leading and falling edges of both signals (plot g, Fig. 2). The keys 11 and 12 carry out filling these pulses with clock pulses coming from the output of generator 1. At the output of the element OR 10, pulses are formed with durations corresponding to the time intervals between the leading edge of one signal and the falling front of another (plot d, Fig. 2) . These pulses arrive at the control unit 13, at the outputs of which short pulses are formed, corresponding to the leading and trailing edges of the input pulse (diagrams e, g, Fig. 2).

The pulses corresponding to the leading edge of the signal at the output of the OR element are fed to the installation input of the reversible counter 14, setting all the bits of the counter to the zero state. At the same time, the impulse packets from the outputs of the first and second keys, respectively, are fed to the summing and subtracting inputs of the reversible counter. Upon completion of the arrival of pulses from the output of the second key, at the outputs of the bits of the reversible counter, a binary code is formed corresponding to the difference in the number of clock pulses received at the summing and subtracting inputs. Let, under the action of the measured value, the capacitance of the sensor changed by the magnitude of the DS. Then the absolute value of the phase shift at the output of the frequency subtraction devices will change by the value of At, which is unambiguously associated with a change in the capacitance of the sensor, as shown by dotted lines in plot b, Fig. 2. At the same time, the pulse duration at the output of the element I will decrease by the magnitude of the dotted lines in the plot in figure 2), and at the output of the elements OR and EXCLUSIVE OR will increase by the value of At (punctured lines in the diagrams g, e of figure 2) . Accordingly, the number of pulses arriving at the summing input of the reversible counter will decrease by A N + AIT. and the number of pulses arriving at the subtraction input will increase by AN-A t fT (fr is the clock frequency). When the sensor capacitance on the AC changes, the binary code at the output of the bits of the reversible counter will correspond to the number N (t + At} ft - (g - At) ft + + (g + At) ft (g + 3At} ft,

where r is the absolute value of the initial phase shift.

Claims (1)

At the end of the counting of the difference in the number of pulses by a reversible counter, under the action of a pulse arriving at the control input of register 15, the binary code present at the outputs of the bits of the reversible counter is written into the register and transmitted to the input of the display unit 16. Then, the pulse arriving at the installation input of the reversible counter is zeroed and the next measurement cycle begins. A measuring transducer for a capacitive sensor, comprising a generator, a measuring circuit and a first key, a generator connected to a second key input, an indication unit, characterized in that, in order to increase the sensitivity and resolution, the first and second frequency dividers are introduced, the first and second frequency subtraction units, AND, IL AND AND EXCLUSIVE OR elements, second key, driver, reversible counter, control unit, register, the generator output connected to the inputs of the first and second partitions You and the second input of the second key, the output of the first frequency divider is connected to the input of the measuring circuit and the first input of the second frequency subtraction unit, the output of the second frequency divider is connected to the second inputs of the frequency subtraction blocks, the output of the measuring circuit is connected to the first input of the first frequency subtraction unit, the outputs of the first and second frequency subtraction units are connected respectively to the first and second inputs of the AND, OR and EXCLUSIVE OR elements, the outputs of the AND elements and EXCLUSIVE OR are connected to the first inputs the first and second keys, the outputs of which are connected to the inputs of the summation and subtraction of the reversible counter, the output of the OR element is connected to the input of the control unit, the first output of which is connected to the installation input of the reversible counter, and the second to the control input of the register, the outputs of the reversible counter bits through the register is connected to the inputs of the display unit.