JP3428088B2 - Signal processing circuit for piezoelectric sensor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a piezoelectric sensor, and more particularly, it can cancel drift of the output of the processing circuit and is effective for use in a load detecting device for automobiles, machine tools and the like.

[0002]

2. Description of the Related Art Since a piezoelectric sensor supplies a current to a change in load, the load value applied to the piezoelectric sensor cannot be seen as a voltage value from the sensor signal itself. But,
By integrating the sensor signal, it can be viewed as a voltage value. As this signal processing circuit, there is a method using an integrating circuit (charge amplifier circuit) as shown in FIG.

The integrating circuit 1 shown in FIG. 2 is composed of an integrating circuit 17 including an operational amplifier 12 and a capacitor 11, and an inverting amplifier circuit 18 including an operational amplifier 15, a resistor 13, a resistor 14 and a resistor 16. When a current from the piezoelectric sensor 7 flows to the input section connected to the inverting input terminal of the operational amplifier 12, the capacitor 11 is charged and the operational amplifier 1
A voltage value proportional to the amount of current appears in the output of 2. Thus, the output value obtained by integrating the input value is obtained.

[0004]

However, in the above-mentioned conventional method, the bias current and the offset current of the electronic components forming the integrating circuit, the leakage current of the charge detecting capacitor 11, and the pyroelectric effect of the piezoelectric sensor itself are caused. Due to the generation of the minute current, the integrated signal level is shown in FIG.
As shown in (c), a drift occurs, causing a problem that the load value for the piezoelectric sensor cannot be obtained accurately.

Therefore, an object of the present invention is to provide a piezoelectric sensor signal processing circuit for subtracting a drift amount from an integrated signal and obtaining only a true value of a load value applied to the piezoelectric sensor as a voltage value. And

[0006]

In order to achieve the above object, the present invention eliminates the drift component of the integration signal and the integration circuit for integrating the current from the piezoelectric sensor, and calculates the average value of the integration signal. A high-pass filter circuit that outputs a signal serving as a reference value, a peak hold circuit that outputs the average value by holding a negative peak of the signal output by the high-pass filter circuit, and an average value of the integrated signal. A low-pass filter circuit that outputs a signal for a drift component that includes: a first arithmetic circuit that calculates a signal for a drift component from the output signal of the low-pass filter circuit and the average value output by the peak hold circuit; and the output signal of the integration circuit And a second arithmetic circuit for subtracting the drift amount signal calculated by the first arithmetic circuit from It is intended to use.

Further, according to the present invention as defined in claim 2, an integrating circuit for integrating the current from the piezoelectric sensor and a drift amount of the integrated signal are removed, and a signal having an average value of the integrated signal as a reference value is output. And the negative peak of the signal output by this high-pass filter circuit.
A piezoelectric sensor including a peak hold circuit that outputs the average value by holding, and a third arithmetic circuit that outputs an integrated signal from the difference between the output signal of the high-pass filter circuit and the average value of the peak hold circuit. A signal processing circuit for use is adopted.

[0008]

According to the present invention described in claim 1, the high pass filter circuit removes the drift component from the integrated signal from the piezoelectric sensor integrated by the integrating circuit, and the average value is used as the reference value. Output the signal. From this output signal, the peak hold circuit detects the negative peak of the output signal.
By holding, the average value is calculated. On the other hand, the low-pass filter circuit outputs a drift component signal including the average value of the integrated signal from the integration circuit. Then, the first arithmetic circuit detects a drift component signal from the drift component signal including the average value output by the low pass filter circuit and the average value calculated by the peak hold circuit. In the second arithmetic circuit, only the true integrated value is calculated by subtracting the drift signal calculated in the first arithmetic circuit from the integrated value including the drift signal output in the integrator circuit. You can

According to the second aspect of the present invention, the high-pass filter circuit removes the drift component from the integrated signal from the piezoelectric sensor integrated by the integrating circuit and outputs a signal based on the average value. . From this output signal, the peak hold circuit holds the negative peak of the output signal.
Thus, the average value is calculated. Then, only the integral value of the true value can be calculated by subtracting the average value of the peak hold circuit from the output signal of the high pass filter circuit in the third arithmetic circuit.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the overall configuration of this embodiment, which includes an integrating circuit block 1, a low-pass filter circuit 2, a high-pass filter circuit 3, a peak hold circuit 4, an adder circuit 5, and a subtractor circuit 6. Composed.
Reference numeral 7 is a piezoelectric sensor.

The integrating circuit block 1 includes an integrating circuit 17 including an operational amplifier 12 and a capacitor 11, and an operational amplifier 1
5, an inverting amplifier circuit 18 including a resistor 13, a resistor 14, and a resistor 16. When a current from the piezoelectric sensor 7 flows to the input section connected to the inverting input terminal of the operational amplifier 12, the capacitor 11 is charged and a voltage value proportional to the amount of current appears at the output of the operational amplifier 12. Thus, the output value obtained by integrating the input value is obtained. Since the input is to the inverting input terminal of the operational amplifier 12, the output waveform has a form in which positive and negative are inverted with respect to the input waveform. In the inverting amplifier circuit 18, a signal amplified by the ratio of the resistors 13 and 14 is obtained at the output of the operational amplifier 15. In the inverting amplifier circuit 18 as well, since the input is to the inverting input terminal, the output is an inverted positive and negative with respect to the input.

The low pass filter 2 comprises a resistor 21 and a capacitor 22. This low pass filter circuit 2
With respect to the signal input to, the higher frequency signal is attenuated and the lower frequency signal is passed by the cutoff frequency determined by the constants of the resistor 12 and the capacitor 22. Therefore, it operates as a low-pass filter circuit. The high pass filter circuit 3 includes a capacitor 31 and a resistor 32. The signal input to the high-pass filter circuit 3 is attenuated by the cut-off frequency determined by the constants of the capacitor 31 and the resistor 32, and the signal of the higher frequency passes through. Therefore, it operates as a high-pass filter circuit.

The peak hold circuit 4 includes an operational amplifier 41.
And a diode 42, a resistor 43, a capacitor 44, and an operational amplifier 45. When a signal having a potential lower than the potential charged in the capacitor 44 is input from the high-pass filter circuit 3 to the operational amplifier 41, the current discharged from the capacitor 44 flows through the diode 42,
The potential of the capacitor 44 decreases until it becomes equal to the potential of the input of the operational amplifier 41. When a signal having a potential higher than the potential charged in the capacitor 44 is present at the input of the operational amplifier 41, a current does not flow in the diode 42, so that the potential of the capacitor 44 is held as it is. Therefore, it operates as a low potential peak hold circuit. However, even when no current flows through the diode 42, the resistor 43 gradually discharges (charges when the potential of the capacitor is negative). The operational amplifier 45 operates as a buffer circuit.

The adder circuit 5 comprises a resistor 51, a resistor 52, an operational amplifier 53, a resistor 54 and a resistor 55. The signals input to the resistors 51 and 52 are added, and this signal is added to the resistors 54 and 55 with respect to the output of the operational amplifier 53.
Since the values are divided by, a signal amplified by the ratio of the resistance 54 and the resistance 55 is output to the output of the operational amplifier 53. Therefore, this circuit operates as an adding circuit.

The subtraction circuit 6 comprises a resistor 61, a resistor 62, a resistor 63, an operational amplifier 64 and a resistor 65. The signals input to the resistors 61 and 62 are input to the input terminals of the operational amplifier 64, respectively. The operational amplifier 64 is
Since it outputs the voltage difference at the input terminals, it operates as a differential input type subtraction circuit. Therefore, the operational amplifier 64 includes the resistor 61
And the difference between the signals input to the resistor 62 is output.

The circuit configuration of each part according to this embodiment is as follows.
The configuration is not limited to the above configuration, and a low pass filter circuit, a high pass filter circuit, or the like may be configured by another configuration. Next, the operation of the present embodiment will be described with reference to FIG. 1, which is an overall configuration diagram, and FIG. 3, which shows the signal waveform of each part.

When the piezoelectric sensor 7 is subjected to a weight variation as shown in FIG.
A current as shown in (b) flows. This current is charged in the capacitor 11 of the integrating circuit block 1, and a voltage obtained by integrating the amount of current appears at the output of the integrating circuit block 1. That is, the weighted value for the piezoelectric sensor 7 can be obtained as the voltage value.

However, this voltage value changes due to leakage current of the capacitor 11, bias current of the operational amplifier 12, generation of minute current due to pyroelectric effect of the piezoelectric sensor, and the like.
As shown in FIG. 3C, a drift will occur. Since the frequency of the drift component of the integrated signal including the drift component is lower than that of the integration signal, the drift component is extracted from the output signal of the integration circuit block 1 by the low-pass filter circuit 2. However, as shown in FIG. 3D, in addition to the drift component, the output of the low-pass filter circuit 2
A value including the average value of the integrated values that are the output values of the integration circuit block 1 is output.

On the other hand, from the output of the integrating circuit block 1, a high pass filter circuit 3 extracts an integrated signal from which drift components have been cut. However, as shown in FIG. 3E, the output of the high-pass filter circuit 3 is a signal with the average value of the integrated signals set to 0 [V]. That is, the output waveform of the high-pass filter circuit 3 has a negative peak from 0 [V].
The value up to the value becomes the average value of the integrated signal in absolute value . So
For inputs the output values of the high-pass filter circuit 3 to the peak hold circuit 4 by the peak hold circuit 4, as shown in FIG. 3 (f), of the high-pass filter circuit 3
By obtaining the integrated signal of the output signal,
The average value of the output values of the filter circuit 3 is calculated.

Then, to the adder circuit 5, the drift amount including the average value of the integrated signal output from the low pass filter circuit 2 and the average value of the integrated signal output from the peak hold circuit 4 are input. Since the adder circuit 5 operates as an adder circuit, the waveform shown in FIG. 3 (d) and the waveform shown in FIG. 3 (f) are added to obtain a value corresponding to the drift amount as shown in FIG. 3 (g). .

The subtraction circuit 6 receives the integrated signal including the drift component output from the integration circuit block 1 and the drift component output from the adder circuit 5. Since the subtraction circuit 6 operates as a subtraction circuit, the output signal of the addition circuit 5 shown in FIG. 3 (g) is subtracted from the output signal of the integration block 1 shown in FIG. 3 (c), and as shown in FIG. 3 (b). , Only the integrated signal can be obtained.

Therefore, it operates as a signal processing circuit capable of canceling the drift amount and taking out the signal obtained by integrating the current amount from the piezoelectric sensor 7. Next, as a second embodiment, a circuit configured by the block diagram of FIG. 4 will be described. The same components as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The configuration of the second embodiment is such that the integrating circuit block 1 connected to the piezoelectric sensor 7, the low-pass filter circuit 2 connected to the integrating circuit block 1, and the integrating circuit block 1 and the low-pass filter circuit 2 are connected. Subtraction circuit 6
And a peak hold circuit 4 connected to the subtraction circuit 6,
It is composed of a subtraction circuit 6 and an arithmetic circuit 5 connected to the peak hold circuit 4.

The operation of the second embodiment will be described. The current from the piezoelectric sensor 7 is integrated by the integration block 1 to obtain an integrated signal as shown in FIG. 3C in the same manner as in the first embodiment. From the integrated signal, the low-pass filter circuit 2 obtains a drift signal including the average value of the integrated signal as shown in FIG. In the subtraction circuit 6, the output signal of the low-pass filter circuit 2, which is a drift component signal including the average value of the integrated signal, is subtracted from the integrated signal in the integration circuit block 1, and the average value of the integrated signal is calculated from the true value of the integrated signal. To get the signal minus. That is, an output waveform similar to the output waveform of the high pass filter circuit 3 in the first embodiment (see FIG. 3E) is obtained.

Then, the peak hold circuit 4 obtains an output signal from the output of the subtraction circuit 6 as shown in FIG. 3 (f) showing only the average value of the integrated signal. From the output of the subtraction circuit 6 and the average value of the integrated signal, the adder circuit 5 can obtain only the true value of the integrated signal with the drift component canceled, as shown in FIG. Next, as a third embodiment, a circuit configured by the block diagram of FIG. 5 will be described.

In the third embodiment, an integrating circuit block 1 connected to the piezoelectric sensor 7, a high pass filter circuit 2 connected to the integrating circuit block 1, and a peak hold circuit 3 connected to the high pass filter circuit 2. , The high pass filter circuit 2 and the peak hold circuit 3 are connected to the arithmetic circuit 4. The same components as those in the above embodiment are designated by the same reference numerals and the description thereof will be omitted.

Explaining the operation of the third embodiment, the current from the piezoelectric sensor 7 is integrated by the integrating circuit block 1 to obtain an output signal as shown in FIG. 3 (c). From the integrated signal, the high-pass filter circuit 2 obtains a signal in which the average value of the integrated signal is 0 [V]. From the signal, the peak hold circuit 3 obtains the average value of the integrated signal as shown in FIG. Then, the signal in which the average value of the integrated signal is 0 [V] and the average value of the integrated signal are input to the adding circuit 5. The addition circuit 5 adds both signals to cancel the drift amount. Only the true value of the integrated signal can be obtained.

The low-pass filter circuit 2 and the subtraction circuit 6 in the second embodiment calculate a signal equivalent to that in the high-pass filter circuit 2 in the third embodiment.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional signal processing circuit.

3A to 3H are diagrams showing signal waveforms in respective components.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a third embodiment of the present invention.

[Explanation of symbols]

1 Integrating circuit block 2 Low-pass filter circuit 3 High-pass filter circuit 4 Peak hold circuit 5 First arithmetic circuit 6 Second arithmetic circuit 7 Piezoelectric sensor

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Mizutani No. 1-1, Showa-cho, Kariya city, Aichi Japan Denso Co., Ltd. (56) References JP-A-49-21048 (JP, A) JP-A 64-- 21237 (JP, A) JP 5-129902 (JP, A) JP 4-268809 (JP, A) JP 59-193617 (JP, A) JP 62-23224 (JP, A) Japanese Patent Publication No. 50-16623 (JP, B1) Japanese Patent Publication No. 48-23466 (JP, B1) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 5/08

Claims (2)

(57) [Claims] 1. An integrating circuit for integrating a current from a piezoelectric sensor, a high-pass filter circuit for removing a drift amount of the integrated signal, and outputting a signal with an average value of the integrated signal as a reference value, and the high-pass filter. The negative of the signal output by the circuit
A peak hold circuit that outputs the average value by holding a peak, a low-pass filter circuit that outputs a drift component signal that includes the average value of the integrated signal, an output signal of the low-pass filter circuit, and the peak hold circuit A first arithmetic circuit for calculating a drift component signal from the average value output by the second arithmetic circuit, and a second arithmetic circuit for subtracting the drift component signal calculated by the first arithmetic circuit from the output signal of the integrating circuit, A piezoelectric sensor signal processing circuit provided. 2. An integrating circuit for integrating a current from a piezoelectric sensor, a high-pass filter circuit for removing a drift amount of the integrated signal, and outputting a signal with an average value of the integrated signal as a reference value, and the high-pass filter. The negative of the signal output by the circuit
Comprising by holding the peak, and a peak hold circuit for outputting the average value, and a third arithmetic circuit that outputs an integration signal from the difference between the output signal and the average value of the peak hold circuit of the high-pass filter circuit Signal processing circuit for piezoelectric sensor.