JPS6126332A - Multipath distortion correcting circuit - Google Patents

Multipath distortion correcting circuit

Info

Publication number
JPS6126332A
JPS6126332A JP14730084A JP14730084A JPS6126332A JP S6126332 A JPS6126332 A JP S6126332A JP 14730084 A JP14730084 A JP 14730084A JP 14730084 A JP14730084 A JP 14730084A JP S6126332 A JPS6126332 A JP S6126332A
Authority
JP
Japan
Prior art keywords
signal
adder
output signal
outputs
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14730084A
Other languages
Japanese (ja)
Inventor
Kazuo Takayama
一男 高山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP14730084A priority Critical patent/JPS6126332A/en
Publication of JPS6126332A publication Critical patent/JPS6126332A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE:To surely correct a multipath distortion, by correcting an input signal in accordance with the difference between the output signal of a low-pass filter and the signal which is the arithmetic mean of the output signals of a (+) side and (-) side envelope detecting circuits. CONSTITUTION:An adder 2 outputs the difference between an input signal (a) and correcting signal (h). The output signal (b) of the adder 2 is supplied to a low-pass filter 3, (+) side envelope detecting circuit 4, and (-) side envelope detecting circuit 5. The filter 3 outputs a signal (c), from which noise frequency components are attenuated. On the other hand, the output signals (d) and (e) of the circuits 4 and 5 are averaged by means of an adder 6 and subtractor 7 and, as a result, a signal (f) is outputted. An adder 8 outputs a signal (g) which is the difference between the signals (f) and (c). Since the signal (g) is superposed upon the signal (a) and proportional to the level of noises, the correcting signal (h) is obtained when the signal (a) is amplified at an amplifier 9. The corrected signal (b) is outputted from an output terminal 10.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はマルチパス歪を補正するマルチパス歪補正回路
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multipath distortion correction circuit that corrects multipath distortion.

従来技術 ラジオ受信機等に於いては、マルチパスが発生すると第
5図(A)、  (B)に示すようなノイズが重畳され
た信号が復調回路から出力される。同図(A)に示すよ
うに、ノイズが信号に対して対称に重畳されている場合
はローパスフィルタを通すことにより、同図(C)に示
すようにノイズを除去した信号を得ることができるが、
同図(B)に示すようにノイズが信号に対して非対称に
重畳されている場合はローパスフィルタを通すだけでは
同図(D)に示すように信号に歪が発生する。
In conventional radio receivers and the like, when multipath occurs, a signal on which noise is superimposed as shown in FIGS. 5(A) and 5(B) is output from the demodulation circuit. If noise is symmetrically superimposed on the signal, as shown in (A) of the same figure, by passing it through a low-pass filter, it is possible to obtain a signal from which the noise has been removed, as shown in (C) of the same figure. but,
If noise is asymmetrically superimposed on the signal, as shown in FIG. 5B, distortion will occur in the signal, as shown in FIG.

発明が解決しようとする問題点 本発明は前述の如き欠点を改善したもので、その目的は
マルチパス歪を確実に補正できるようにすることにある
。以下、実施例について詳細に説明する。
Problems to be Solved by the Invention The present invention is an attempt to improve the above-mentioned drawbacks, and its purpose is to make it possible to reliably correct multipath distortion. Examples will be described in detail below.

問題点を解決するための手段 本発明は前出の如き問題点を解決するため、入力信号と
補正信号との差を出力する第1の加算器と、使用周波数
の上限にカットオフ周波数を有すると共にカットオフ周
波数以上の周波数成分も減衰させて通過させる第1の加
算器の出力信号を入力とするローパスフィルタと、第1
の加算器の出力信号の立上りに急峻に追従し立下りに緩
やかに追従する信号を出力する+側包絡線検波回路と、
第1の加算器の出力信号の立下りに急峻に追従し立上り
に緩やかに追従する信号を出力する−側包絡線検波回路
と、+側包絡線検波回路と−側包絡線検波回路との出力
信号を平均化する平均化手段と、平均化手段の出力信号
と前記ローパスフィルタの出力信号との差を出力する第
2の加算器と、第2の加算器の出力信号を所定の増幅率
で増幅して補正信号を出力する増幅器とを備えたことを
特徴するマルチパス歪補正回路。
Means for Solving the Problems In order to solve the above problems, the present invention includes a first adder that outputs the difference between the input signal and the correction signal, and a cutoff frequency at the upper limit of the frequency used. a low-pass filter that receives the output signal of the first adder and also attenuates and passes frequency components higher than the cutoff frequency;
a + side envelope detection circuit that outputs a signal that sharply follows the rise of the output signal of the adder and gently follows the fall of the output signal;
Outputs of a negative envelope detection circuit, a positive envelope detection circuit, and a negative envelope detection circuit that output a signal that sharply follows the falling edge of the output signal of the first adder and gently follows the rising edge of the output signal of the first adder. an averaging means for averaging signals; a second adder for outputting the difference between the output signal of the averaging means and the output signal of the low-pass filter; and an output signal of the second adder at a predetermined amplification factor. A multipath distortion correction circuit characterized by comprising an amplifier that amplifies and outputs a correction signal.

実施例 第1図は本発明の実施例のブロック線図であり、1は例
えばif 11器(図示せず)の出力信号が入力される
入力端子、2は加算器、3は抵抗R1及びコンデンサC
Iからなるローパスフィルタ、4はダイオードDI、コ
ンデンサC2及び抵抗R2,R3からなる+側包絡線検
波回路、5はダイオードD2.コンデンサC3及び抵抗
1’14.R5からなる一側包絡線検波回路、6は加算
器、7は除数が2の除算器、8は加算器、9は増幅器、
10は出力端子である。尚、R1= R2= R3,C
I= C2= C3となるように、抵抗R1〜R3の抵
抗値及びコンデンサ01〜C3の抵抗値が設定されてい
るものである。
Embodiment FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is an input terminal into which the output signal of, for example, an IF 11 unit (not shown) is input, 2 is an adder, and 3 is a resistor R1 and a capacitor. C
4 is a + side envelope detection circuit consisting of a diode DI, a capacitor C2 and resistors R2 and R3, 5 is a diode D2. Capacitor C3 and resistor 1'14. One side envelope detection circuit consisting of R5, 6 an adder, 7 a divider with a divisor of 2, 8 an adder, 9 an amplifier,
10 is an output terminal. In addition, R1= R2= R3,C
The resistance values of the resistors R1 to R3 and the resistance values of the capacitors 01 to C3 are set so that I=C2=C3.

今、例えば第2図(A)に示すノイズが重畳された信号
aが入力端子1に印加され、且つ説明の便宜上加算器2
の一端子に信号りが印加されていないとすると、信号a
はそのままローパスフィルタ3.+側包絡線検波回路4
及び−測色絡線検波回路5に加えられることになる。ロ
ーパスフィルタ3はノイズが重畳されている信号aの周
波数成分が第3図に示すものであるとすると、同図に実
線で示すように信号周波数領域の成分aを通過させ、ノ
イズ周波数成分すを減衰させて通過させるようにその特
性が設定されているものであり、従ってローパスフィル
タ3の出力信号Cは第2図(B)に示すように信号aに
重畳されているノイズを鈍らせたものとなる。また、+
側包絡線検波回路4はダイオードD1及び抵抗R2を介
してコンデンサC2を充電し、抵抗R2を介してコンデ
ンサc2の充電電荷を放電するものであるから、その出
力信号dは同図(C)に示すように立上りが急峻で立下
りが緩やかなものとなる。また、−例句路線検波回路5
は抵抗R4を介してコンデンサc3を充電し、ダイオー
ドD2及び抵抗R4を介して充電電荷を放電するもので
あるから、その出力信号eは同図(D)に示すように立
下りが急峻で立上りが緩やかなものとなる。
Now, for example, the noise-superimposed signal a shown in FIG.
Assuming that no signal is applied to one terminal of a, the signal a
is the low pass filter 3. + side envelope detection circuit 4
and - will be added to the colorimetric cross-wire detection circuit 5. Assuming that the frequency component of the signal a on which noise is superimposed is as shown in FIG. Its characteristics are set so that the signal is attenuated and passed through, so the output signal C of the low-pass filter 3 is a signal obtained by dulling the noise superimposed on the signal a, as shown in Fig. 2 (B). becomes. Also, +
Since the side envelope detection circuit 4 charges the capacitor C2 via the diode D1 and the resistor R2, and discharges the charge of the capacitor C2 via the resistor R2, its output signal d is as shown in FIG. As shown, the rise is steep and the fall is gradual. Also, -Example line detection circuit 5
charges the capacitor c3 via the resistor R4, and discharges the charged charge via the diode D2 and the resistor R4, so the output signal e has a steep fall and a rise as shown in (D) of the same figure. becomes gradual.

そして、+側包絡線検波回路4及び−測色絡線検波回路
5の出力信号d、eは加算器6で加算されて除算器7に
加えられ、除算器7より第2図(E)に示す信号fが出
力される。加算器8は除算器7の出力信号fとローパス
フィルタ3の出力信号Cとの差を示す信号gを出力する
。ここで、加算器8の出力信号gは同図(F)に示すよ
うに、信号aに重畳されているノイズのレベルに比例し
たものとなるから、信号gを所定の増幅率で増幅する増
幅器9の出力信号りを加算器2の一端子に加えることに
より、加算器2の出力信号すはノイズが除去されたもの
となる。
Then, the output signals d and e of the + side envelope detection circuit 4 and the - colorimetric cross detection circuit 5 are added in an adder 6 and added to a divider 7, and the output signals from the divider 7 are shown in FIG. 2(E). A signal f shown is output. The adder 8 outputs a signal g indicating the difference between the output signal f of the divider 7 and the output signal C of the low-pass filter 3. Here, the output signal g of the adder 8 is proportional to the level of noise superimposed on the signal a, as shown in FIG. By applying the output signal of 9 to one terminal of the adder 2, the output signal of the adder 2 becomes one from which noise has been removed.

また、第4図(A)〜(F)は第2図(A)に示した信
号aに比較して周波数が高く、且つノイズが重畳されて
いない信号すをローパスフィルタ3、+側包絡線検波回
路4及び−測色絡線検波回路5に加えた際の各部の波形
c −gを示したものであり、同図(F)に示すように
加算器8の出力信号gのレベルは零となるものであるか
ら、入力端子1に周波数が高く且つノイズが重畳されて
いない信号aが印加された場合にも、誤動作することは
ない。
In addition, in FIGS. 4(A) to 4(F), a signal having a higher frequency than the signal a shown in FIG. 2(A) and on which no noise is superimposed is filtered by the low-pass filter 3, and the + side envelope This shows the waveforms c to g of each part when added to the detection circuit 4 and the colorimetric circuit detection circuit 5, and as shown in (F) in the same figure, the level of the output signal g of the adder 8 is zero. Therefore, even if a signal a having a high frequency and no noise is superimposed is applied to the input terminal 1, there will be no malfunction.

発明の詳細 な説明したように本発明は、入力信号と補正信号との差
を出力する加算器2等の第1の加算器と、第1の加算器
の出力信号を濾波するローパスフィルタと、第1の加算
器の出力信号を入力とする+側包絡線検波回路と、第1
の加算器の出力信号を入力とする一側包絡線検波回路と
、+側包絡線検波回路と一例包絡線検波回路との出力信
号を平均化する加算器6、除算器7等からなる平均化手
段と、平均化手段の出力信号とローパスフィルタの出力
信号の差を出力する加算器8等の第2の加算器と、第2
の加算器の出力信号を所定の増幅率で増幅して補正信号
を出力する増幅器とを備えたものであるから、マルチパ
ス歪を補正できる利点がある。
DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention includes: a first adder such as adder 2 that outputs the difference between an input signal and a correction signal; a low-pass filter that filters the output signal of the first adder; a + side envelope detection circuit which receives the output signal of the first adder;
An averaging circuit consisting of an adder 6, a divider 7, etc., which averages the output signals of the one-side envelope detection circuit that inputs the output signal of the adder, the +-side envelope detection circuit, and the envelope detection circuit. a second adder such as an adder 8 for outputting the difference between the output signal of the averaging means and the output signal of the low-pass filter;
Since it is equipped with an amplifier that amplifies the output signal of the adder by a predetermined amplification factor and outputs a correction signal, it has the advantage that multipath distortion can be corrected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図本発明の実施例のブロック線図、第2図は第1図
の動作説明図、第3図はローパスフィルタの特性図、第
4図は第1図の動作説明図、第5図は従来の欠点を説明
する為の波形図である。 1は入力端子、2,6.8は加算器、3はローパスフィ
ルタ、4は+側包絡線検波回路、5は一側包絡線検波回
路も、7は除算器、9は増幅器、10は出力端子である
。 特許出願人 富士通テン株式会社 代理人弁理士玉蟲久五部(外1名) 第1図 ン 第6図 す 第2図
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is a characteristic diagram of the low-pass filter, Fig. 4 is an explanatory diagram of the operation of Fig. 1, Fig. 5 is a waveform diagram for explaining the conventional drawbacks. 1 is an input terminal, 2, 6.8 is an adder, 3 is a low-pass filter, 4 is a + side envelope detection circuit, 5 is also a one side envelope detection circuit, 7 is a divider, 9 is an amplifier, 10 is an output It is a terminal. Patent Applicant Fujitsu Ten Ltd. Representative Patent Attorney Gobe Tamamushi (1 other person) Figure 1, Figure 6, Figure 2

Claims (1)

【特許請求の範囲】[Claims] 入力信号と補正信号との差を出力する第1の加算器と、
使用周波数の上限にカットオフ周波数を有すると共にカ
ットオフ周波数以上の周波数成分も減衰させて通過させ
る前記第1の加算器の出力信号を入力とするローパスフ
ィルタと、前記第1の加算器の出力信号の立上りに急峻
に追従し立下りに緩やかに追従する信号を出力する+側
包絡線検波回路と、前記第1の加算器の出力信号の立下
りに急峻に追従し立上りに緩やかに追従する信号を出力
する−側包絡線検波回路と、前記+側包絡線検波回路と
−側包絡線検波回路との出力信号を平均化する平均化手
段と、該平均化手段の出力信号と前記ローパスフィルタ
の出力信号との差を出力する第2の加算器と、該第2の
加算器の出力信号を所定の増幅率で増幅して前記補正信
号を出力する増幅器とを備えたことを特徴するマルチパ
ス歪補正回路。
a first adder that outputs the difference between the input signal and the correction signal;
a low-pass filter that receives as input the output signal of the first adder, which has a cutoff frequency at the upper limit of the frequency used, and also attenuates and passes frequency components higher than the cutoff frequency; and the output signal of the first adder. a + side envelope detection circuit that outputs a signal that sharply follows the rising edge of the output signal and slowly follows the falling edge of the output signal of the first adder; a negative envelope detection circuit for outputting a signal, an averaging means for averaging the output signals of the positive envelope detection circuit and the negative envelope detection circuit, and averaging means for averaging the output signals of the averaging means and the low-pass filter. A multipath comprising: a second adder that outputs the difference between the output signal and the output signal; and an amplifier that amplifies the output signal of the second adder by a predetermined amplification factor and outputs the correction signal. Distortion correction circuit.
JP14730084A 1984-07-16 1984-07-16 Multipath distortion correcting circuit Pending JPS6126332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14730084A JPS6126332A (en) 1984-07-16 1984-07-16 Multipath distortion correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14730084A JPS6126332A (en) 1984-07-16 1984-07-16 Multipath distortion correcting circuit

Publications (1)

Publication Number Publication Date
JPS6126332A true JPS6126332A (en) 1986-02-05

Family

ID=15427078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14730084A Pending JPS6126332A (en) 1984-07-16 1984-07-16 Multipath distortion correcting circuit

Country Status (1)

Country Link
JP (1) JPS6126332A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0439299A2 (en) * 1990-01-23 1991-07-31 International Business Machines Corporation A circuit for suppressing additive disturbances in data channels

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0439299A2 (en) * 1990-01-23 1991-07-31 International Business Machines Corporation A circuit for suppressing additive disturbances in data channels

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