JP3421441B2 - Dynamic memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic memory (DRAM) which requires very high speed data transfer in a data input / output path.

[0002]

2. Description of the Related Art Generally, a dynamic memory uses a cell array division operation system in which a memory cell array is divided into a plurality of cell arrays (sub-arrays) and some of them are operated simultaneously. This method is for reducing the charging / discharging current of the bit line, which occupies most of the current consumption of the row system operation. The number of sub-array divisions has a great relationship with the operating speed. If the scale of one sub-array is large, the capacity of the word line becomes too large and the rising speed and the falling speed thereof become slow, and the capacity of the bit line becomes too large and the potential difference between the bit line pair becomes small. The amplification operation of the bit line potential due to is slowed, and the operation speed of the entire memory chip is slowed. Therefore, as the storage capacity of the DRAM increases with the miniaturization of elements, the number of sub-arrays tends to increase.

On the other hand, the conventional general-purpose DRAM chip is
Various bit configurations (x1, x4 , x8, x16, etc.)
And various package configurations (DIP, SOJ, TSO
P, ZIP, etc.). Therefore, as shown in FIG. 4, DQ buffers 43 for amplifying the data on the data lines 42 are arranged near each sub-array 41, and the data of all the DQ buffers 43 are arranged at one location on the chip (see FIG. 4). Then, the data is collected in the multiplexer 44 arranged at the center of the chip) and the data of the number of bits corresponding to the bit configuration is output to the input / output pad (I / O pad) 45 at the position corresponding to the package configuration.

However, in the method of concentrating all the read data from the increasing sub-array in one place on the chip like the above-mentioned DRAM, the data path in the chip is lengthened and the data transfer speed is increased. Hinders the operation.

In a dedicated DRAM chip, each I
By using the vertical type package (VSMP) that collects / O pads on one side of the chip and can be surface-mounted vertically on the printed circuit board for memory mounting, the lead frame inside the package and the wiring on the circuit board can be shortened. Therefore, attempts have been made to increase the data transfer rate and at the same time improve the data transfer rate by adopting a multi-bit configuration such as × 8 or × 16.

On the other hand, as a memory used in large quantities in a computer system, a DRAM that can be realized at a low cost is required. In the field of computers, the difference between the operating speed of a microprocessor (MPU) and the operating speed of a DRAM is increasing, and the data transfer speed between the two becomes a bottleneck that determines the performance of the entire system. There is. Various improvements have been made to solve this, and a typical one is placed between the MPU and the main memory in order to bridge the difference between the cycle time of the MPU and the access time of the main memory. This is the adoption of high-speed memory (cache memory) that enables improvement.

As a cache memory, the D is also used by the MPU.
MPU, which is composed of SRAM independent from RAM
On-chip cache (or embedded memory) configured with SRAM called chip (actually, MPU with cache memory)
However, it may have an SRAM cache of another chip. ) And SRAM cells mounted on a DRAM chip.

Regarding mounting a cache composed of SRAM cells on a DRAM chip, 1990 Symposium o
n VLSI Circuits, Digest of Technical Papers, pp 79-8
0 "A Circuit Design of Intelligent CDDRAM with Aut
A document "omatic Write back Capability" discloses a technique in which an SRAM cell is added to each column of a DRAM using a cell of 1 transistor and 1 capacitor and the cell is used as a cache memory. When the address to be read is not in the cache memory (miss hit), the contents of the cache memory at that time are written back to the DRAM cell at the corresponding address, and then the technology to read the DRAM cell at the address to be accessed is also mentioned. Such a cache-mounted DRAM can also be used in combination with an MPU equipped with a cache memory.
Regarding that the M bit line sense amplifier can be used as a cache memory, Japanese Patent Application No.
No. 41316 (Japanese Patent Laid-Open No. 4-212780), and a specific configuration example and control operation example thereof are described in Japanese Patent Application No. 3-41315 filed by the applicant of the present application.

[0009] Furthermore, Japanese Patent Application No. Hei.
No. -131095, a DRAM capable of increasing the hit rate of the cache memory by dividing the memory area of the DRAM into a plurality of subarrays, operating each subarray independently of each other, and using the bit line sense amplifier as the cache memory. Proposed.

In this DRAM, the sense amplifier holds the data extracted from the rows corresponding to the addresses different from each other for each of the plurality of sub-arrays, so that a data access request comes to the selected row. (hit)
The probability can be increased, and the average value of the data access time determined by the average value of the probability (miss) of no data access request to the row in the selected state and the probability of the hit can be reduced.

The sense amplifier cache system will be briefly described below. Now, consider a state in which the DRAM is waiting for an access from the MPU or the like. At this time, read data from the memory cell group at a certain row address is latched in the sense amplifier group.

If there is an access to the same row address as the row address where the data is latched in the sense amplifier group (at the time of hit) as described above, the row system operation is omitted and only the column system operation is performed. The data can be output by, and the access time for the row-related operation can be reduced.

On the other hand, if the row address in which the data is not latched in the sense amplifier group is accessed (during a miss), the data in the sense amplifier group is written back to the memory cell (or simply sensed). After the equalizing operation of the amplifier group), it is necessary to latch the read data from the memory cell group of the new row address in the sense amplifier group. In the case of this miss, the access time is longer than when the cache method is not used.

Therefore, if the hit rate of the cache memory is small, there is a risk that the average access time of the system becomes long, and increasing the hit rate is important for shortening the average access time of the system. Is.

In order to increase the hit rate of the cache memory, there are a method of increasing the capacity of the cache memory and a method of dividing the cache memory into several banks.
When the method of increasing the capacity of the cache memory as described above is applied to the sense amplifier cache method, it means increasing the number of sense amplifiers waiting for access while latching data. In general, a large capacity memory performs partial activation in which some of the sub-arrays are activated at the same time as described above. At that time, the sense amplifiers associated with the sub-arrays that do not operate in the row system generally do not hold data. However, by keeping the data held in the sense amplifiers associated with the sub-arrays that do not operate the row system as described above, the number of sense amplifiers holding the data in the state of waiting for access can be reduced. The hit rate can be increased by increasing the cache memory capacity.

When the method of dividing the cache memory into several banks as described above is applied to the sense amplifier cache system, it means that the sense amplifier group is divided into a plurality of banks. In a general-purpose DRAM, sense amplifiers associated with a plurality of sub-arrays normally perform operations such as sense, latch, and equalize at the same timing. At that time, as described above, the sense amplifier associated with the sub-array which does not operate the row system can be made to stand by while holding the data. Here, a group of sense amplifiers that operate simultaneously is called a bank.
There are some conditions as described below in the method of dividing into banks for increasing the hit rate of the cache memory. (1) Each bank must have an independent sense amplifier.
(2) The sense amplifier of each bank can hold the data of its own bank regardless of the row addresses of other banks. In other words, the sense amplifier of a bank that is not operating in the row system can continue to hold the data of the bank to which it belongs, regardless of the row addresses of other banks. (3) Each bank must have a data path for all input / output pads. In other words, the cache memory is accessed to a specific bank, but in the case of a multi-bit DRAM, it is necessary to supply data from the bank being accessed to all input / output pads at the same timing. Because there is.

[0017]

As described above, the conventional DRAM concentrates all the read data from the increasing sub-array in one place on the chip.
There is a problem in that the data path in the chip becomes long, which hinders the speeding up of data transfer.

The present invention has been made to solve the above-mentioned problems. The data path in the chip is shortened, the speed of data transfer can be increased, and the cache is adopted when the sense amplifier cache system is adopted. An object of the present invention is to provide a dynamic memory that can increase the hit rate of the memory.

[0019]

In order to achieve the object of the present onset Ming, your first direction
And divided into a second direction perpendicular to the first direction.
Multiple sub-arrays, and multiple banks.
Memory cells arranged in a matrix
Memory cell array consisting of
Memory cells formed in the first direction and in the same row
A plurality of word lines connected to each sub-array
Accordingly, the memory cells are formed in the second direction and are in the same row.
A plurality of bit lines connected to the memory cell,
Is formed corresponding to the ray and is connected to the plurality of bit lines.
Note that when the corresponding bit lines are selected
A plurality of sense amplifiers for sense-amplifying the potential read from the recell and the first sense amplifier corresponding to each of the sub-arrays.
Formed in the same direction, the sense of the corresponding sub-array
It is connected to the amplifier and transfers the data from the sense amplifier.
A plurality of data lines formed in the second direction,
A plurality of data line buffer multiplexers each connected to one of the sub-arrays of each bank, and in the second direction
Is formed and the plurality of data line buffers
It is placed on the opposite side of the memory cell array from the perspective of Lexa.
Connected to the multiple data line buffers and multiplexers.
It is characterized by comprising a plurality of continuous data input / output terminals .

[0020]

All the data lines provided corresponding to each sub-array are formed in parallel with the word lines, and the data line buffer / multiplexer group and the input / output pad group are on the same side of the memory chip (bit line). Concentrated on the second side parallel to.

Since the arrangement of the data line group, the data line buffer / multiplexer group, and the input / output pad group is devised in this way, the data path in the chip can be shortened and the speed of data transfer can be increased. become.

Further, a data line buffer / multiplexer is commonly connected to a plurality of data lines corresponding to each one sub-array of different banks, and each bank has a data path for all input / output pad groups. have. Therefore, when the sense amplifier cache method in which the sense amplifier group of each sub-array is used as a cache memory is adopted, it is possible to multiplex the data of a plurality of banks, and thus the hit rate of the cache memory can be increased. Become.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a DRA according to a first embodiment of the present invention.
An example of arrangement of the sub-array 11, the DQ buffer / multiplexer 12, and the I / O pad 13 in the M chip is shown.

FIG. 2 shows one sub-array 11 in FIG.
1 DQ buffer multiplexer 12, 1 I /
The O pad 13 is taken out and an example thereof is shown. As shown in FIGS. 1 and 2, the plurality of sub-arrays 11 includes dynamic memory cells M arranged in rows and columns.
Each of the memory chips 10 has an array of C and is divided into a plurality of parts along a first side X and a second side Y of the memory chip 10 which are perpendicular to each other, and divided into a plurality of banks to control the operation. To be done. In the present embodiment, a plurality (two in this example) of banks are set as a unit of a plurality of subarrays (two in this example) arranged along the first side X of the memory chip. Is divided into

In each of the sub-arrays 11, a plurality of word lines WL connected to the memory cells MC in the same row and formed in parallel with the first side X of the memory chip are provided.
i, and a plurality of bit lines BLi connected to the memory cells MC in the same column and formed parallel to the second side Y perpendicular to the first side of the memory chip. The plurality of word lines WLi are selected by the row decoder 21, and the plurality of bit lines BLi are selected by the column decoder 22.
Is selected by the column selection circuit 23. Further, the row decoder 2 is provided in each of the sub-arrays 11.
A plurality of sense amplifiers 24 for sense-amplifying the potential read from the memory cell of the row selected by 1 are provided.

A plurality of data lines DQi are formed in parallel with the word lines WLi corresponding to the respective sub-arrays 11, and the sense amplifiers of the selected column among the plurality of sense amplifiers 24 of the corresponding sub-array 11 are formed. For transferring data from.

Multiple data line buffers (DQ buffers)
The multiplexer 12 is commonly connected to a plurality of data lines DQi corresponding to each sub-array 11 in each of the plurality of banks, and selectively amplifies the data from the plurality of data lines DQi. It is arranged parallel to the second side Y of the memory chip.

A plurality of data input / output (I / O) pads 1
3 is connected to each of the plurality of data line buffers / multiplexers 12 in correspondence with the second line of the memory chip rather than the plurality of data line buffers / multiplexers 12.
Is arranged in parallel to the second side at a position close to the side Y.

The DQ buffer / multiplexer 1 is used.
Regarding the connection between the data lines DQi of two and two banks, if the data lines DQi of different banks are connected to each other, the load capacitance of the data lines DQi increases and the delay time of data transfer increases, which is not preferable. . Therefore,
The multiplexer of the DQ buffer / multiplexer 12 is, for example, as shown in the drawing, a switch element (for example, a MOS element) corresponding to each data line DQi of a different bank.
The transistor 25) is inserted and connected in series. As a result, it becomes possible to selectively permit data input / output operations by the DQ buffer to different banks.

The data lines DQi of different banks are also provided.
Of the data lines (DQ2, DQ in this example) corresponding to the sub-array located on the side far from the I / O pad 13.
4, ... are data lines (DQ1, DQ in this example) corresponding to the sub-arrays located on the side closer to the I / O pad 13.
3, ...) longer. Therefore, in order to make the wiring resistances of both data lines commonly connected to the DQ buffer / multiplexer 12 substantially equal, increase the wiring resistance of the data line corresponding to the sub-array located far from the I / O pad 13. In order to suppress it, it is desirable to make it thicker than the data line corresponding to the sub-array located on the side close to the I / O pad 13.

The data lines DQi of different banks are also provided.
Among them, the data line corresponding to the sub-array located on the side farther from the I / O pad passes near (or on the sub-array) the sub-array located on the side closer to the I / O pad.

In the DRAM of the first embodiment, the data line DQ provided corresponding to each sub array 11 is provided.
All of i are formed in parallel with the word line WLi, and the data line buffer / multiplexer 12 group and the I / O pad 1 are formed.
The three groups are concentrated on the same side of the memory chip 10 (the second side Y parallel to the bit line).

Since the arrangement of the data line DQi group, the data line buffer / multiplexer 12 group, and the I / O pad 13 group is devised in this way, the data path in the chip 10 is shortened, and the lead frame in the package and It becomes easy to shorten the wiring on the memory mounting circuit board, and it is possible to speed up the data transfer.

Further, in this embodiment, a plurality of sub-arrays 1
1 is the first side X of the memory chip (vertical direction in the figure)
1 is divided into two sub-arrays
It is divided into two banks with one group as a unit. The data line buffer / multiplexer 12 is connected in common to the plurality of data lines DQi corresponding to the respective one sub-arrays of different banks, and each bank has all I / Os.
It has a data path for the O pad 13 group.

Therefore, when the sense amplifier cache system in which the sense amplifier group provided independently for each sub-array is used as the cache memory, the data for each bank can be read out independently, and the cache memory can be read independently. It is possible to increase the hit rate of. In this case, the data is latched by configuring the sense amplifier group of each bank so that it can be controlled to continue holding the data even in the access standby state of its own bank regardless of access to other banks. It is possible to increase the number of sense amplifiers and further increase the hit rate of the cache memory.

When the sense amplifier cache system is adopted, as in the configuration disclosed in detail in Japanese Patent Application No. 4-131095 filed by the applicant of the present application, the dotted line in FIG. As shown, the register circuit 26 that holds the row address for each sub-array and the row address (row address corresponding to the selected row) held in this register circuit 26 and the newly given row address are compared. The comparator 27 is provided.

When the access request and the address are supplied to the sub-array to be accessed, the comparator 27 compares the two row address inputs, and when the row addresses match each other, a hit indicating that there is a hit is issued. A signal is output, and if they do not match, a miss signal is output to notify that a mistake has occurred. When the hit signal is output, the column data corresponding to the column address is read without operating the row system. When the miss signal is output, the register circuit 26, the word line WLi, and the sense amplifier 24 are once reset, and then the newly given row address is set in the register circuit 26.
The row system operates according to the row address newly held in the register circuit 26. Then, the access request and the address are supplied again, the hit determination is performed, and the data of the column corresponding to the column address is read without operating the row system. The above-described operation is sequentially performed in the plurality of sub-arrays 11 by sequentially supplying access requests to the plurality of sub-arrays 11 to be accessed. In this case, in each sub-array 11, it is possible to reselect only the row having a miss, and it is not necessary to reselect all the rows each time a miss occurs.

FIG. 3 shows a DRA according to the second embodiment of the present invention.
An example of arrangement of the sub-array 11, the DQ buffer / multiplexer 12, and the I / O pad 13 in the M chip is shown.

In the second embodiment, as compared with the first embodiment, the second side Y is divided so that the sub-array 11 group is divided into, for example, two banks along the second side Y of the memory chip. 1 is the same as that in FIG. 1 and therefore the same reference numerals are given. Second above
Also in the DRAM of the embodiment, the DRA of the first embodiment is used.
Operation similar to that of M is possible, and DR of the first embodiment
Almost the same effect as AM can be obtained.

[0040]

As described above, according to the DRAM of the present invention, the data path in the chip is shortened and the data transfer can be speeded up. When the sense amplifier cache system is adopted, It is possible to increase the hit rate.

[Brief description of drawings]

FIG. 1 is a sub-array, a DQ buffer, a multiplexer, and an I of a DRAM chip according to a first embodiment of the present invention.
The figure which shows the example of arrangement | positioning of / O pad.

FIG. 2 is a circuit diagram showing one example of one sub array, one DQ buffer, one multiplexer, and one I / O pad taken out in FIG.

FIG. 3 is a diagram illustrating a sub array, a DQ buffer, a multiplexer, and an I in a DRAM chip according to a second embodiment of the present invention.
The figure which shows the example of arrangement | positioning of / O pad.

FIG. 4 is a diagram showing an arrangement example of a sub-array, a DQ buffer, a multiplexer, and an I / O pad in a conventional general-purpose DRAM chip.

[Explanation of symbols]

10 ... Memory chip, X ... First side, Y ... Second side, 1
1 ... Sub array, MC ... Memory cell, WLi ... Word line, BLi ... Bit line, DQi ... Data line, 12 ... DQ
Buffer multiplexer, 13 ... I / O pad, 21
... row decoder, 22 ... column decoder, 23 ... column selection circuit, 24 ... sense amplifier, 25 ... multiplex switch element.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoshi Sakurai 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa 1 Toshiba Microelectronics Stock Association In-house (72) Satoru Takase 1 Komukai-Toshiba, Kawasaki-shi, Kanagawa Within Toshiba Research & Development Center (56) References JP-A-5-334869 (JP, A) JP-A-6-203567 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/40

Claims (22)

(57) [Claims] 1. A plurality of sub-arrays divided and arranged in a first direction and a second direction perpendicular to the first direction, divided into a plurality of banks, and arranged in a matrix. A memory cell array composed of a plurality of memory cells; a plurality of word lines formed in the first direction corresponding to each sub-array and connected to memory cells in the same row; and a plurality of word lines corresponding to each sub-array. A plurality of bit lines formed in the two directions and connected to the memory cells of the same column, and formed corresponding to each of the sub-arrays and connected to the plurality of bit lines, and select the corresponding bit lines. A plurality of sense amplifiers for sense-amplifying the potential read from the memory cell at the time of the operation, and a plurality of sense amplifiers formed in the first direction corresponding to each of the sub-arrays. A plurality of data lines connected to the sense amplifier for transferring data from the sense amplifier, and a plurality of data line buffers / multiplexers formed in the second direction and connected to one of the sub-arrays of each bank And a plurality of data input / output terminals formed in the second direction and arranged on the opposite side of the memory cell array as viewed from the plurality of data line buffer / multiplexers, and connected to the plurality of data line buffer / multiplexers. When,
A semiconductor device comprising: 2. A is divided into a plurality of banks are arranged in the first direction or the second direction, and a memory cell array of sub-arrays of multiple, said first direction corresponding to the sub-arrays of the banks To
Data from each corresponding sub-array
A plurality of data lines to be transferred, a plurality of data line buffer / multiplexers which are formed to be separated from each other in the second direction and are connected to the sub-arrays of the respective banks, and to be separated from each other in the second direction. A plurality of data input / output terminals formed and connected to the corresponding data line buffer / multiplexers, wherein the plurality of data line buffer / multiplexers include the plurality of data input / output terminals and the plurality of sub-arrays. A semiconductor device characterized in that it is arranged between. 3. A plurality of rows arranged in rows and columns, respectively.
Consists of memory cells in the first or second direction
A memory cell array which is divided into a plurality of banks arranged and which is composed of a plurality of sub-arrays; and a plurality of memory cells of one row which extend in the first direction and are provided corresponding to the respective sub-arrays. A plurality of word lines that are commonly connected to each other and a plurality of memory cells that extend in the second direction and are provided corresponding to the respective sub-arrays, and that connect a plurality of memory cells in a column of the corresponding sub-arrays in common. And a plurality of bit lines that are formed corresponding to the sub-arrays
Connected to bit lines, select corresponding bit lines
Sense amplification of the potential read from the memory cell
A plurality of sense amplifiers, a plurality of data line buffer / multiplexers formed separately from each other in the second direction, and at least a data line portion extending in the first direction. A plurality of data lines connecting the plurality of sub-arrays to the plurality of data line buffer multiplexers so that the line buffer multiplexer is connected to the sub-array of each bank; and a plurality of data lines formed separately from each other in the second direction. , A plurality of data input / output terminals respectively connected to the corresponding data line buffer / multiplexers, wherein the plurality of data line buffer / multiplexers are arranged between the plurality of data input / output terminals and the sub-array. A semiconductor device characterized by the above. 4. A plurality of sub-arrays divided and arranged in a first direction and a second direction perpendicular to the first direction, divided into a plurality of banks, and arranged in a matrix. A memory cell array composed of a plurality of memory cells; a plurality of word lines formed in the first direction corresponding to each sub-array and connected to memory cells in the same row; and a plurality of word lines corresponding to each sub-array. A plurality of bit lines formed in the two directions and connected to the memory cells of the same column, and formed corresponding to each of the sub-arrays and connected to the plurality of bit lines, and select the corresponding bit lines. A plurality of sense amplifiers for sense-amplifying the potential read from the memory cell at the time of the operation, and a plurality of sense amplifiers formed in the first direction corresponding to each of the sub-arrays. A plurality of data lines connected to the sense amplifier for transferring data from the sense amplifier; a plurality of multiplexers formed in the second direction and connected to one of the sub-arrays of each bank; A plurality of data buffers formed in two directions and connected to respective corresponding multiplexers; and a plurality of data buffers formed in the second direction and on the opposite side of the memory cell array when viewed from the plurality of data buffers and the plurality of multiplexers. A plurality of data input / output terminals that are arranged and connected to the plurality of data buffers, and a semiconductor device. 5. A is divided into a plurality of banks are arranged in the first direction or the second direction, and a memory cell array of sub-arrays of multiple, said first direction corresponding to the sub-arrays of the banks To
Data from each corresponding sub-array
A plurality of data lines to be transferred, a plurality of multiplexers formed separately from each other in the second direction and connected to the sub-array of each bank, and a plurality of multiplexers formed separately from each other in the second direction, respectively. A plurality of data buffers connected to the corresponding multiplexer, and a plurality of data input / output terminals formed separately from each other in the second direction and connected to the corresponding data buffers, respectively; 2. The semiconductor device, wherein the multiplexer and the plurality of data buffers are arranged between the plurality of data input / output terminals and the plurality of sub-arrays. 6. A plurality of rows arranged in rows and columns, respectively.
Consists of memory cells in the first or second direction
A memory cell array which is divided into a plurality of banks arranged and which is composed of a plurality of sub-arrays; and a plurality of memory cells of one row which extend in the first direction and are provided corresponding to the respective sub-arrays. A plurality of word lines that are commonly connected to each other and a plurality of memory cells that extend in the second direction and are provided corresponding to the respective sub-arrays, and that connect a plurality of memory cells in a column of the corresponding sub-arrays in common. And a plurality of bit lines that are formed corresponding to the sub-arrays
Connected to bit lines, select corresponding bit lines
Sense amplification of the potential read from the memory cell
A plurality of sense amplifiers, a plurality of multiplexers formed separately from each other in the second direction, a plurality of data line buffers formed separately from each other in the second direction, and the first direction A plurality of data lines connecting at least the data line portion extending to the plurality of sub-arrays and the plurality of multiplexers so that each multiplexer is connected to the sub-array of each bank; A plurality of data input / output terminals that are formed separately from each other in the direction and are connected to corresponding data line buffers, respectively, and the plurality of multiplexers and the plurality of data line buffers are the plurality of data input / output terminals. And a semiconductor device arranged between the sub-array and the sub-array. 7. A plurality of sub-arrays divided and arranged in a first direction and a second direction perpendicular to the first direction, divided into a plurality of banks, and arranged in a matrix. A memory cell array composed of a plurality of memory cells; a plurality of word lines formed in the first direction corresponding to each sub-array and connected to memory cells in the same row; and a plurality of word lines corresponding to each sub-array. A plurality of bit lines formed in two directions and connected to the memory cells in the same column, and formed on the memory chip corresponding to each of the sub-arrays and connected to the plurality of bit lines. A plurality of sense amplifiers for sense-amplifying the potential read from the memory cell when the bit line to be selected is selected, and the sense amplifiers are formed in the first direction corresponding to the sub-arrays. A plurality of data lines connected to the sense amplifiers of the corresponding sub-arrays and transferring data from the sense amplifiers; and a plurality of switches formed in the second direction and respectively connected to one of the sub-arrays of each bank. An element, a plurality of data line buffers formed in the second direction and connected to corresponding switch elements respectively, and a plurality of data line buffers formed in the second direction and including the plurality of data buffers and the plurality of switch elements. A plurality of data input / output terminals arranged on the opposite side of the memory cell array and connected to the plurality of data buffers. 8. is divided into a plurality of banks are arranged in the first direction or the second direction, and a memory cell array of sub-arrays of multiple, said first direction corresponding to the sub-arrays of the banks To
Data from each corresponding sub-array
A plurality of data lines to be transferred, a plurality of switch elements formed separately from each other in the second direction, and connected to a sub-array of each bank, and a plurality of switch elements formed separately from each other in the second direction, A plurality of data buffers connected to respective corresponding switch elements, and a plurality of data input / output terminals formed separately from each other in the second direction and connected to respective corresponding data buffers, A semiconductor device, wherein the plurality of switch elements and the plurality of data buffers are arranged between the plurality of data input / output terminals and the plurality of sub-arrays. 9. A plurality of rows, each arranged in rows and columns.
Consists of memory cells in the first or second direction
A memory cell array which is divided into a plurality of banks arranged and which is composed of a plurality of sub-arrays; and a plurality of memory cells of one row which extend in the first direction and are provided corresponding to the respective sub-arrays. A plurality of word lines that are commonly connected to each other and a plurality of memory cells that extend in the second direction and are provided corresponding to the respective sub-arrays, and that connect a plurality of memory cells in a column of the corresponding sub-arrays in common. And a plurality of bit lines that are formed corresponding to the sub-arrays
Connected to bit lines, select corresponding bit lines
Sense amplification of the potential read from the memory cell
A plurality of sense amplifiers, a plurality of switch elements formed separately from each other in the second direction, a plurality of data line buffers formed separated from each other in the second direction, and the first A plurality of data lines each including at least a data line portion extending in a direction, and connecting the plurality of sub-arrays to the plurality of switch elements so that each switch element is connected to the sub-array of each bank; A plurality of data input / output terminals formed separately from each other in the second direction and connected to corresponding data line buffers, respectively, wherein the plurality of switch elements and the plurality of data line buffers are provided in the plurality of data input / output terminals. A semiconductor device arranged between a data input / output terminal and the plurality of sub-arrays. 10. A plurality of sub-arrays divided and arranged in a first direction and a second direction perpendicular to the first direction, divided into a plurality of banks, and arranged in a matrix. A memory cell array composed of a plurality of memory cells; a plurality of word lines formed in the first direction corresponding to each sub-array and connected to memory cells in the same row; and a plurality of word lines corresponding to each sub-array. A plurality of bit lines formed in the two directions and connected to the memory cells of the same column, and formed corresponding to each of the sub-arrays and connected to the plurality of bit lines, and select the corresponding bit lines. A plurality of sense amplifiers for sense-amplifying the potential read out from the memory cell when a plurality of sub-arrays are formed, the sub-arrays being formed in the first direction corresponding to the sub-arrays, respectively. A plurality of data lines that are connected to the sense amplifier of the array and transfer data from the sense amplifier; a plurality of multiplexers that are formed in the second direction and that are respectively connected to one of the sub-arrays of each bank; A plurality of data line buffers, which are formed in two directions and are connected to corresponding multiplexers, respectively, and a semiconductor device. 11. is divided into a plurality of banks are arranged in the first direction or the second direction, and a memory cell array of sub-arrays of multiple, said first direction corresponding to the sub-arrays of the banks To
Data from each corresponding sub-array
A plurality of data lines to be transferred, a plurality of multiplexers formed separately from each other in the second direction and connected to the sub-array of each bank, and a plurality of multiplexers formed separately from each other in the second direction, respectively. A plurality of data line buffers connected to corresponding multiplexers, wherein the plurality of multiplexers are arranged between the plurality of data line buffers and the plurality of sub-arrays. 12. A plurality arranged in rows and columns, respectively.
Memory cells of the first direction or the second direction
A memory cell array composed of a plurality of sub-arrays divided into a plurality of banks arranged in a row; and a plurality of memories in one row of the corresponding sub-array, the memory cells extending in the first direction and provided corresponding to the respective sub-arrays. A plurality of word lines that connect the cells in common and a plurality of memory cells that extend in the second direction and are provided corresponding to the respective sub-arrays and that connect a plurality of memory cells in a column of the corresponding sub-arrays are connected in common. And a plurality of bit lines that are formed corresponding to each of the sub-arrays,
Connected to bit lines, select corresponding bit lines
Sense amplification of the potential read from the memory cell
A plurality of sense amplifiers, a plurality of multiplexers formed separately from each other in the second direction, a plurality of data line buffers formed separately from each other in the second direction, and the first direction A plurality of data lines connecting the plurality of sub-arrays to the plurality of multiplexers so that each multiplexer is connected to the sub-array of each bank, A semiconductor device, wherein a plurality of multiplexers are arranged between the plurality of data line buffers and the plurality of sub arrays. 13. A plurality of sub-arrays divided and arranged in a first direction and a second direction perpendicular to the first direction, divided into a plurality of banks, and arranged in a matrix. A memory cell array composed of a plurality of memory cells; a plurality of word lines formed in the first direction corresponding to each sub-array and connected to memory cells in the same row; and a plurality of word lines corresponding to each sub-array. A plurality of bit lines formed in the two directions and connected to the memory cells of the same column, and formed corresponding to each of the sub-arrays and connected to the plurality of bit lines, and select the corresponding bit lines. A plurality of sense amplifiers for sense-amplifying the potential read out from the memory cell when a plurality of sub-arrays are formed. A plurality of data lines that are connected to the sense amplifier of the array and transfer data from the sense amplifier; a plurality of switch elements that are formed in the second direction and that are respectively connected to one of the sub-arrays of each bank; A semiconductor device comprising: a plurality of data line buffers formed in a second direction and connected to corresponding switch elements, respectively. 14. is divided into a plurality of banks are arranged in the first direction or the second direction, and a memory cell array of sub-arrays of multiple, said first direction corresponding to the sub-arrays of the banks To
Data from each corresponding sub-array
A plurality of data lines to be transferred, a plurality of switch elements formed separately from each other in the second direction, and connected to a sub-array of each bank, and a plurality of switch elements formed separately from each other in the second direction, A plurality of data line buffers respectively connected to corresponding switch elements, wherein the plurality of switch elements are arranged between the plurality of data line buffers and the plurality of sub-arrays. Semiconductor device. 15. A plurality arranged in rows and columns, respectively.
Memory cells of the first direction or the second direction
A memory cell array composed of a plurality of sub-arrays divided into a plurality of banks arranged in a row; and a plurality of memories in one row of the corresponding sub-array, the memory cells extending in the first direction and provided corresponding to the respective sub-arrays. A plurality of word lines that connect the cells in common and a plurality of memory cells that extend in the second direction and are provided corresponding to the respective sub-arrays and that connect a plurality of memory cells in a column of the corresponding sub-arrays are connected in common. And a plurality of bit lines that are formed corresponding to each of the sub-arrays,
Connected to bit lines, select corresponding bit lines
Sense amplification of the potential read from the memory cell
A plurality of sense amplifiers, a plurality of switch elements formed separately from each other in the second direction, a plurality of data line buffers formed separated from each other in the second direction, and the first A plurality of data lines each including at least a data line portion extending in the direction, and connecting the plurality of sub-arrays to the plurality of switch elements so that each switch element is connected to the sub-array of each bank. A semiconductor device, wherein the plurality of switch elements are arranged between the plurality of data line buffers and the plurality of sub-arrays. 16. The semiconductor device according to claim 1, wherein the plurality of banks are arranged in the second direction. 17. The semiconductor device according to claim 1, wherein the plurality of banks are arranged in the first direction. 18. Of the plurality of data lines, a data line provided for a sub-array farther from the plurality of data input / output terminals of the plurality of sub-arrays is closer to the plurality of data input / output terminals. 10. The semiconductor device according to claim 1, wherein the semiconductor device passes through one of the sub arrays. 19. The size of a data line of the plurality of data lines provided for the sub-array farther from the plurality of data input / output terminals of the plurality of sub-arrays is the plurality of data input / outputs. 10. The semiconductor device according to claim 1, wherein the size is larger than the size of the data line provided for the sub-array closer to the terminal. 20. extend in the first direction, a plurality of word lines, each one of the sub-array a plurality of memory cells of one row of the plurality of sub-arrays are connected in common, the second In the direction of each of the plurality of sub
Multiple memories in a row of a sub-array of an array
A plurality of bit lines that connect cells in common and a plurality of cells that sense and amplify the potentials of the plurality of bit lines.
Claim, further comprising a Suanpu 2,5,8,11,1
4. The semiconductor device according to any one of 4 above. 21. Among the plurality of data lines, a data line provided for a sub-array farther from the plurality of data line buffers of the plurality of sub-arrays is closer to the plurality of data line buffers. The semiconductor device according to any one of claims 10 to 15, wherein the semiconductor device passes over the sub-array. 22. Among the plurality of data lines, the dimension of the data line provided for the sub-array farther from the plurality of data line buffers of the plurality of sub-arrays is closer to that of the plurality of data line buffers. 16. The semiconductor device according to claim 10, wherein the size is larger than the size of the data line provided for the sub-array.