JP3404310B2 - Digital modulated wave demodulation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit for digitally modulated waves used in satellite communication, satellite broadcasting and the like.

[0002]

2. Description of the Related Art In the transmission of video signals and audio signals by satellite communication, satellite broadcasting, etc., multi-level QAM and multi-phase PSK are used as a modulation system. On the receiving side, a demodulation circuit for demodulating a modulated wave by multilevel QAM or multiphase PSK is required. FIG. 3 is a block diagram showing a demodulation circuit for a digitally modulated wave using conventional digital PLL carrier reproduction.

The input terminal 1 has, for example, a multi-phase PSK (n
A modulated wave of phase PSK) is input. The input n-phase PSK modulated wave is distributed to the in-phase detector 2 and the quadrature detector 3. A local oscillation signal having a fixed frequency is supplied from the local oscillator 5 to the in-phase detector 2. Further, the quadrature detector 3 is supplied with a signal obtained by shifting the local oscillation signal from the local oscillator 5 by 90 degrees by the π / 2 phase shift circuit 4.

The detection outputs of the in-phase detector 2 and the quadrature detector 3 are input to AD converters 6 and 7, respectively, and converted into digital signals. Each digital signal is a digital low-pass filter 8, 9 having the same frequency transfer characteristic.
The spectrum is shaped by. The digital low-pass filters 8 and 9 are filters having transfer characteristics required to prevent intersymbol interference in digital data transmission, and are designed to obtain so-called roll-off characteristics when combined with a filter on the transmission side. To be done. Therefore, the outputs of the digital low-pass filters 8 and 9 are spectrally shaped so that the eye opening ratio is sufficiently large.

The outputs of the digital low pass filters 8 and 9 are branched and also input to the clock recovery circuit 32. The clock recovery circuit 32 extracts the symbol timing component in the signal and supplies the clock signal as a converted clock signal to the AD converters 6 and 7.

Branch outputs of the digital low pass filters 8 and 9 are input to a complex multiplier 10. Complex multiplier 10
Can realize exactly the same operation as the operation of the frequency converter in the intermediate frequency band in the baseband. Complex multiplier 10
The output of is input to the phase detector 11. Phase detector 1
1 is an input signal and a numerically controlled oscillator (NCO) 1 described later.
The phase difference with 5 is detected.

The phase difference information from the phase detector 11 is used as a loop filter 12 and an adder 14 for carrier regeneration.
Is input to the frequency control terminal of the numerically controlled oscillator 15. The numerically controlled oscillator 15 is composed of a cumulative addition circuit that does not prohibit overflow. Then, the addition operation up to the dynamic range is performed according to the value of the signal input to the frequency control terminal, so that the oscillation state occurs, and the oscillation frequency changes according to the output of the adder 14. That is, the numerically controlled oscillator 15 operates in the same manner as the voltage controlled oscillator (VCO) in the analog circuit. However, the oscillating frequency is more stable than the oscillating frequency of the VCO, has a stability higher than that of a VCO (VCXO) using a crystal, and has a wide frequency variable range that cannot be realized by the VCXO.

The output of the complex multiplier 10 is also input to the frequency error detection circuit 13. The frequency error detection circuit 13 has
The frequency error between the frequency of the input signal and the desired frequency is detected, and the frequency error value is output to the adder 14. Adder 14
Adds the output value of the loop filter 12 and the frequency error value.

The output of the numerically controlled oscillator 15 is input to a data conversion circuit 16 having a sine characteristic and a data conversion circuit 17 having a cosine characteristic. Data conversion circuit 1
The outputs of 6 and 17 are input to the complex multiplier 10. The loop that exits the complex multiplier 10 and returns to the complex multiplier 10 is a fully digital configured PLL. Here, if the loop filter 12 includes a circuit having a perfect integration system, P
The frequency pull-in range of LL is infinite in principle.

Further, I, which is output from the complex multiplier 10,
The Q signal is supplied to a decoder using, for example, Viterbi decoding. The decoder makes a data decision from the I and Q signals.

A configuration similar to the demodulation circuit shown in FIG. 3 is described in Japanese Patent Laid-Open No. 5-41717. As described in JP-A-5-41717, the demodulation circuit as shown in FIG. 3 has a problem with frequency detuning. In satellite communication and satellite broadcasting, it is difficult to increase the stability of the frequency converter inside the repeater mounted on the satellite, and generally there is a large frequency detuning. Therefore, detuning may occur in the frequency of the signal input to the input terminal 1 shown in FIG.

On the receiver side, since a frequency synthesizer type down converter having a stable frequency is expensive, generally an inexpensive circuit is used. Then, frequency detuning may occur even in the down converter in the receiver. For example, in the satellite communication using the 12 GHz band, an error of about 2 MHz in frequency down-conversion of the receiver may occur.

When the input frequency is detuned and the center frequency (carrier frequency) of the modulated wave spectrum is deviated, the local oscillation signal from the local oscillator 5 is a fixed frequency signal. The spectrums of the detection outputs of the in-phase detector 2 and the quadrature detector 3 are not symmetrical with respect to direct current. The detection outputs of the in-phase detector 2 and the quadrature detector 3 are spectrally shaped by the digital low-pass filters 8 and 9, but the characteristics of the digital low-pass filters 8 and 9 are symmetrical with respect to direct current. The spectrum of the signal is partially scraped off because of the detuning. Then, the transfer characteristic for preventing intersymbol interference is not satisfied. As a result, there is a problem that the eye opening rate is lowered and the code error rate is increased.

In order to deal with such a problem, it is conceivable to install the digital low-pass filters 8 and 9 in the subsequent stage of the complex multiplier 10 as shown in FIG. According to the configuration shown in FIG. 4, the influence of frequency detuning is removed by the complex multiplier 10, so that the spectrum of the signal is prevented from being partially scraped.

[0015]

However, if the digital low-pass filters 8 and 9 are installed after the complex multiplier 10 as shown in FIG. 4, the digital low-pass filters 8 and 9 are provided in the PLL loop. Has been installed. Since the digital low-pass filters 8 and 9 are generally composed of transversal filters, the structure having several tens of taps is required to improve the transfer characteristic. Then,
This means that a large delay element has been inserted in the PLL. As a result, the feedback control becomes unstable and the jitter characteristic and the PLL pull-in characteristic deteriorate.

Therefore, an object of the present invention is to provide a demodulation circuit for a digital modulated wave which does not deteriorate the receiver performance even when there is frequency detuning.

Incidentally, Japanese Patent Laid-Open Nos. 5-41717 and 5-41718 also describe a demodulation circuit for a digitally modulated wave having the same purpose, but its configuration is described in detail below. The configuration of the invention is different.

[0018]

A digital modulated wave demodulation circuit according to the present invention converts a detection output obtained by detecting an input signal into a digital detection signal, and the digital detection signal includes a digital PLL including a complex multiplier. It is a demodulation circuit for a digital modulated wave which is input to the loop and supplies the output of the PLL loop to a decoder. In the locked state of the PLL loop, a digital low pass filter is connected to the latter stage of the complex multiplier, and a digital low pass filter is used when the phase is pulled. This is a configuration including filter switching means for connecting the band pass filter to the preceding stage of the complex multiplier.

The digital modulated wave demodulation circuit is provided with a digital low-pass filter in the front and rear stages of the complex multiplier, and the filter switching means supplies the digital detected signal to the complex multiplier in the locked state of the PLL loop. The first switch, which supplies the output of the digital low-pass filter provided in the preceding stage of the complex multiplier to the complex multiplier when the phase is pulled in, and the latter stage of the complex multiplier when the PLL loop is locked. A second switch that selects the output of the digital low-pass filter and selects the output of the complex multiplier when the phase is pulled may be included. In this case, since the digital low-pass filters are installed before and after the complex multiplier, the switching control is easy.

The digital low-pass filter connected in the PLL loop and the digital low-pass filter connected before the complex multiplier are combined into one digital low-pass filter. It may be arranged to make a switched connection of two digital low-pass filters. In this case, since only one digital low pass filter is used, the circuit scale can be reduced and the cost can be reduced. One digital low-pass filter means a filter that filters both I and Q signals.

Here, the filter switching means supplies the digital detection signal to the complex multiplier in the locked state of the PLL loop, and supplies the output of the digital low-pass filter to the complex multiplier when the phase is pulled in. And a second switcher that selects the output of the digital low-pass filter when the PLL loop is locked, and selects the output of the complex multiplier when the phase is locked, and the output of the complex multiplier is digital when the PLL loop is locked. A third switch that supplies the digital detection signal to the low pass filter and supplies the digital detection signal to the digital low pass filter when the phase is pulled may be included.

A frequency error detection circuit for detecting a deviation of the PLL output frequency from the lock frequency is provided, and the PLL loop outputs a signal of a frequency corresponding to input data, a numerical control oscillator, an input signal and an output of the numerical control oscillator. And a phase detector that detects the phase difference and outputs phase difference information, and further includes an adder that adds the frequency shift by the frequency error detection circuit to the phase difference information and supplies it to the numerically controlled oscillator. May be. According to such a configuration,
Even when the frequency detuning is great, the PLL can stably pull in the frequency.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a demodulation circuit for a digitally modulated wave according to the present invention.
As shown in FIG. 1, in this embodiment, switching devices 18 and 19 are provided between the digital low-pass filters 8 and 9 and the complex multiplier 10 in addition to the configuration shown in FIG. There is. The switches 18 and 19 select and output either the input or the output of the digital low-pass filters 8 and 9. Further, digital low-pass filters 20 and 21 are provided at the subsequent stage of the complex multiplier 10 in the PLL loop, and switching devices 22 and 23 are provided at the subsequent stages. The switching devices 22 and 23 include the digital low-pass filter 20,
One of the 21 inputs and outputs is selected and output. Further, a lock detection circuit 31 for detecting the frequency lock state based on the output of the phase detector 11 is provided.

Next, the operation will be described. Input terminal 1
In, for example, a modulated wave by polyphase PSK (n-phase PSK) is input. The input n-phase PSK modulated wave is distributed to the in-phase detector 2 and the quadrature detector 3. In-phase detector 2
A local oscillation signal having a fixed frequency is supplied from the local oscillator 5. Further, the quadrature detector 3 includes a local oscillator 5
The local oscillation signal from is supplied with a signal whose phase is shifted by 90 degrees by the π / 2 phase shift circuit 4.

The detection outputs of the in-phase detector 2 and the quadrature detector 3 are input to AD converters 6 and 7, respectively, and converted into digital signals. Each digital signal is a digital low-pass filter 8, 9 having the same frequency transfer characteristic.
And input to the switches 18, 19. The digital low pass filters 8 and 9 shape the spectrum of the input signal. The outputs of the digital low pass filters 8 and 9 are branched and also input to the clock recovery circuit 32. The clock recovery circuit 32 extracts the symbol timing component in the signal and supplies the clock signal as a converted clock signal to the AD converters 6 and 7. The clock recovery circuit 32
May introduce the output of the complex multiplier 10.

At the time of the pull-in operation of the PLL after the signal is input, the switches 18 and 19 select the outputs of the digital low-pass filters 8 and 9. It is recognized by the control signal from the lock detection circuit 31 that the PLL is in the pull-in state. In this example, the control signal becomes low level during the pull-in operation. When the PLL is locked,
The switching devices 18 and 19 are the digital low-pass filters 8 and
Select the 9 input. That is, a signal that does not pass through the digital low pass filters 8 and 9 is supplied to the complex multiplier 10. The lock is recognized by the control signal from the lock detection circuit 31. In this example, the control signal becomes high level in the locked state.

The outputs of the switches 18, 19 are the complex multiplier 10
Entered in. The complex multiplier 10 can realize exactly the same operation as that of the frequency converter in the intermediate frequency band in the baseband. The output of the complex multiplier 10 is input to the digital low pass filters 20 and 21 and the switches 22 and 23.

During the pull-in operation of the PLL, the switching device 2
2 and 23 select the input of the digital low pass filters 20 and 21. That is, a signal that does not pass through the digital low pass filters 20 and 21 is supplied to the PLL loop. When the PLL is locked, the switching devices 22, 2
3 selects the output of the digital low pass filters 20 and 21.

Therefore, during the pull-in operation of the PLL, P
This means that the digital low-pass filters 20 and 21 which are delay elements do not exist in the LL loop. Therefore, PL
The L pull-in characteristic is improved as compared with the conventional case. Also,
The frequency pull-in range can be wide. At this time, since the input signal has passed through the digital low pass filters 8 and 9, the input signal is spectrally shaped so that the eye opening ratio is sufficiently large.

In the locked state of the PLL, the spectrum shaping is realized by the digital low pass filters 20 and 21 in the latter stage of the complex multiplier 10. Therefore, in the frequency locked state, the effect of frequency detuning is removed by the complex multiplier 10, so that the spectrum of the signal is prevented from being partially scraped off, and accurate spectrum shaping is performed. Note that the digital low-pass filters 20, 21
Is configured so that its characteristics are the same as those of the digital low pass filters 8 and 9.

The outputs of the switches 22 and 23 are the phase detector 11
Entered in. The phase detector 11 detects the phase difference between the input signal and the numerically controlled oscillator (NCO) 15. The phase difference information from the phase detector 11 is input to the frequency control terminal of the numerically controlled oscillator 15 via the loop filter 12 and the adder 14 for carrier regeneration. The numerically controlled oscillator 15 is composed of a cumulative addition circuit that does not prohibit overflow. Then, the addition operation up to the dynamic range is performed according to the value of the signal input to the frequency control terminal, so that the oscillation state occurs, and the oscillation frequency changes with the output of the adder 14.

The output of the complex multiplier 10 is also input to the frequency error detection circuit 13. The frequency error between the frequency of the input signal and the desired frequency is detected, and the frequency error value is added by the adder 1
Output to 4. The adder 14 adds the output value of the loop filter 12 and the frequency error value. The frequency error value is for correcting the data input to the numerically controlled oscillator 15 so that it falls within the pull-in range of the digital PLL. If the input signal is supplied to the PLL loop as it is when the frequency detuning is severe, it may be impossible for the PLL to lock the frequency. However, in this embodiment, the frequency shift is corrected by the adder 14, so that the PLL is stable. Frequency pulling can be performed.

The lock detection circuit 31 detects the frequency lock state of the PLL from the phase difference information from the phase detector 11. If it is in the locked state, the control signal is set to the high level, and if it is in the phase pull-in state, the control signal is set to the low level.

The output of the numerically controlled oscillator 15 is input to a data conversion circuit 16 having a sine characteristic and a data conversion circuit 17 having a cosine characteristic. Data conversion circuit 1
The outputs of 6 and 17 are input to the complex multiplier 10. The loop that exits the complex multiplier 10 and returns to the complex multiplier 10 is a fully digital configured PLL. All the circuits after the A / D converters 6 and 7 are realized by digital signal processing.

Further, I, which is output from the complex multiplier 10,
The Q signal is supplied to a decoder using, for example, Viterbi decoding. The decoder makes a data decision from the I and Q signals.

FIG. 2 is a block diagram showing another example of the configuration of the demodulation circuit for a digital modulated wave according to the present invention. In the configuration shown in FIG. 1, since the digital low-pass filters 8 and 9 and the digital low-pass filters 20 and 21 are installed before and after the complex multiplier 10, the circuit scale becomes large and the cost increases. Therefore, the embodiment shown in FIG. 2 is devised to reduce the number of digital low-pass filters.

In the configuration shown in FIG. 2, switching devices 33 and 34 and switching devices 18 and 19 are provided before and after the digital low-pass filters 8 and 9 in addition to the configuration shown in FIG. . In addition, the switch 22 is provided at the subsequent stage of the complex multiplier 10.
23 are provided. The switchers 33 and 34 select either the output of the AD converters 6 and 7 or the output of the complex multiplier 10. Switching device 18, 19 A-D converter 6, 7
Or the output of the digital low pass filters 8 and 9 is selected. Then, the switching devices 33, 34
Selects one of the outputs of the digital low pass filters 8 and 9 and the output of the complex multiplier 10. Further, a lock detection circuit 31 for detecting the frequency lock state based on the output of the phase detector 11 is provided.

During the pull-in operation of the PLL after the signal is input, the lock detection circuit 31 sets the control signal to the low level. In this state, the changeover devices 33 and 34 are set to the A-D
The outputs of the converters 6 and 7 are selected and output to the digital low pass filters 8 and 9. The switches 18 and 19 select the outputs of the digital low pass filters 8 and 9. Further, the switches 22 and 23 select the output of the complex multiplier 10. Therefore, there is no digital low pass filter in the PLL loop.

Therefore, as in the case of the configuration shown in FIG. 1, the digital low-pass filters 20 and 21, which are delay elements, do not exist in the PLL loop during the pull-in operation of the PLL. Therefore, the PLL pull-in characteristic is improved as compared with the conventional case. Also, the frequency pull-in range can be wide.

In the locked state of the PLL, the lock detection circuit 31 sets the control signal to the high level. In this state,
The outputs of the AD converters 6 and 7 are input to the complex multiplier 10 via the switches 18 and 19. Therefore, the complex multiplier 1
This means that there is no digital low-pass filter in the signal route before 0. Further, since the switches 33 and 34 select the output of the complex multiplier 10 and the switches 22 and 23 select the outputs of the digital low pass filters 8 and 9, the digital low pass filters 8 and 9 are PLL loops. Will exist within.

Therefore, as in the case of the configuration shown in FIG. 1, the spectrum shaping is realized by the digital low pass filters 20 and 21 in the latter stage of the complex multiplier 10. Therefore, in the frequency locked state, the effect of frequency detuning is removed by the complex multiplier 10, so that the spectrum of the signal is prevented from being partially scraped off, and accurate spectrum shaping is performed.

[0042]

As described above, according to the present invention, the demodulation circuit for a digital modulated wave is connected to the digital low pass filter in the latter stage of the complex multiplier in the locked state of the PLL loop, and the digital low pass is used in the phase pull-in. Since the configuration is provided with the filter switching means that connects the pass filter to the preceding stage of the complex multiplier, a demodulation circuit for a digital modulated wave that does not deteriorate the receiver performance even when there is frequency detuning is provided. There is an effect that can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a demodulation circuit for a digitally modulated wave according to the present invention.

FIG. 2 is a block diagram showing another configuration example of a demodulation circuit for digitally modulated waves according to the present invention.

FIG. 3 is a block diagram showing a conventional demodulation circuit for digitally modulated waves.

FIG. 4 is a block diagram showing another conventional demodulation circuit for digitally modulated waves.

[Explanation of symbols]

1 input terminal 2 In-phase detector 3 Quadrature detector 4π / 2 phase shift circuit 5 Local oscillator 6,7 A-D converter 8,9 Digital low pass filter 10 Complex multiplier 11 Phase detector 12 loop filter 13 Frequency error detection circuit 14 adder 15 Numerically controlled oscillator (NCO) 16,17 Data conversion circuit 18, 19 switch 20,21 Digital low pass filter 22, 23 switch 31 Lock detection circuit 32 clock recovery circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-209904 (JP, A) JP-A-8-223238 (JP, A) JP-A-5-41717 (JP, A) JP-A-5- 41718 (JP, A) JP-A-2-32648 (JP, A) JP-A-5-66259 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/00 H03D 3 / 00 H04L 7/00

Claims (5)

(57) [Claims] 1. A detection output obtained by detecting an input signal is converted into a digital detection signal, and the digital detection signal is input to a digital PLL loop including a complex multiplier to generate a PL signal.
In a digital modulation wave demodulation circuit for supplying the output of the L loop to a decoder, a digital low pass filter is connected to the latter stage of the complex multiplier in a locked state of the PLL loop, and the digital low pass filter is connected to the digital low pass filter when the phase is pulled in. A demodulation circuit for digitally modulated waves, which is provided with a filter switching means connected to the front stage of a complex multiplier. 2. A digital low-pass filter is provided before and after the complex multiplier, and the filter switching means supplies a digital detection signal to the complex multiplier in the locked state of the PLL loop and the complex multiplication at the time of phase pull-in. A first switch for supplying the output of a digital low-pass filter provided in the front stage of the multiplier to the complex multiplier, and a digital low pass provided in the latter stage of the complex multiplier when the PLL loop is locked. 2. A demodulation circuit for digitally modulated waves according to claim 1, further comprising a second switcher which selects an output of the pass filter and selects an output of the complex multiplier when the phase is pulled. 3. A digital low-pass filter connected in the PLL loop and a digital low-pass filter connected before the complex multiplier are combined into one digital low-pass filter. The demodulation circuit for digitally modulated waves according to claim 1, wherein the one digital low-pass filter is switched and connected. 4. The filter switching means supplies a digital detection signal to the complex multiplier in a locked state of the PLL loop, and supplies an output of the digital low-pass filter to the complex multiplier during phase pull-in. A second switch that selects the output of the digital low-pass filter when the PLL loop is locked, and selects the output of the complex multiplier when the phase is locked; and the output of the complex multiplier when the PLL loop is locked. 4. A demodulator circuit for a digital modulated wave according to claim 3, further comprising: a third switch for supplying the digital detected signal to the digital low-pass filter while supplying the digital detected signal to the digital low-pass filter. 5. A frequency error detection circuit for detecting a deviation of a PLL output frequency from a lock frequency, wherein the PLL loop outputs a signal having a frequency according to input data, an input signal and a numerical control oscillator. And a phase detector that outputs phase difference information by detecting the phase difference of the output of the adder, and further supplies a frequency shift by the frequency error detection circuit to the phase difference information and supplies it to the numerically controlled oscillator. A demodulation circuit for a digitally modulated wave according to any one of claims 1 to 4, including: