JP3403648B2 - Clock regeneration signal generation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a π / 4 shift QP.
The present invention relates to an instantaneous phase detection circuit and a clock recovery signal generation circuit provided in a delay detection circuit for an SK signal.

[0002]

2. Description of the Related Art Since a digital modulation system for digital mobile communication has various advantages, modulation is performed while shifting the phase axis by π / 4 for each symbol period (for example, 2 bits) which is one information unit. The π / 4 shift QPSK method is used (reference 1). In addition, a π / 4 shift QPSK system differential detection circuit that can realize downsizing of a modulation structure and low power consumption has also been proposed (Reference 2).

Reference 1: "Proposal of Linear Modulation System for Digital Mobile Communication", Yoshihiko Akaiwa, Yoshinori Nagata, 1985 General Conference of IEICE, NO. 2348 Document 2: “π / 4 shift Q for digital cordless telephones”
PSK differential detection circuit ”, Hitoshi Shinoda, Tsutomu Suda, Kenzo Urabe, 1992 IEICE Spring Conference, NO. B-
344 FIG. 20 shows a block diagram of a conventional differential detection circuit described in Document 2.

A delay detection circuit for detecting a π / 4 shift QPSK signal will be described below with reference to FIG. The differential detection circuit includes a set terminal 1, an oscillator 2, an instantaneous phase detection circuit 3, a phase difference calculation circuit 5, a clock reproduction circuit 7, a data reproduction circuit 8, a reproduction clock signal output terminal 9, and a reproduction data output. It is composed of the terminal 10.

The input terminal 1 is a modulated wave (carrier wave) signal (eg, 1) modulated by the π / 4 shift QPSK system.
0, 7 MHz). The oscillator 2 is asynchronous with the modulation signal input to the input terminal 1 and generates electrical vibrations having substantially the same frequency.

FIG. 21 shows a block diagram of a conventional instantaneous phase detection circuit 3. The instantaneous phase detection circuit 3 includes an exclusive OR (exclusive OR circuit, hereinafter abbreviated as EX-OR) circuit 171, a D-type flip-flop (hereinafter,
DFF) 172, analog low-pass filter (hereinafter, LPF) 173, analog / digital converter (hereinafter, A / D converter) 1
74 and a polarity switching circuit 175.

Next, the instantaneous phase detection circuit 3 will be described with reference to FIG.
Shows the operation of. FIG. 22a shows an EX-OR circuit 171 and L
The phase detection characteristic processed by PF173 is shown. Here, the phase detection characteristics are 0 to π, 2π to 3π, and 4π to 5π, and the phase detection characteristics are sloping to the right and π to 2π, 3π to 4π, and 5π to 6π. FIG. 22b shows the phase detection characteristic of the DFF circuit 122. Where 0 to π, 2π
-1 to 3π, 4π to 5π, 1, π to 2π, 3π to 4
It has a phase detection characteristic of 0 in the period of π, 5π to 6π.

The output from the DFF circuit 172 is 1
In the case of, the output of FIG. 22a is output as it is. If the output from the DFF circuit 172 is 0,
The sign of the output of 2a is inverted and output. Then, FIG.
As shown in c, over a period of 2π from π to 3π,
The phase of a straight line was detected.

As shown in FIG. 23, the clock regeneration circuit 7 includes a clock regeneration signal generation circuit 71 and a digital phase locked loop (hereinafter abbreviated as DPLL) 7.
2 and. Here, the clock reproduction signal generation circuit 71 is configured to detect the magnitude comparator 711.
And a level setting circuit 712.

FIG. 24 shows the relationship between the conventional clock reproduction signal and the eye pattern. The eye pattern is the phase difference signal 6
In the case of describing all possible patterns,
A figure obtained from the locus of the phase difference signal 6. Here, the open eye pattern means that the phase difference signal 6 and the figure surrounded by the phase difference signal 6 are in the shape of human eyes. The closed eye pattern means a state in which the area of the figure surrounded by the phase difference signal 6 is small.

[0011]

However, in the conventional instantaneous phase detection circuit 3, the DFF circuit 172 determines the phase. The phase determination by the DFF circuit 172 is
Only at the rising edge of the signal input to the clock terminal. Therefore, when the frequency of the input modulated wave is low, that is, when the frequency of the oscillator 2 is low (for example, 1.2
In the case of using the frequency of MHz), the polarity determination interval becomes wider, which does not match the phase determination of FIG. 22a. Therefore,
In the vicinity of π, 2π, ..., Nπ (n is an integer), the phase detection becomes discontinuous.

Further, the conventional clock recovery signal generating circuit 71 is accompanied by jitter ± δ, as shown in FIG. 24b. Therefore, when the reproduction clock signal reproduced by the DPLL 72 differs from the phase of the phase difference signal 6 by 180 °, a deadlock state occurs, and there is a problem that reproduction cannot be performed properly. Here, the jitter is
The fluctuation of the phase difference signal 6 with respect to the clock signal.

In FIG. 24a, if the detection level is set to level 2 (phase difference is π / 4) during the preamble period and the detection level is set to level 1 (phase difference is 0) after the preamble period ends, the jitter is , Becomes almost 0. However, with this method, it is necessary to determine from the data body whether the currently received data is the preamble or the UW. However, it is quite difficult to determine the data type, a circuit such as an external microprocessor is required, and it is impossible to realize with a simple circuit configuration. The external microprocessor is busy implementing other processing functions, and in practice, it is difficult to perform data type classification processing. As a result, it is difficult to apply the method of switching the setting level according to the data type described above.

It is an object of the present invention to provide an instantaneous phase detection circuit which prevents a phase discontinuity and causes no trouble even if the frequency of an input modulated wave becomes low. Furthermore, the analog LPF1 that was required in the past
It is an object of the present invention to provide an instantaneous phase detection circuit that is composed of digital circuits and that eliminates 73 and the A / D converter 174.

Further, the clock recovery signal generating circuit of the present invention generates the clock recovery signal which can be properly reproduced when the DPLL pulls in the clock signal and after the pulling in of the clock signal. It is intended to provide a circuit.

[0016]

In order to solve the above-mentioned problems, a clock recovery signal generating circuit of the present invention inputs a phase difference signal and determines the timing at which the phase difference signal crosses a detection axis having a predetermined value. A plurality of detection axis crossing detection means having different detection axis values to be detected and the detection timing by the plurality of detection axis crossing detection means are described in advance.
Determine which of the multiple detection conditions that are stored
And estimates the change in trajectory of the phase difference signal based on the filled detection condition, the locus classifying means for outputting a timing adjustment signal according to the estimation result, either test Dejiku that the timing adjustment signal points out the detection timing by the cross detecting means, and a timing control means for generating a clock recovery signal corrected by the time timing adjustment signal instructs.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of an instantaneous phase detection circuit of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a detailed configuration of the instantaneous phase detection circuit 3A of the present invention. The instantaneous phase detection circuit 3A includes a 1 / n frequency divider circuit 2
1, EX-OR circuits 31 and 32, and π / 2 phase circuit 3
3, the moving average filter circuits 34 and 35, the π / 2 phase circuit 33, the moving average filter circuits 34 and 35, and the logic circuit 36.

The moving average filter circuit 34 comprises an N-stage shift register 341, a comparison circuit 342, and an up / down counter 343. Similarly, the moving average filter circuit 35 includes an N-stage shift register 351, a comparison circuit 352, and an up / down counter 353.

The carrier S2 output from the oscillator 2 is input to the 1 / n frequency dividing circuit 21. 1 / n frequency divider 2
1 is a circuit that divides the carrier S2 into a frequency of 1 / n. Here, the frequency of 1 / n is substantially the same as the frequency of the modulated wave signal S1 input from the input terminal 1. Then, the 1 / n frequency dividing circuit 21 outputs the signal S21 frequency-divided to the frequency of 1 / n to the EX-OR circuit 31 and π / 2.
It outputs to the phase circuit 33.

To the π / 2 phase circuit 33, the signal S21 divided into a frequency of 1 / n is input. The π / 2 phase circuit 33 delays the phase of the input signal S21 by π / 2 to phase it. Then, the π / 2 phase circuit 33
The signal S33 whose phase is delayed by only is output to the EX-OR circuit 32.

To the EX-OR circuits 31 and 32, the modulated wave signal S1 and the signal S21 whose frequency is 1 / n are input. Next, the EX-OR circuit 31 receives the modulated wave signal S1 and the signal S2 whose frequency is 1 / n.
An exclusive OR operation of 1 is performed. Then, the EX-OR circuit 31 outputs the operation result S31 of the exclusive OR operation to the moving average filter circuit 34.

The EX-OR circuit 32 includes a modulated wave signal S1.
And the signal S33 whose phase is delayed by π / 2 are input. Next, the EX-OR circuit 32 performs an exclusive OR operation of the input modulated wave signal S1 and the signal S33 whose phase is delayed by π / 2. Then, the EX-OR circuit 32 is
The operation result S32 of the exclusive OR operation is output to the moving average filter circuit 35.

The moving average filter circuit 34 comprises an N-stage shift register 341, a comparison circuit 342, and an up / down counter 343. Here, N is a natural number. The calculation result S31 and the carrier S2 are input to the N-stage shift register 341. here,
The carrier S2 in this case is the moving average filter circuit 34.
Used as a master clock to drive the.
Then, the N-stage shift register 341 is the first stage 341.
The comparison circuit 342 compares the contents of A and the contents of the Nth stage 341B.
Output to. The output to the comparison circuit 342 is performed according to the timing of the carrier S2 as the master clock.

The comparison circuit 342 includes carriers S2 and N.
The contents of the first stage 341A of the stage shift register 341,
The contents of the Nth stage 341B are input. Here, the carrier S2 in this case is also used as the master clock. After the following calculation is completed, the comparison circuit 342 outputs the calculation result S342 to the up / down counter 343.

The arithmetic processing of the comparison circuit 342 will be described below.
The arithmetic processing of the comparison circuit 342 is roughly divided into the following three (see FIG. 2). (1) When the content of the first stage 341A of the input N-stage shift register 341 is 1 and the content of the N-th stage 341B is 0, the comparison circuit 342 increments the up / down counter 343 by +1. (2) When the content of the first stage 341A of the input N-stage shift register 341 is 0 and the content of the N-th stage 341B is 1, the comparison circuit 342 causes the up / down counter 343 to count down by -1. (3) When the contents of the first stage 341A and the contents of the Nth stage 341B of the input N-stage shift register 341 are equal (the contents of the first stage 341A are 0 and the contents of the Nth stage 341B are 0, or The contents of the first stage 341A is 1, and the contents of the first stage 341B are 341B.
1), the comparison circuit 342 does not change the content of the up / down counter 343.

When the comparison circuit 342 performs the above-described arithmetic processing for one timing of the master clock, the number of "1" s from the second stage to the Nth stage of the N-stage shift register 341 is stored in the up-down counter 343. expressed. That is, the contents of the up-down counter 343 are the contents of the EX-OR circuit 3
The output result of 1 is the result of processing by the moving average filter that performs time averaging of T = (N-1) / fc. Here, N is the number of stages of the shift register 341, and fc is the frequency of the oscillator 2.

The up / down counter 343 has a phase detection characteristic (value counted by the instruction of the comparison circuit 342).
The S34 is output to the logic circuit 36. Here, the moving average filter circuit 34 is, for example, Japanese Patent Publication No. 1-38244.
It is disclosed in the publication.

The moving average filter circuit 35 has the same structure as the moving average filter circuit 34. The N-stage shift register 351 stores the calculation result S32 and the carrier S2.
And are entered. Here, the carrier S2 in this case is
It is used as a master clock for driving the moving average filter circuit 35. The N-th stage shift register 351 has the contents of the first stage 351A and the N-th stage 351B.
And the contents of the above are output to the comparison circuit 352. This comparison circuit 3
The output to 52 is carrier S2 as a master clock.
It is performed according to the timing of.

The comparison circuit 352 includes carriers S2 and N.
The contents of the first stage 351A of the stage shift register 351;
The contents of the Nth stage 351B are input. Here, the carrier S2 in this case is also used as the master clock. The comparison circuit 352 then outputs the calculation result S35.
2 is output to the up / down counter 353. The operation of the comparison circuit 352 is similar to that of the comparison circuit 342. The up-down counter 353 has a phase detection characteristic (value counted by the instruction of the comparison circuit 352) S.
35 is output to the logic circuit 36.

The logic circuit 36 has a phase detection characteristic S34.
And the phase detection characteristic S35 are input. Then, the logic circuit 36, based on the input phase detection characteristic S35,
If the input phase detection characteristic S35 is negative, the logic circuit 3
Reference numeral 6 inverts the sign of the input phase detection characteristic S34 to output it. In addition, the input phase detection characteristic S35
Is positive, the logic circuit 36 receives the input phase detection characteristic S
34 is output as it is.

Next, the operation of the instantaneous phase detection circuit of the present invention will be described with reference to FIG. FIG. 3A is a graph showing the phase detection characteristic S34 obtained from the moving average filter circuit 34. In FIG. 3a, 0 to π, 2π to 3π, 4π to 5
In the section of π, the up / down counter 343 changes from 0 to N−.
It is a straight line with a slope that rises to the right, indicating that it has increased to 1. Also, π to 2π, 3π to 4π, 5π to 6π
In the section of, the up-down counter 343 is 0 from N-1 to 0.
It is a straight line with a downward sloping slope, which indicates that Here, the horizontal axis in the figure is the phase difference between the signal S21 divided into the frequency of 1 / n and the modulated wave signal S1. Further, the vertical axis in the figure indicates the up / down counter 343.
Is the content of.

FIG. 3b is a graph showing the phase detection characteristic S35 obtained from the moving average filter circuit 35. Here, the phase detection characteristic S35 of FIG. 3b is delayed in phase by π / 2 from the phase detection characteristic S34 of FIG. 3a. This phase delay is due to the π / 2 phase circuit 33. Figure 3
In b, the section from 0 to π / 2 is a straight line having an upward slope, which indicates that the up / down counter 353 is increasing from N / 2 to N−1. (3π / 2) ~
The sections (5π / 2) and (7π / 2) to (9π / 2) are straight lines having a rising slope indicating that the up / down counter 353 is increasing from 0 to N−1.
The up / down counter 3 is in the section from (11π / 2) to 6π.
It is a straight line having an upward slope, which shows that 53 increases from 0 to N / 2. Also, π / 2 to (3π /
2), (5π / 2) to (7π / 2), (9π / 2) to
The section of (11π / 2) is a straight line having a downward sloping slope, which indicates that the up / down counter 353 is decreasing from N−1 to 0. Here, the horizontal axis in the figure is 1 / n
This is the phase difference between the signal S21 divided into the frequency of and the modulated wave signal S1. Further, the vertical axis in the figure represents the contents of the up / down counter 353.

The logic circuit 36 includes the up / down counter 3
0 to π, 2π to 3 based on N / 2 of the contents of 53
The interval of π, 4π to 5π is a positive interval, and π to 2π, 3π to
The section of 4π, 5π to 6π is a negative section. Then, the logic circuit 36 outputs the phase detection characteristic S34 of FIG. 3A as it is in the section determined to be the positive section in FIG. 3B.
Further, the logic circuit 36 inverts the sign of the phase detection characteristic S34 of FIG. 3a and outputs it in the section determined to be the negative section in FIG. 3b. Then, a graph as shown in FIG. 3c is obtained. In FIG. 3c, the section from 0 to π is a straight line having an upward slope, which indicates that the phase from 0 to π is increasing. The interval from π to 3π and 3π to 5π is −π to π.
It is a straight line with a rising slope that indicates that the phase is increasing up to. In addition, the section of 5π to 6π is a straight line having a rising slope indicating that the phase increases from −π to 0.

As described above, the instantaneous phase detection circuit of the present invention converts the digital phase modulated wave into two EX-OR circuits,
A moving average filter circuit and a logic circuit are used to delay one phase from the other phase by π / 2 for processing. Therefore, the instantaneous phase detection circuit of the present invention is less likely to cause discontinuity in phase detection even when the input modulated wave has a low frequency such as 1 or 2 MHz. Therefore, the instantaneous phase detection circuit of the present invention can accurately detect the phase.

The phase delay is not limited to π / 2, and the present invention can be implemented even when the phase delay is 0, π / 4, or the like. In this case, the configuration of the logic circuit 36 may be changed appropriately according to the delay of each phase. Further, as in the present invention, by configuring the instantaneous phase detection circuit by using the moving average filter circuit, the instantaneous phase detection circuit can be digitized, suitable for IC, and the cost can be reduced. Therefore, it is possible to reduce the size and weight of the device using the instantaneous phase detection circuit of the present invention.

Next, a first embodiment of the clock recovery signal generating circuit of the present invention will be described in detail with reference to the drawings. Here, FIG. 4 is a block diagram showing a detailed configuration of the first embodiment. The clock regeneration circuit 7A is a clock regeneration signal generation circuit 7
1A and a DPLL (Digital Phase Locked Loop) circuit 72. The clock reproduction signal generation circuit 71A is composed of the magnitude comparator 7
01, 703, level setting circuits 702, 704, a locus classification circuit 710, and a timing control circuit 707. The trajectory classification circuit 710 is composed of a timer circuit 705 and a determination circuit 706. Here, the magnitude comparator 701 and the level setting circuit 702 are provided correspondingly, and similarly, the magnitude comparator 703 and the level setting circuit 704 are also provided correspondingly.

The clock recovery signal generation circuit 71 is described below.
The configuration of A will be described. Magnitude comparator 70
Reference numerals 1 and 703 are a kind of comparator of a digital circuit.
The magnitude comparators 701 and 703 are provided in the level setting circuits 702 to which the input phase difference signal 6 corresponds.
This circuit generates an instantaneous pulse when the detection level value (detection axis) preset by 704 becomes equal.

The level setting circuits 702 and 704 set the detection level value (detection axis) and output the detection level value to the magnitude comparators 701 and 703. The phase difference signal 6 and the detection level value S702 output from the level setting circuit 702 are input to the magnitude comparator 701. The magnitude comparator 701 receives the input phase difference signal 6 and the input detection level value S7.
Judge whether 02 is equal to or not. The magnitude comparator 701 generates the pulse S701 only when it determines that the input phase difference signal 6 and the input detection level value S702 are equal (hereinafter, the pulse S701 generated by the magnitude comparator 701 is level 1 crossed). Pulse S701 is abbreviated). When the magnitude comparator 701 generates the level 1 cross pulse S701, the magnitude comparator 701 outputs the level 1 cross pulse S701.
The cross pulse S701 is output to the timing control circuit 707 and the trajectory classification circuit 710. Here, the level setting circuit 70
2 sets the level 1 corresponding to the phase difference 0 as the detection level value S702 (see FIGS. 6a and 7 described later).

Similarly, the magnitude comparator 70
The phase difference signal 6 and the detection level value S704 output from the level setting circuit 704 are input to 3. The magnitude comparator 703 receives the input phase difference signal 6
And the input detection level value S704 are equal to each other. The magnitude comparator 703 generates the pulse S703 only when it determines that the input phase difference signal 6 and the input detection level value S704 are equal (hereinafter, the pulse S703 generated by the magnitude comparator 703 is level 0 crossed). Abbreviated as pulse S703). Then, when the magnitude comparator 703 generates the level 0 cross pulse S703, the magnitude comparator 703 outputs the level 0 cross pulse S703 to the timing control circuit 707 and the trajectory classification circuit 710. Here, the level setting circuit 704 determines that the detection level value
As S704, the level 0 corresponding to the phase difference π / 2 is set (see FIGS. 6a and 7 described later).

The locus classification circuit 710 includes a timer circuit 705.
And a determination circuit 706. The locus classification circuit 710 uses the level 1 cross pulse S701 and the level 0 cross pulse S703 to detect the phase difference signal 6
The change locus of is determined and classified. Then, the trajectory classification circuit 71
0 is the timing adjustment signal S70 according to the determined classification.
6 is output to the timing control circuit 707.

The level 1 cross pulse S 701 and the level 0 cross pulse S 703 are input to the timer circuit 705. The timer circuit 705 uses the level 1 cross pulse S
When either one of 701 and level 0 cross pulse S703 is input, the timer starts counting. Then, the timer circuit 705 causes the level 1 cross pulse S7 to be output within a certain time after the timer starts counting.
When either 01 or level 0 cross pulse S703 is input, the timer count is ended. Here, the same pulse may be used to start and stop the counting of the timer. For example, level 0 cross pulse S
This is the case where the timer starts counting by the input of 703 and ends the counting by the input of the level 0 cross pulse S703. Further, there is a case where the pulse for ending the counting of the timer is not input within a certain time after the pulse for starting the counting of the timer is input. Therefore, the count of the timer of the timer circuit 705 is configured to automatically end and be reset after the elapse of a certain time. Then, the timer circuit 705
Outputs count information (measured time) S705 to the determination circuit 706 and resets the timer.

Here, when the first pulse input after the level 0 cross pulse S701 is input is the level 0 cross pulse S701, the timer circuit 705 resets the timer by the level 0 cross pulse S701 and measures the time. Start over.

If the first pulse input after the level 1 cross pulse S703 is the level 1 cross pulse S703, the timer circuit 705 resets the timer by the level 1 cross pulse S703,
Start timing again from the beginning.

The judgment circuit 706 stores count information S70.
5 is input. The determination circuit 706 determines whether or not the input count information S705 satisfies one of the detection conditions (see FIG. 6a described later) stored in the determination circuit 706 in advance. Then, the determination circuit 706
Is a timing adjustment signal S706 corresponding to the detection condition determined to satisfy the input count information S705.
Is output to the timing control circuit 707.

The timing control circuit 707 has a level 1
Cross pulse S701 and level 0 cross pulse S70
3 and the timing adjustment signal S706 are input. The timing control circuit 707 responds to the input timing adjustment signal S706 (see FIG. 6a, which will be described later), and the DPLL.
The clock recovery signal S707 is output to the circuit 72.

The clock recovery signal generation circuit 71 is described below.
The operation of each circuit in A will be described, and the functions of the timer circuit 705, the determination circuit 706, and the timing control circuit 707 will be clarified through this operation description. In the first embodiment, two detection level values of level 0 and level 1 are set in the level setting circuit. Then, each magnitude comparator generates a pulse at the moment when the phase difference signal 6 becomes equal to this detection level value. The locus classification circuit 710 estimates what kind of locus the phase difference signal 6 follows, depending on the input state of the generated pulse.
Then, the timing control circuit 707 selects the time until the clock reproduction signal S707 is output based on this trajectory estimation, and the timing control circuit 7 according to this selection.
07 outputs the clock reproduction signal S707.

Here, the two detection level values are the level 1 detection level value S702 corresponding to the phase difference 0 and the level 0 detection level value S704 corresponding to the phase difference π / 2.
Is. The detection level value S702 is the level setting circuit 70.
It is set to 2. Further, the detection level value S704 is
It is set in the level setting circuit 704.

The magnitude comparator 701 includes
The phase difference signal 6 and the detection level value S702 are input. The magnitude comparator 701 determines whether the phase difference signal 6 and the detection level value S702 are equal. When it is determined that the phase difference signal 6 and the detection level value S702 are equal, the magnitude comparator 7
01 generates a level 1 cross pulse S701. Then, the magnitude comparator 701 outputs the generated level 1 cross pulse S701 to the timing control circuit 7
07 and the trajectory classification circuit 710. When it is determined that the phase difference signal 6 is not equal to the detection level value S702, the magnitude comparator 701 does not generate the level 1 cross pulse S701.

The magnitude comparator 703 has
The phase difference signal 6 and the detection level value S704 are input. The magnitude comparator 703 determines whether the phase difference signal 6 is equal to the detection level value S704. When it is determined that the phase difference signal 6 and the detection level value S704 are equal, the magnitude comparator 7
03 generates a level 0 cross pulse S703. Then, the magnitude comparator 703 outputs the generated level 0 cross pulse S703 to the timing control circuit 7
07 and the trajectory classification circuit 710. If it is determined that the phase difference signal 6 is not equal to the detection level value S704, the magnitude comparator 703 does not generate the level 0 cross pulse S703.

Data used in the present invention will be described with reference to FIG. The data is composed of a preamble part, a UW part, and a data body part. The preamble pattern is input to the preamble part. For example,
For example, "10111001 ... 1001", "10
01 ”is repeatedly input. A code indicating the beginning of data is input to the UW section. Data to be transmitted is input to the data body.

FIGS. 6a and 7a are diagrams showing the operation of the trajectory classification circuit 710 and the timing control circuit 707 of the first embodiment. The time T is a time corresponding to one symbol of data (a time corresponding to 360 °). The predetermined time Td is
Time for determining whether the phase difference signal 6 is a pulse in the preamble period (for example, time corresponding to 150 °)
Is. The time t0 is a time (for example, a time corresponding to 60 °) for adjusting the timing at which the timing control circuit 707 outputs the clock reproduction signal S707.

Next, the method of estimating the trajectory of the phase difference signal 6 will be described with reference to FIG. 6a. FIG. 6 a shows a trajectory classification circuit 710.
7 is a diagram showing the operation of the timer circuit 705 and the determination circuit 706 of FIG.

The detection number 1 is obtained only when the following conditions 1 to 5 are all satisfied in order. 1, the timer circuit 705 has a level 0 cross pulse S7
03 is input. 2. The timer circuit 705 starts counting (clocking). 3. The timer circuit 705 has a level 1 cross pulse S7.
01 is input. 4. The timer circuit 705 finishes counting (clocking). 5, the determination circuit 706, the count information (clock value) S70
5 is compared with a preset predetermined time Td, and it is determined that it is shorter than the predetermined time Td.

Here, when the detection number 1 is obtained, the determination circuit 706 outputs the timing adjustment signal S706 to the timing control circuit 707. Here, the timing adjustment signal S706 is output from the time when the level 0 cross pulse S703 is input to the locus classification circuit 710 at time {t.
0 + T / 2} has elapsed, the timing control circuit 7
07 sends the clock reproduction signal S707 to the DPLL circuit 72.
To output to.

The detection number 2 is obtained only when all the following conditions 1 to 5 are satisfied in order. 1. The timer circuit 705 has a level 1 cross pulse S7.
01 is input. 2. The timer circuit 705 starts counting (clocking). 3. The timer circuit 705 has a level 0 cross pulse S7.
03 is input. 4. The timer circuit 705 finishes counting (clocking). 5, the determination circuit 706, the count information (clock value) S70
5 is compared with a preset predetermined time Td, and it is determined that it is shorter than the predetermined time Td.

Here, when the detection number 2 is obtained, the determination circuit 706 outputs the timing adjustment signal S706 to the timing control circuit 707. Here, the timing adjustment signal S706 is output from the time when the level 1 cross pulse S701 is input to the locus classification circuit 710 at a time {t.
0 + T / 2} has elapsed, the timing control circuit 7
07 sends the clock reproduction signal S707 to the DPLL circuit 72.
To output to.

The detection number 3 is obtained only when the following conditions 1 to 3 are all satisfied in order. 1. The timer circuit 705 has a level 1 cross pulse S7.
01 is input. 2. The timer circuit 705 starts counting (clocking). 3. The level 0 cross pulse S703 is not input to the timer circuit 705 within the predetermined time Td.

Here, when the detection number 3 is obtained, the determination circuit 706 outputs the timing adjustment signal S706 to the timing control circuit 707. Here, the timing adjustment signal S 706 is output from the time when the level 1 cross pulse S 701 is input to the trajectory classification circuit 710 at a time {T.
/ 2} has elapsed, the timing control circuit 707 instructs the clock recovery signal S707 to be output to the DPLL circuit 72.

FIG. 7 is an explanatory diagram of the trajectory classification (trajectory detection) of the phase difference signal, and an explanatory diagram of the output timing adjustment of the clock reproduction pulse shown in FIG. The locus indicated by the bold line in FIG. 7a is the same as that shown in FIG.
It is a locus of the phase difference signal 6 in the preamble period of "100 ... 1001". In the case of the π / 4 shift QPSK signal, the phase difference value of the phase difference signal 6 does not represent the data value as it is, but the locus of the phase difference signal 6 represents the data value. Here, the vertical axis is π, π / 2, π /
4, 0, -π / 2, and -π represent phase difference values. Figure 7a
In, the time points a and e indicate the intersections of the phase difference signal 6 and the phase difference 0 during the preamble period.

First, the case where the detection number 1 is obtained will be described with reference to FIG. 7a. Phase difference signal 6 in preamble period
Intersects the detection level value at time a. And
The timer circuit 705 of the locus classification circuit 710 includes a level 0 cross pulse S from the magnitude comparator 703.
703 is input, and the timer circuit 705 starts counting. Next, the phase difference signal 6 in the preamble period crosses the detection level value at the time point b. Then, the level 1 cross pulse S701 is input from the magnitude comparator 701 to the timer circuit 705 within a predetermined time Td from the time point a, and the timer circuit 705 ends counting (time point b). Here, the determination circuit 705 determines that the count information S705 is shorter than the predetermined time Td.
The detection number 1 is obtained as described above. Then, the determination circuit 70
6 is a time point c when the time {t0 + T / 2} has passed from the time point a, and the clock recovery signal S707 is sent to the DPLL circuit 72.
Timing adjustment signal S706 instructing to output
To the timing control circuit 707 (see FIG. 7b).

Next, the case where the detection number 2 is obtained will be described with reference to FIG. 7a. Phase difference signal 6 in preamble period
Intersects the detection level value at time d. And
The timer circuit 705 of the locus classification circuit 710 includes a level 1 cross pulse S from the magnitude comparator 701.
701 is input, and the timer circuit 705 starts counting. Next, the phase difference signal 6 in the preamble period crosses the detection level value at the time point e. Then, the level 0 cross pulse S703 is input from the magnitude comparator 703 to the timer circuit 705 within a predetermined time Td from the time point d, and the timer circuit 705 ends counting (time point e). Here, the determination circuit 705 determines that the count information S705 is shorter than the predetermined time Td.
Detection number 2 is thus obtained.

Then, the judgment circuit 706 outputs the timing adjustment signal S706 instructing the DPLL circuit 72 to output the clock reproduction signal S707 at the time point f when the time {t0 + T / 2} has elapsed from the time point d. Output to 707 (see FIG. 7b).

Similarly, for the phase difference signal 6 in the preamble period, the trajectory classification circuit 710 applies the timing adjustment of detection number 1 and detection number 2. Then, from the timing control circuit 707, as shown in FIG.
The clock reproduction signal S707 is output at the timing when the eye pattern is most open (time points c and f). As a result, the DPLL 72 produces a clock signal of the correct phase synchronized with this pulse, as shown in FIG. 7c.

Here, in FIG. 24b, the jitter δ is set to 0.
And The clock recovery signal of FIG.
4b clock reproduction signal is compared. Then, in the preamble period, the phase of the clock reproduction signal S707 given to the DPLL 72 differs by T / 2. However, the phase determination in the DPLL 72 differs by T / 2. However, the DPLL 72 can easily cope with such a difference by accelerating the phase determination in the DPLL 72 by T / 2.

When the preamble period ends and the UW or the data body period starts, the bit pattern cannot be fixed.
Therefore, the clock recovery signal generation circuit 71A has 1
The phase difference signal 6 that takes one of all six trajectories is input. The detection number 1 and the detection number 2 described above take into consideration the trajectory in the preamble period.
However, even during UW and data periods, these detection numbers 1
And, the locus of the detection number 2 is taken. The locus relating to the detection number 3 corresponds to the period of the UW or the data body, and there are eight loci on which the timing adjustment by the detection number 3 is executed, as will be described later.

8, FIG. 9, FIG. 10, FIG. 11 and FIG.
The relation between all 16 loci and the output timing adjustment of the clock reproduction pulse will be described. Hereinafter, the relationship between the locus of the phase difference signal 6 and the timing adjustment will be described with reference to FIGS. 8, 9, 10, 11, and 12. For convenience of explanation, all 16 trajectories are shown divided into 5 figures.

FIG. 8 shows two types of trajectory patterns 8a-1 and 8a.
a-2 is indicated by a thick line. First, the trajectory pattern 8a-1 will be described. Timer circuit 705 of trajectory classification circuit 710
Level 0 from the magnitude comparator 703.
The cross pulse S703 is input and counting is started (time point g). Next, the timer circuit 705, within a predetermined time Td from the time point g, the magnitude comparator 701.
Then, the level 1 cross pulse S701 is input from and the counting is completed (time h). The determination circuit 705 determines that the count information S705 is shorter than the predetermined time Td. With the above, the detection number 1 (see FIG. 6a) is obtained. Then, the determination circuit 706 determines that the time {t0 + T /
When 2} has elapsed, the timing adjustment signal S706 is output to the timing control circuit 707. In the same way as described for the preamble period, the trajectory classification circuit 7
In response to the timing adjustment by 10, the timing control circuit 707 generates the clock reproduction signal S707 at the timing when the eye pattern opens the eyes.

Next, the locus pattern 8a-2 will be described. The timer circuit 705 of the locus classification circuit 710 receives the level 1 cross pulse S701 from the magnitude comparator 701 and starts counting (time i).
Next, the timer circuit 705 outputs the level 0 from the magnitude comparator 703 within a predetermined time Td from the time point i.
The cross pulse S703 is input and the counting is finished (time j). The determination circuit 705 uses the count information S705.
Is shorter than the predetermined time Td. With the above, the detection number 2 (see FIG. 6a) is obtained.

Then, the judgment circuit 706 outputs the timing adjustment signal S706 to the timing control circuit 707 when the time {t0 + T / 2} has elapsed from the time point i. As described for the preamble period,
In response to the timing adjustment by the trajectory classification circuit 710, the timing control circuit 707 generates the clock reproduction signal S707 at the timing when the eye pattern opens its eyes most.

FIG. 9 shows six types of trajectory patterns 8b-1, 8b.
B-2, 8b-3, 8b-4, 8b-5, 8b-6 are indicated by thick lines. Neither locus pattern crosses any of the level 0 and level 1 detection levels. in this case,
It does not correspond to any of the detection conditions of detection numbers 1 to 3 in FIG. Therefore, the timing adjustment by the trajectory classification circuit 710 is not executed for any trajectory pattern.
Then, the timing control circuit 707 does not generate the clock reproduction signal S707.

FIG. 10 shows two types of trajectory patterns 8c-1,
8c-2 is indicated by a thick line. Two locus patterns 8c-1, 8
c-2 will be described. The timer circuit 705 of the locus classification circuit 710 receives the level 0 cross pulse S703 from the magnitude comparator 703 and starts counting (time k). However, two locus patterns 8c-
Both 1 and 8c-2. Within a predetermined time Td from the time point k, either the detection level value S7 of level 0 or level 1 is detected.
02 or S704 does not cross. Therefore, FIG.
Does not correspond to any of the detection conditions of detection numbers 1 to 3.
Therefore, the timing adjustment by the trajectory classification circuit 710 is not executed for the two trajectory patterns 8c-1 and 8c-2. Then, the timing control circuit 707 does not generate the clock reproduction signal S707.

FIG. 11 shows four types of trajectory patterns 8d-1,
8d-2, 8d-3, and 8d-4 are indicated by thick lines. The four trajectory patterns 8d-1, 8d-2, 8d-3, 8d-4 will be described. Timer circuit 705 of trajectory classification circuit 710
Receives the level 1 cross pulse S701 from the magnitude comparator 701 and starts counting (time points 1, m, n). However, the four trajectory patterns 8d-
1, 8d-2, 8d-3, and 8d-4 are all detection level values S702 or S704 of level 0 or level 1 within a predetermined time Td from each time point (l, m, n).
Do not cross with. Then, in this case, the detection condition of the detection number 3 in FIG. Therefore, the timing control circuit 707 receives the timing adjustment by the trajectory classification circuit 710. Then, the timing control circuit 707
The clock recovery signal S707 is generated at a timing when a predetermined time T / 2 has elapsed from the time point (1, m, n) at which the signals cross.

Here, the timing control circuit 707 has four locus patterns 8d-1, 8d-2, shown in FIG.
For the two locus patterns 8d-1 and 8d-2 of 8d-3 and 8d-4 having a gentle inclination, the clock reproduction signal S707 is generated at the timing when the eye pattern opens the eyes most. In addition, the timing control circuit 707, for the other two trajectory patterns 8d-3 and 8d-4 having a steep inclination,
The clock reproduction signal S deviated by a predetermined amount (jitter ± δ1) from the timing when the eye pattern opens the eyes most.
707 is generated.

FIG. 12 shows two types of trajectory patterns 8e-1 and 8e.
e-2 is shown by a thick line. Neither trajectory pattern is a signal in the preamble period. First, the trajectory pattern 8e-1
Will be described. Timer circuit 7 of trajectory classification circuit 710
05 receives the level 0 cross pulse S703 from the magnitude comparator 703 and starts counting (time point o). Next, the timer circuit 705, within a predetermined time Td from the time point o, measures the magnitude comparator 70.
The level 1 cross pulse S701 is input from 1 and the counting is completed (time point p). The determination circuit 705 determines that the count information S705 is shorter than the predetermined time Td. With the above, the detection number 1 (see FIG. 6a) is obtained. Then, the determination circuit 706 determines that the time {t0 + T /
When 2} has elapsed, the timing adjustment signal S706 is output to the timing control circuit 707.

Next, the locus pattern 8e-2 will be described. The timer circuit 705 of the locus classification circuit 710 receives the level 1 cross pulse S701 from the magnitude comparator 701 and starts counting (time point p).
Next, the timer circuit 705 outputs the level 0 from the magnitude comparator 703 within a predetermined time Td from the time point p.
The cross pulse S703 is input and the counting is completed (time point q). The determination circuit 705 uses the count information S705.
Is shorter than the predetermined time Td. With the above, the detection number 2 (see FIG. 6a) is obtained.

Then, the judgment circuit 706 outputs the timing adjustment signal S706 to the timing control circuit 707 when the time {t0 + T / 2} has elapsed from the time point p. However, in each of the locus patterns, the rear cross occurs earlier or later than the locus pattern mainly occurring in the preamble period shown in FIG. 7A. Therefore, the generation timing of the clock reproduction pulse is deviated by a predetermined amount (jitter ± δ2) from the timing when the most desirable eye pattern opens.

As described above, in the clock reproduction signal generation circuit 71A of the first embodiment, when the pattern of the preamble period is received, 100% of the clock reproduction signal S707 having no jitter is taken out and the DPLL7 is outputted.
Can be given to 2. Further, the phase of the clock signal output from the DPLL 72 can be quickly pulled into the correct phase angle, and the correct phase angle can be stably maintained.

Further, even if the pattern of the preamble period has passed, the clock reproduction signal generation circuit 71A of the first embodiment.
In the above, the clock reproduction pulse can be taken out and given to the DPLL 72 with a probability of 1/2 (8 ways / 16 ways). Then, the clock regeneration signal generation circuit 71
A can be used for phase control of the clock signal output from the DPLL 72. 1/2 (4/8 patterns) for the clock recovery pulses extracted in this way
However, even if the DPLL 72 uses a clock reproduction pulse having such a jitter, the phase error between the reproduced clock signal and the input signal is sufficiently small in the preamble period. Therefore, it functions sufficiently to make the reproduced clock signal follow the input signal.

Therefore, the clock recovery signal generating circuit 71A described above detects the phase in the phase difference signal 6 by using the cross phase with respect to a plurality of detection levels (detection axes). The clock reproduction signal generation circuit 71A described above is adapted to generate a clock reproduction pulse having no jitter. Therefore, the clock reproduction signal generation circuit 71A can quickly and correctly synchronize the clock signal with the phase of the input signal during the preamble period. Further, the clock reproduction signal generation circuit 71A generates a clock reproduction signal S707 having no jitter. Therefore, the clock regeneration signal generation circuit 71A
It is possible to prevent the occurrence of a so-called deadlock state.
Further, the DPLL 72 can prevent the occurrence of the deadlock state. Further, the DPLL 72 does not necessarily need to have the structure provided with the structure for preventing the occurrence of the deadlock state.

Further, the clock recovery signal generating circuit 71A described above can generate the clock recovery signal S707 with a high probability even after the preamble period ends. The clock reproduction signal generation circuit 71A can continue to follow the clock reproduction signal S707. Therefore, the clock recovery signal generation circuit 71A can significantly reduce the risk of loss of synchronism. As a result, DPLL72
From this, it becomes possible to generate a good clock signal.

Further, the above-mentioned clock reproduction signal generation circuit 71A does not need to distinguish whether the input signal to the differential detection circuit is the preamble or another UW or data body. Further, the clock reproduction signal generation circuit 71A can minimize the increase in size of the clock reproduction signal generation circuit 71A, and does not burden the external microprocessor. As described above, the clock reproduction signal is generated.

Next, a second embodiment of the clock recovery signal generating circuit of the present invention will be described in detail with reference to the drawings. here,
FIG. 13 is a block diagram showing the detailed structure of the second embodiment. The clock reproduction circuit is composed of a clock reproduction signal generation circuit 71B and a DPLL circuit 91. The clock reproduction signal generation circuit 71B includes a magnitude comparator 701, 703 and a level setting circuit 7.
02, 704, a locus classification circuit 710A, a timing control circuit 707, and a phase difference determination circuit 93. The trajectory classification circuit 710A includes a timer circuit 705.
And a determination circuit 706 and a gate circuit 92. Here, the magnitude comparator 701
And the level setting circuit 702 are provided corresponding to each other. Similarly, the magnitude comparator 703 and the level setting circuit 70 are provided.
4 is also provided correspondingly, which is the same as the first embodiment.

The DPLL circuit 91 performs a low speed control mode in which the phase tracking is performed at a low speed and a high speed control mode in which the phase tracking is performed at a high speed according to the magnitude of the phase difference between the clock reproduction signal S707 and the generated clock signal. Apply what you switch. Here, the DPLL 91 is, for example,
It is disclosed in Japanese Patent Laid-Open No. 61-265922.

Below, the clock recovery signal generation circuit 71
The configuration of B will be described. Magnitude comparator 70
1, 703 and the level setting circuits 702, 704 are
The configuration is the same as that used in the clock reproduction signal generation circuit 71A of the embodiment. Trajectory classification circuit 710A
Is composed of a timer circuit 705, a determination circuit 706, and a gate circuit 92. The gate circuit 92 receives the level 0 cross pulse S703 output from the magnitude comparator 703 and the mode signal S93 output from the phase difference determination circuit 93. Here, in the gate circuit 92, the mode signal S93 is used as a signal for controlling the output of the level 0 cross pulse S703. When the mode signal S93 indicates the high speed control mode, the gate circuit 92 outputs the level 0 cross pulse S703 to the timer circuit 705. Further, the gate circuit 92 does not pass the level 0 cross pulse S703 to the timer circuit 705 when the mode signal S93 indicates the low speed control mode. Here, the high-speed control mode is
This is the state of detection numbers 1 to 3 of the first embodiment (Fig. 6a,
(See FIG. 14). The low-speed control mode is the detection number 4
Is the state of. Here, the detection number 4 is the gate circuit 92.
Is the time {T / 2} from the time when the level 1 cross pulse S701 is input from the magnitude comparator 701.
Timing control signal 707
Is a state in which the clock reproduction signal S707 is output from (see FIG. 14).

The timer circuit 705 is inputted with the level 1 cross pulse S701 and the level 0 cross pulse S703. The determination circuit 706 has the same configuration as the determination circuit described in the first embodiment and operates similarly. The timing control circuit 707 has the same configuration as the timing control circuit described in the first embodiment and operates in the same manner. The timing control circuit 707 outputs the clock reproduction signal S707 to the DPLL circuit 91 and the phase difference determination circuit 93.

The phase difference determination circuit 93 receives the clock reproduction signal S707 and the clock signal S91. Then, the phase difference is determined using the input signal. Also in the clock recovery signal generating circuit 71B of the second embodiment, when the preamble period is received, the operation of detection number 1 or 2 in the high speed control mode is executed. Then, the clock reproduction signal generation circuit 71B can take out 100% of the clock reproduction pulse having no jitter and supply it to the DPLL circuit 91. As a result, the clock reproduction signal generation circuit 71B can quickly bring the phase of the clock signal S91 output from the DPLL circuit 91 to the correct phase angle.

In this way, when the clock signal S91 is pulled in to a desired phase angle (for example, within π / 4) during or after the preamble period, the mode is switched to the low speed control mode by the phase difference determination circuit 93. . Therefore, the trajectory classification circuit 710A executes the operation of the detection number 4 based only on the level 1 cross pulse, and the DPLL circuit 91 is also switched to the low speed control mode, so that the DPLL circuit 91 maintains its stabilized state. As described above, the control of the generation phase of the clock signal S91 is executed at a low speed.

Also according to the second embodiment, the phase in the phase difference signal 6 is detected by utilizing the cross phase with respect to a plurality of detection levels (detection axes), and the clock recovery signal S is detected.
707 is generated. Therefore, the clock recovery circuit is configured to use the clock signal S91 during the preamble period.
Can be quickly and correctly tuned to the phase of the input signal. Further, the clock recovery circuit can generate the clock recovery signal S707 with a high probability even after the preamble period ends and can continue the tracking, and the risk of loss of synchronization can be significantly reduced as compared with the conventional case. Also, the clock signal S9
After pulling 1 into the phase of the input signal, the phase is controlled at a low speed. Therefore, even if a pulse is output from the magnitude comparators 701 and 703 due to noise or the like, the stable phase of the clock signal S91 is ignored. Obtainable.

That is, according to the second embodiment, the first
More than the embodiment, it is possible to meet the contradictory requirements of rapid clock pull-in and stable clock recovery. In each of the above embodiments, the detection level (detection axis) for estimating the trajectory of the phase difference signal is shown as two, but the present invention is not limited to this, and three or more detection levels are used. It may be one that has been made. In this case, the number of loci classifications (control type of the timing control circuit 707) may be appropriately selected according to the number of detection levels. In each of the above embodiments, the pattern of the preamble period is "1001".
It is assumed that it is a repeating pattern of
The preamble pattern may be another one, and in this case, the trajectory classification and the output timing adjustment of the clock recovery pulse may be performed accordingly.

Next, a third embodiment of the clock recovery signal generating circuit of the present invention will be described in detail with reference to the drawings. here,
FIG. 15 is a block diagram showing the detailed structure of the third embodiment. The clock reproduction circuit is composed of a clock reproduction signal generation circuit 71C and a DPLL circuit 72.

The clock reproduction signal generation circuit 71C includes magnitude comparators 1101, 1103 and 110.
5, 1107 and level setting circuits 1102, 1104,
1106 and 1108 and pulse synthesizing circuits 1109 and 11
10, a trajectory classification circuit 710B, and a timing control circuit 7
And 07. Trajectory classification circuit 710B
Is composed of a timer circuit 1111 and a determination circuit 1112. Here, the magnitude comparator 1101 and the level setting circuit 1102, the magnitude comparator 1103 and the level setting circuit 1104, the magnitude comparator 1105 and the level setting circuit 110.
6. The magnitude comparator 1107 and the level setting circuit 1108 are provided corresponding to each other. DPL
The L circuit 72 has the same configuration as the circuit described in the first embodiment and operates in the same manner.

Below, the clock recovery signal generation circuit 71
The configuration and operation of C will be described. The phase difference signal 6 and the detection level value S1102 output from the level setting circuit 1102 are input to the magnitude comparator 1101. The magnitude comparator 1101 determines whether or not the input phase difference signal 6 changes in the π → −π direction.
Moreover, the input phase difference signal 6 is detected level value S1102.
And whether or not The magnitude comparator 1101 generates the pulse S1101 only when the input phase difference signal 6 satisfies the above condition. And
The magnitude comparator 1101 outputs the generated pulse S1101 to the pulse synthesis circuit 1109 and the trajectory classification circuit 7
It outputs to the determination circuit 1112 of 10B. Here, the level setting circuit 1102 sets the level 1 corresponding to the phase difference 0 as the detection level value S1102 (FIG. 17a).
reference). The detection level value S1102 in this case is
It is a value when the phase difference signal 6 changes from π to −π direction. That is, the magnitude comparator 110
1 is the pulse S11 when the phase difference signal 6 changes from π to −π direction and crosses the detection level value S1102.
01 (see FIG. 17b).

The phase difference signal 6 and the detection level value S1104 output from the level setting circuit 1104 are input to the magnitude comparator 1103. The magnitude comparator 1103 determines whether or not the input phase difference signal 6 changes in the −π → π direction and whether or not the input phase difference signal 6 is equal to the detection level value S1104. Magnitude comparator 110
3 generates the pulse S1103 only when the input phase difference signal 6 satisfies the above condition. Then, the magnitude comparator 1103 causes the generated pulse S
1103 is output to the pulse synthesis circuits 1109 and 1110. Here, the level setting circuit 1104 sets the level 1 corresponding to the phase difference 0 as the detection level value S1104 (see FIG. 17a). The detection level value S1104 in this case is a value when the phase difference signal 6 changes from −π to π direction. That is, in the magnitude comparator 1103, the phase difference signal 6 is −
When changing from π to π direction and crossing the detection level value S1104, a pulse S1103 is generated (FIG. 17c).
reference).

The phase difference signal 6 and the detection level value S1106 output from the level setting circuit 1106 are input to the magnitude comparator 1105. The magnitude comparator 1105 determines whether or not the input phase difference signal 6 changes in the π → −π direction and whether or not the input phase difference signal 6 is equal to the detection level value S1106. Magnitude comparator 110
5 generates the pulse S1105 only when the input phase difference signal 6 satisfies the above condition. Then, the magnitude comparator 1105 determines that the generated pulse S
1105 is output to the pulse synthesis circuit 1110. Here, the level setting circuit 1106 is configured to detect the detection level value S110.
As level 6, level 0 corresponding to the phase difference π / 2 is set (see FIG. 17a). The level setting circuit 110
The detection level value S1106 of 6 is a value when the phase difference signal 6 changes from π to −π direction. That is, the magnitude comparator 1105 determines that the phase difference signal 6
Changes from π to −π and crosses the detection level value S1106, a pulse S1105 is generated (FIG. 1).
7d).

The phase difference signal 6 and the detection level value S1108 output from the level setting circuit 1108 are input to the magnitude comparator 1107. The magnitude comparator 1107 determines whether or not the input phase difference signal 6 changes in the −π → π direction and whether or not the input phase difference signal 6 is equal to the detection level value S1108. Magnitude comparator 110
7 generates the pulse S1107 only when the input phase difference signal 6 satisfies the above condition. Then, the magnitude comparator 1107 determines that the generated pulse S
1107 is output to the determination circuit 1112 of the trajectory classification circuit 710B. Here, the level setting circuit 1108 sets the level 0 corresponding to the phase difference π / 2 as the detection level value S1108 (see FIG. 17a). The detection level value S1108 of the level setting circuit 1108 is a value when the phase difference signal 6 changes from −π to π direction. That is, the magnitude comparator 1107
Is a pulse S110 when the phase difference signal 6 changes from −π to π and crosses the detection level value S1108.
7 (see FIG. 17e).

The pulse synthesizing circuit 1109 has a pulse S1.
101 and the pulse S1103 are input. The pulse synthesizing circuit 1109 receives the input pulses S1101 and S110.
The logical sum of 3 is taken to obtain a composite value S1109 (FIG. 17f).
reference). The pulse synthesizing circuit 1109 then synthesizes the synthesized value S
1109 is output to the timing control circuit 707.

The pulse synthesizing circuit 1110 has a pulse S1
103 and the pulse S1105 are input. The pulse synthesis circuit 11110 receives the input pulses S1103 and S11.
The logical sum of 05 is taken to obtain a composite value S1110 (FIG. 17).
g)). Then, the pulse synthesis circuit 1110 outputs the synthesis value S1110 to the timing control circuit 707 and the timer circuit 1111 of the trajectory classification circuit 710B.

The locus classification circuit 710B includes a timer circuit 11
11 and a determination circuit 1112. FIG.
The operation of the trajectory classification circuit 710B will be described using. FIG. 18a shows the trajectory of the phase difference signal. Here, the phase difference signal in the preamble period is shown in, and two examples of the phase difference signal not in the preamble period are shown in. The composite value S1110 is input to the timer circuit 1111. When the combined value S1110 is input, the timer circuit 1111 resets and counts (clocks) the timer. Here, the timer circuit 1111 automatically stops after a certain period of time has elapsed after the start of counting (here, Td time). Then, the timer circuit 1111 outputs the count information S1111 (counted value) to the determination circuit 1112. The count information S1111 is information indicating after a lapse of the counted fixed time (here, Td time).

Here, first, an example of the above-mentioned operation using the phase difference signal in the preamble period will be shown. The timer circuit 1111 counts for Td time from the time points r and u, and outputs the H level to the determination circuit 1112 for Td time (see FIGS. 18b and 18c). Similarly, in the case of the phase difference signal which is not in the preamble period, counting is performed for the time Td from the time point w. When the phase difference signal is not in the preamble period, counting is performed for the time Td from the time point x. Then, the determination circuit 1112 only for Td time.
To the H level (see FIG. 18f, g, j, k).

The judgment circuit 1112 has an SE reset judgment unit (not shown). Here, the S-E reset determination unit is an abbreviation for the START-END reset determination unit. The S-E reset determination unit holds the state at the H level by inputting the composite value S1110, and outputs the pulse S1.
By inputting 101 or pulse S1107, the state is held at the L level. The determination circuit 1112 includes count information S1111, pulse S1101, and pulse S1.
107 is input. The determination circuit 1112 uses the input count information S1111, pulse S1101, and pulse S1101.
It is determined whether 1107 satisfies the detection conditions described in the first embodiment of the clock recovery signal generating circuit of the present invention (see FIG. 6b).

Here, with reference to FIG. 18, the determination circuit 111
The operation of No. 2 will be described. The counting of the Td time starts when the inclination of the pulse that crosses level 0 is negative and when the inclination of the pulse that crosses level 1 is positive. First, Figure 1
8b, c, d, and e, the case where the phase difference signal in the preamble period is input to the determination circuit 1112 will be described. When the composite value S1110 (time points d1 and d2) is input to the timer circuit 1111 and the timer starts counting, the S-E reset determination unit (not shown) holds the H level (time points r and u). And S-E not shown
The reset determination unit uses the pulse S1101 or the pulse S11.
When 07 is input, the L level is held (time s,
v). Here, when the input count information S1111 changes from the H level to the L level (that is, when the counting of the Td time ends), the determination circuit 1112 determines that
The state held by an S-E reset determination unit (not shown) is checked. Then, the S-E reset determination unit (not shown)
When the level is held, the decision circuit 1112 selects the composite value S1110 by the timing control circuit 707 (detection numbers 1 and 2 in FIG. 6b). Here, S- not shown
When the pulse S1101 is input to the E reset determination unit (time point s), the determination circuit 1112 determines that {t0 from time point d1.
-T / 2} timing adjustment signal S for instructing to output the level 0 cross timing at time e1
1112 is output to the timing control circuit 707 (see FIG. 6).
Detection number 1) described in b). Then, the timing control circuit 7
07 holds the state of level 0. When the pulse S1107 is input to the S-E reset determination unit (not shown) (time point v), the determination circuit 1112 outputs the level 1 cross timing at time point e2 when {t0 + T / 2} time has elapsed from time point d2. The timing adjustment signal S1112 for instructing is output to the timing control circuit 707 (detection number 2 in FIG. 6B). Then, the timing control circuit 707 holds the level 1 state.

Next, the case where the phase difference signal which is not in the preamble period is input to the determination circuit 1112 will be described with reference to FIGS. 18f, g, h and i. S- not shown
The E reset determination unit causes the timer circuit 1111 to generate a composite value S1.
When 110 (time point h1) is input and the timer starts counting, the H level is maintained (time point w). But,
Since neither the pulse S1101 nor the pulse S1107 is input to the S-E reset determination unit (not shown), the S-E reset determination unit (not shown) continues to maintain the H level. Then, when the counting of the Td time ends, the determination circuit 1112 checks the state held by the S-E reset determination unit (not shown). Since the S-E reset determination unit (not shown) holds the H level, the determination circuit 1112 selects the composite value S1109 in the timing control circuit 707 (detection number 3 in FIG. 6B). Then, the determination circuit 11
The timing control circuit 707 outputs the timing adjustment signal S1112 instructing to output the level 1 cross timing when {T / 2} time has elapsed from the time point h1.
(Detection number 3 in FIG. 6b). Here, the pulse synthesizing circuit 1109 has not detected level 1. Further, the timing control circuit 707 does not hold level 0. Therefore, the timing control circuit 707 cannot output the level 1 cross timing (FIG. 18i). Here, the timing control circuit 707 holds the previous state.

Next, the case where the phase difference signal which is not in the preamble period is input to the determination circuit 1112 will be described with reference to FIGS. 18j, k, l and m. S- not shown
The E reset determination unit causes the timer circuit 1111 to generate a composite value S1.
When 110 (time point 11) is input and the count of the timer is started, the H level is held (time point x). here,
The S-E reset determination unit (not shown) uses the pulse S1101.
Is input, the L level is held (time point y). Then, when the counting of the Td time is completed, the determination circuit 11
Reference numeral 12 checks the state held by the S-E reset determination unit (not shown). Then, since the S-E reset determination unit (not shown) holds the H level, the determination circuit 1112 selects the composite value S1109 by the timing control circuit 707 (detection number 3 in FIG. 6B). The determination circuit 1112 is
At the time point ml when {T / 2} time has elapsed from the time point l1, the timing adjustment signal S1112 instructing to output the level 1 cross timing is output to the timing control circuit 707 (detection number 3 in FIG. 6b). Then, the timing control circuit 707 holds the level 1 state. Also,
The Td time is not counted at time point l2. But,
Since the timing control circuit 707 does not maintain the 1-level state, the level 1 is crossed, so
At a time point m2 when {T / 2} time has elapsed from 2, a timing adjustment signal S1112 instructing to output the level 1 cross timing is output to the timing control circuit 707 (detection number 3 in FIG. 6B).

In the timing control circuit 707, the combined value S1109 output from the pulse synthesizing circuit 1109 and the combined value S1110 output from the pulse synthesizing circuit 1110.
Then, the timing adjustment signal S1112 output from the trajectory classification circuit 710B is input. Timing control circuit 7
07 delays the composite values S1109 and S1110 by a time corresponding to the instruction of the timing adjustment signal S1112,
A clock reproduction signal S707 is generated. At this time, the timing control circuit 707 causes the timing adjustment signal S11
The state instructed by 12 is retained. Then, the timing control circuit 707 outputs the clock reproduction signal S707 to the DPLL 72. As described above, the clock reproduction signal is generated.

Next, a fourth embodiment of the clock recovery signal generating circuit of the present invention will be described in detail with reference to the drawings. here,
FIG. 16 is a block diagram showing the detailed structure of the fourth embodiment. The clock reproduction circuit includes a clock reproduction signal generation circuit 71D and a DPLL circuit 91.

The clock reproduction signal generation circuit 71D includes the magnitude comparators 1101, 1103, 110.
5, 1107 and level setting circuits 1102, 1104,
1106 and 1108 and pulse synthesizing circuits 1109 and 11
10, a trajectory classification circuit 710B, a timing control circuit 707, a gate circuit 1201, and a phase difference determination circuit 93.
It is composed of and. The trajectory classification circuit 710B includes a timer circuit 1111 and a determination circuit 1112. Here, the magnitude comparator 110
1 and level setting circuit 1102, magnitude comparator 1103 and level setting circuit 1104, magnitude comparator 1105 and level setting circuit 1106, magnitude comparator 1107 and level setting circuit 1
108 are provided correspondingly. The DPLL circuit 91 is the second clock recovery signal generating circuit of the present invention.
The circuit has the same configuration as the circuit described in the above embodiment and operates in the same manner.

Below, the clock recovery signal generation circuit 71
The configuration and operation of D will be described. In FIG. 16, magnitude comparators 1101, 1103, 1105,
1107, the pulse synthesizing circuits 1109 and 1110, the timing control circuit 707, the locus classification circuit 710B, and the phase difference determination circuit 93 are the same as the circuits having the same names and the same symbols explained in the respective embodiments of the clock reproduction signal generating circuit of the present invention. It has the same configuration and operates in the same manner. here,
The determination circuit 1112 of the trajectory classification circuit 710B outputs the timing adjustment signal S1112 generated by the determination circuit 1112 to the gate circuit 1201. Further, the timing control circuit 707 outputs the clock reproduction signal S707 generated by the timing control circuit 707 to the DPLL 91 and the phase difference determination circuit 93.

The phase difference determining circuit 93 performs the same operation as the phase difference determining circuit 93 described in the second embodiment of the clock reproduction signal generating circuit of the present invention as described above. Here, the operation of the phase difference determination circuit 93 will be described with reference to FIG. The phase difference determination circuit 93 has a clock recovery pulse S707 output from the timing control circuit 707.
And the clock signal S9 output from the DPLL circuit 91.
1 is input. The phase difference determination circuit 93 includes a current clock signal (described in FIG. 19a) and a clock signal delayed by π / 4 from the current clock signal (described in FIG. 19b).
A clock signal advanced by π / 4 from the current clock signal (described in FIG. 19c), and a timing control circuit 707.
A pulse for lock reproduction S707 (FIG. 19)
(described in d) is input. Here, the phase difference determination circuit 93
Are input to the three clock signals (FIGS. 19a and 19a).
b) (described in FIG. 19c) (state in the figure), the states of the input clock reproduction pulse S707 and the current clock signal are recognized. The state is such that the current clock signal is L, the clock signal delayed by π / 4 is H, and the clock signal advanced by π / 4 is L. Hereinafter, in the order of the current clock signal, the clock signal delayed by π / 4, and the clock signal advanced by π / 4, the state is H.H.L, the state is H.H.H, and the state is H.L.
H, the state is L ・ L ・ H. The state is L.L.L, the state is L.H.L, and the state is H.H.L. In this case, the phase discrimination determination circuit 93 recognizes that the clock reproduction pulse S707 is in the state of. Then, the phase difference determination circuit 93 determines from the recognized result that the clock signal S91 is input at a desired phase angle (for example, within π / 4). Then, the phase difference determination circuit 93 outputs the phase difference determination signal S93 instructing the constant speed control mode to the gate circuit 1201 and the DPLL circuit 91. Here, the phase difference determination is performed using a signal delayed by π / 4 and a signal advanced by π / 4 from the current clock signal. However, it is not limited to π / 4, and the same effect can be obtained by using π / 2 or the like.

The gate circuit 1201 includes a determination circuit 111.
2 and the phase difference determination signal S93 output from the phase difference determination circuit 93.
Is entered. The input phase difference determination signal S93 is divided into two, that is, a signal for instructing the high speed control mode and a signal for instructing the constant speed control mode. The gate circuit 1201 is
When the input phase difference determination signal S93 indicates the high speed control mode, the timing adjustment signal S1112 is output to the timing control circuit 707. In addition, the gate circuit 120
No. 1 does not output the timing adjustment signal S1112 to the timing control circuit 707 when the input phase difference determination signal S93 indicates the low speed control mode. As described above, the clock reproduction signal is generated.

Clock recovery signal generating circuit 7 of the present invention
1D detects the phase in the phase difference signal 6 using the cross phase for a plurality of detection levels (detection axes),
A clock reproduction pulse S707 is generated. for that reason,
The clock reproduction pulse 71D of the present invention can quickly and correctly synchronize the clock signal S91 with the phase of the input signal in the preamble period, and can generate the clock reproduction pulse S707 with a high probability even after the preamble period ends. . Then, the clock recovery signal generating circuit 71D of the present invention uses the clock recovery pulse S7.
The tracking of 07 can be continued, and the risk of loss of synchronization can be significantly reduced as compared with the conventional clock reproduction signal generation circuit. Further, the clock regeneration signal generation circuit 71D of the present invention is
After pulling the clock signal S91 into the phase of the input signal, the phase is controlled at a low speed. Therefore, even if the pulse includes noise or the like, the noise or the like is ignored and a stable phase of the clock signal S91 is obtained. The fourth embodiment can meet the contradictory demands of rapid clock pull-in and stable clock recovery more than the third embodiment.

In each of the above embodiments, the detection level (detection axis) for estimating the trajectory of the phase difference signal is 2 or 4.
I showed the one. However, the present invention is not limited to this, and may use three or five or more detection levels. In this case, the locus classification number (control type of the timing control circuit) may be appropriately selected according to the number of detection levels.

Further, in each of the above-mentioned embodiments, it is premised that the pattern of the preamble period is the repeating pattern of "1001". However, the preamble pattern may be another one, and in this case, the trajectory classification and the output timing adjustment of the clock recovery pulse may be performed accordingly. Further, the clock recovery signal generation circuit of the present invention can be widely applied to the delay detection circuit of the π / 4 shift QPSK signal, and the application is not limited to the digital mobile communication.

As described above, according to the clock reproduction signal generating circuit of the present invention, a plurality of detection axes having different detection axis values for detecting the timing at which the phase difference signal crosses the detection axis having the predetermined value are detected. The intersection detection means and the detection timings of the plurality of detection axis intersection detection means are described in advance.
Determine which of the multiple detection conditions that are stored
And estimates the change in trajectory of the phase difference signal based on the filled detection condition, the locus classifying means for outputting a timing adjustment signal according to the estimation result, either the detection axis which the timing adjustment signal is pointed out the detection timing by the cross detecting means, the timing adjustment signal constituted the clock recovery signal generating circuit in the timing control means for generating a clock reproduction signal corrected by the time the instruction, after retraction time and pull the clock signal Even in the case of good reproduction.

[0114]

As described above, the differential detection circuit having the instantaneous phase detection circuit or the clock regeneration signal generation circuit of the present invention is applicable to police, flood control, road management, firefighting, disaster prevention administrative radio,
For public services such as electricity, gas, water, taxis, railways, newspapers, broadcasting, MCA land mobile radio communication systems, automatic vehicle position display systems, on-site radio stations, specified low-power radio stations, etc.
It is used for mobile communication systems for general or personal communication such as personal radio stations and amateur radio stations.
In addition, for land mobile communication such as car phone, cordless phone, train public phone, land mobile radio data communication, airport mobile radio, maritime mobile communication such as ship telephone, maritime satellite communication, port radio telephone communication, airplane public telephone Used in mobile communication systems for telecommunication business such as aircraft mobile communication.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an instantaneous phase detection circuit of the present invention.

FIG. 2 is a table showing a calculation processing pattern of a comparison circuit of the present invention.

FIG. 3 is a graph showing a first phase detection characteristic, a second phase detection characteristic obtained by a moving average filter circuit, and a processing result of the instantaneous phase detection circuit of the present invention.

FIG. 4 is a block diagram showing a first embodiment of a clock recovery signal generating circuit of the present invention.

FIG. 5 is a diagram showing data used in the present invention.

FIG. 6 is a diagram showing a detection condition and a timing adjustment output.

FIG. 7 is a diagram showing a trajectory pattern of a phase difference signal, output timing adjustment and output timing of a clock recovery pulse.

FIG. 8 is a diagram showing a trajectory pattern of a phase difference signal.

FIG. 9 is a diagram showing a trajectory pattern of a phase difference signal.

FIG. 10 is a diagram showing a trajectory pattern of a phase difference signal.

FIG. 11 is a diagram showing a trajectory pattern of a phase difference signal.

FIG. 12 is a diagram showing a trajectory pattern of a phase difference signal.

FIG. 13 is a block diagram showing a second embodiment of the clock recovery signal generating circuit of the present invention.

FIG. 14 is a diagram showing a detection condition and a timing adjustment output.

FIG. 15 is a block diagram showing a third embodiment of the clock recovery signal generating circuit of the present invention.

FIG. 16 is a block diagram showing a fourth embodiment of the clock recovery signal generating circuit of the present invention.

FIG. 17 is a diagram showing locus patterns of phase difference signals and pulse generation timing.

FIG. 18 is a diagram showing a trajectory pattern of a phase difference signal and a pulse generation timing.

FIG. 19 is a diagram showing a current and a clock signal advanced by π / 4 and advanced by π / 4 from the current clock signal.

FIG. 20 is a block diagram showing a conventional differential detection circuit.

FIG. 21 is a block diagram showing a conventional instantaneous phase detection circuit.

FIG. 22 is a diagram showing a phase detection characteristic processed by an EX-OR circuit and an LPF, a phase detection characteristic of a DFF circuit, and a linear phase detection characteristic.

FIG. 23 is a diagram showing a conventional clock recovery circuit.

FIG. 24 is a diagram showing a locus pattern of a phase difference signal and output timing of a conventional clock reproduction signal.

[Explanation of symbols]

701,703 Magnitude comparator 702, 704 Level setting circuit 705 timer circuit 706 Judgment circuit 707 Timing control circuit 710 Trajectory classification circuit

Continuation of the front page (56) References Japanese Patent Publication Sho 58-40386 (JP, B1) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/00 H04L 7/00

Claims (3)

(57) [Claims] 1. A clock regeneration signal generating circuit for generating a clock regeneration signal, wherein a phase difference signal is input and a timing at which the phase difference signal crosses a detection axis having a predetermined value is detected Different detection axis crossing detection means and detection timings by the plurality of detection axis crossing detection means
Is one of the multiple detection conditions stored in advance.
A trajectory classifying unit for determining whether or not the condition is satisfied , estimating a change trajectory of the phase difference signal based on the satisfied detection condition, and outputting a timing adjustment signal according to the estimation result; A clock reproduction means for generating a clock reproduction signal in which the detection timing by any one of the detection axis crossing detection means indicated by a signal is corrected by the time indicated by the timing adjustment signal. Signal generator circuit. 2. A phase difference determining means is provided for detecting that an error between the phase of the reproduced clock signal and the phase of the clock reproducing signal is equal to or less than a predetermined value, and the trajectory classification means is provided with the phase difference determining means. 2. The clock recovery signal generating circuit according to claim 1, wherein when the determination means performs a detection operation, the processing is performed using only the detection timing by any one of the detection axis crossing detection means. 3. The clock regeneration signal generating circuit according to claim 1, wherein four detection axis crossing detection means are provided to detect timing using two detection axes.