JP3402238B2 - Tape carrier for semiconductor devices - Google Patents
Tape carrier for semiconductor devicesInfo
- Publication number
- JP3402238B2 JP3402238B2 JP01295499A JP1295499A JP3402238B2 JP 3402238 B2 JP3402238 B2 JP 3402238B2 JP 01295499 A JP01295499 A JP 01295499A JP 1295499 A JP1295499 A JP 1295499A JP 3402238 B2 JP3402238 B2 JP 3402238B2
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- nickel plating
- tape carrier
- semiconductor device
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Chemically Coating (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置用テー
プキャリアに関し、特に、ワイヤーボンディングによっ
て配線パターンと半導体チップを接続する形式の半導体
装置用テープキャリアに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device tape carrier, and more particularly to a semiconductor device tape carrier of a type in which a wiring pattern is connected to a semiconductor chip by wire bonding.
【０００２】[0002]
【従来の技術】この種のテープキャリアとしては、ポリ
イミド等の絶縁フィルムの表面に銅箔を貼り合わせ、貼
り合わせた銅箔をエッチング加工することによって所定
の形状の配線パターンを形成し、配線パターンの上にめ
っき層を形成したものが広く使用されている。2. Description of the Related Art As a tape carrier of this type, a wiring pattern having a predetermined shape is formed by bonding a copper foil to the surface of an insulating film such as polyimide and etching the bonded copper foil. The one with a plated layer formed on is widely used.
【０００３】図４はその具体例を示したもので、１は絶
縁フィルム、２は絶縁フィルム１の表面に形成された配
線パターン、３は配線パターン２の上に形成されたニッ
ケルめっき層、５はニッケルめっき層３の上に形成され
た金めっき層を示す。FIG. 4 shows a specific example thereof, 1 is an insulating film, 2 is a wiring pattern formed on the surface of the insulating film 1, 3 is a nickel plating layer formed on the wiring pattern 2, 5 Indicates a gold plating layer formed on the nickel plating layer 3.
【０００４】この構成における金めっき層５は、材質的
な面からワイヤーボンディング性を保証し、一方、ニッ
ケルめっき層３は、その硬質性によって金めっき層５を
支持し、これにより構造的な面からワイヤーボンディン
グ性を保証する。通常、ニッケルめっき層３には、８重
量％以上のリンを含むニッケル材料が使用される。The gold plating layer 5 in this structure guarantees wire bondability from a material standpoint, while the nickel plating layer 3 supports the gold plating layer 5 by virtue of its hardness, thereby providing a structural surface. Guarantees wire bondability. Usually, a nickel material containing 8% by weight or more of phosphorus is used for the nickel plating layer 3.
【０００５】[0005]
【発明が解決しようとする課題】しかし、従来の半導体
装置用テープキャリアによると、ニッケルめっき層と金
めっき層の密着性が必ずしも充分ではなく、両めっき層
間に剥離を発生させることがある。剥離はワイヤーボン
ディングによる接続を不安定なものにし、半導体装置の
品質を大きく低下させる。However, according to the conventional tape carrier for a semiconductor device, the adhesion between the nickel plating layer and the gold plating layer is not always sufficient, and peeling may occur between both plating layers. The peeling makes the connection by wire bonding unstable and significantly deteriorates the quality of the semiconductor device.
【０００６】従って、本発明の目的は、ニッケルめっき
層と金めっき層の密着が良好で、両層間に剥離が発生す
る恐れのない半導体装置用テープキャリアを提供するこ
とにある。Therefore, an object of the present invention is to provide a tape carrier for a semiconductor device, which has good adhesion between the nickel plating layer and the gold plating layer and is free from the possibility of peeling between the two layers.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記の目的を
達成するため、絶縁フィルムと、前記絶縁フィルムの表
面に形成された配線パターンと、前記配線パターンの上
に形成されたニッケルめっき層と、前記ニッケルめっき
層の上に形成された金めっき層から構成される半導体装
置用テープキャリアにおいて、前記ニッケルめっき層
は、前記ニッケルめっき層を８重量％以上のリンを含む
第１のニッケルめっき層と、２重量％以下のリンを含む
第２のニッケルめっき層によって構成されることを特徴
とする半導体装置用テープキャリアを提供するものであ
る。In order to achieve the above object, the present invention provides an insulating film, a wiring pattern formed on the surface of the insulating film, and a nickel plating layer formed on the wiring pattern. And a gold plating layer formed on the nickel plating layer, wherein the nickel plating layer is the first nickel plating containing 8 wt% or more of phosphorus. The present invention provides a tape carrier for a semiconductor device, which comprises a layer and a second nickel plating layer containing 2% by weight or less of phosphorus.
【０００８】また、本発明は、上記の目的を達成するた
め、絶縁フィルムと、前記絶縁フィルムの表面に形成さ
れた配線パターンと、前記配線パターンの上に形成され
たニッケルめっき層と、前記ニッケルめっき層の上に形
成された金めっき層から構成される半導体装置用テープ
キャリアにおいて、前記ニッケルめっき層は、８重量％
以上のリンを含むニッケルめっき層と、ホウ素ニッケル
めっき層によって構成されることを特徴とする半導体装
置用テープキャリアを提供するものである。In order to achieve the above object, the present invention provides an insulating film, a wiring pattern formed on the surface of the insulating film, a nickel plating layer formed on the wiring pattern, and the nickel. In a tape carrier for a semiconductor device, which is composed of a gold plating layer formed on a plating layer, the nickel plating layer is 8% by weight.
It is intended to provide a tape carrier for a semiconductor device, characterized by comprising the above-mentioned nickel-plated layer containing phosphorus and a boron-nickel-plated layer.
【０００９】絶縁フィルムの構成材としては、ポリイミ
ドフィルム、ポリエステルフィルム等が使用され、配線
パターンの構成材としては、銅箔、銅合金箔等が使用さ
れる。リン含有量の異なる２つのニッケルめっき層とホ
ウ素ニッケルめっき層は、無電解めっきによって形成す
ることが好ましい。A polyimide film, a polyester film or the like is used as the constituent material of the insulating film, and a copper foil, a copper alloy foil or the like is used as the constituent material of the wiring pattern. The two nickel plating layers and the boron nickel plating layer having different phosphorus contents are preferably formed by electroless plating.
【００１０】[0010]
【発明の実施の形態】次に、本発明による半導体装置用
テープキャリアの実施の形態について説明する。図１に
おいて、１はポリイミドフィルム、２はフィルム１の表
面に所定の形状に設けられた配線パターン、３は配線パ
ターン２の上に形成された８重量％以上のリンを含むニ
ッケルめっき層、５はニッケルめっき層３との間にめっ
き層４を介して形成された金めっき層を示す。BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a tape carrier for a semiconductor device according to the present invention will be described. In FIG. 1, 1 is a polyimide film, 2 is a wiring pattern provided on the surface of the film 1 in a predetermined shape, 3 is a nickel plating layer containing 8% by weight or more of phosphorus formed on the wiring pattern 2, 5 Indicates a gold plating layer formed between the nickel plating layer 3 and the plating layer 4.
【００１１】めっき層４は、２種類のめっき層のいずれ
かによって構成され、その一方は、２重量％以下のリン
を含有するニッケルめっき層であり、他方はホウ素ニッ
ケルめっき層である。The plating layer 4 is composed of either of two types of plating layers, one of which is a nickel plating layer containing 2% by weight or less of phosphorus and the other of which is a boron nickel plating layer.
【００１２】図２は、図１のテープキャリアを使用して
構成された半導体装置を示し、６はテープキャリアに搭
載された半導体チップ、７は半導体チップ６の電極（図
示せず）と配線パターン２の所定の個所の金めっき層５
との間を接続したボンディングワイヤー、８は半導体チ
ップ６とボンディングワイヤー７の周囲に形成した樹脂
封止部を示す。図３は、他の半導体装置の構成を示し、
テープキャリアに形成されたデバイスホール９の中に半
導体チップ６を搭載している点で、図２の半導体装置と
異なる。FIG. 2 shows a semiconductor device constructed by using the tape carrier of FIG. 1, 6 is a semiconductor chip mounted on the tape carrier, 7 is an electrode (not shown) of the semiconductor chip 6 and a wiring pattern. 2 Gold plating layer 5 at a predetermined location
A bonding wire 8 connected between and is a resin sealing portion formed around the semiconductor chip 6 and the bonding wire 7. FIG. 3 shows the configuration of another semiconductor device,
2 in that the semiconductor chip 6 is mounted in the device hole 9 formed in the tape carrier.
【００１３】[0013]
【実施例】厚さ１８μｍの銅箔と厚さ５０μｍのポリイ
ミドフィルムを厚さ１２μｍの接着剤によって貼り合わ
せた後、銅箔にソルダレジストを塗布し、これにより形
成されたソルダレジスト層に露光と現像を施すことによ
って所定のパターンの銅箔の露出部を形成し、その後、
銅箔の露出部をエッチングすることによって所定の形状
の配線パターン２を形成した。EXAMPLE A copper foil having a thickness of 18 μm and a polyimide film having a thickness of 50 μm were bonded to each other with an adhesive having a thickness of 12 μm, a solder resist was applied to the copper foil, and a solder resist layer thus formed was exposed to light. By forming the exposed portion of the copper foil of a predetermined pattern by developing, then,
The exposed portion of the copper foil was etched to form the wiring pattern 2 having a predetermined shape.
【００１４】次いで、洗浄と水洗を施した後、これを無
電解ニッケルめっき液に浸漬し、配線パターン２の上に
ニッケルめっき層３を形成した。めっき液としては、ニ
ムデンＳＸ（上村工業社商品名。リン含有量８重量％の
ニッケルめっき液）、あるいはトップニコロンＤ−１３
０（奥野製薬社商品名。リン含有量１２重量％のニッケ
ルめっき液）を使用し、いずれの場合も浴液を９０℃に
加熱して、めっき厚さが２μｍになるようにめっき処理
を施した。Next, after washing and washing with water, this was immersed in an electroless nickel plating solution to form a nickel plating layer 3 on the wiring pattern 2. As the plating solution, Nimden SX (trade name of Uemura Kogyo Co., Ltd. nickel plating solution having a phosphorus content of 8% by weight) or Top Nicolon D-13
0 (trade name of Okuno Seiyaku Co., nickel plating solution with a phosphorus content of 12% by weight) is used, and in each case, the bath solution is heated to 90 ° C. to perform plating treatment so that the plating thickness becomes 2 μm. did.
【００１５】次に、これを、トップニコロンＳＰ−１５
（奥野製薬社商品名。リン含有量２重量％のニッケル用
無電解めっき液。液温９０℃に設定）、あるいはＢＥＬ
ニッケル（上村工業社商品名。ホウ素ニッケル用無電解
めっき液。液温６５℃に設定）に浸漬することによっ
て、リン含有量２重量％および厚さ０．２μｍの第２の
ニッケルめっき層４、あるいは同じく厚さが０．２μｍ
のホウ素ニッケルめっき層４を形成した後、ＧＯＢＥＬ
−２Ｍ（上村工業社商品名。金めっき液）を使用して、
これらめっき層４の上に厚さ０．５μｍの金めっき層５
を形成した。Next, this is top Nicolon SP-15.
(Okuno Pharmaceutical Co., Ltd. product name. Electroless plating solution for nickel with a phosphorus content of 2% by weight. Liquid temperature set to 90 ° C), or BEL
The second nickel plating layer 4 having a phosphorus content of 2% by weight and a thickness of 0.2 μm is immersed in nickel (trade name of Uemura Kogyo Co., electroless plating solution for boron nickel; liquid temperature is set to 65 ° C.). Or similarly, the thickness is 0.2 μm
GOBEL after forming the boron-nickel plated layer 4 of
-2M (trade name of Uemura Kogyo. Gold plating solution)
A gold plating layer 5 having a thickness of 0.5 μm is formed on these plating layers 4.
Was formed.
【００１６】表１は、以上の実施例により得られた半導
体装置用テープキャリアの特性試験結果を従来例との対
比において示したものである。表中、テープピーリング
試験とは、金めっき層５に接着用セロハンテープを貼り
付けてこれを剥がしたときの金めっき層５の剥離の有無
を観察する試験である。Table 1 shows the characteristic test results of the tape carriers for semiconductor devices obtained by the above examples in comparison with the conventional example. In the table, the tape peeling test is a test for observing the presence or absence of peeling of the gold plating layer 5 when the adhesive cellophane tape is attached to the gold plating layer 5 and peeled off.
【００１７】また、金ワイヤーピール試験とは、樹脂封
止前の半導体装置において、配線パターン２と半導体チ
ップ６の電極の間に結線された金のボンディングワイヤ
ー７を真上に引っ張ったときの金ワイヤーの破断強度と
破断モードを調べるもので、ワイヤーボンディング性を
評価する試験である。なお、各実施例および従来例の試
験用サンプルの数は、各試験ともそれぞれ２０個ずつと
した。The gold wire peel test is a gold test when the gold bonding wire 7 connected between the wiring pattern 2 and the electrode of the semiconductor chip 6 is pulled right above in the semiconductor device before resin sealing. This is a test for evaluating the wire bondability by examining the breaking strength and breaking mode of the wire. The number of test samples in each of the examples and the conventional example was 20 in each test.
【００１８】[0018]
【表１】 [Table 1]
【００１９】表１によれば、実施例がテープピーリング
試験においていずれも金めっき層５の剥離を発生させ
ず、さらに、金ワイヤーピール試験においても剥離のな
い高いピール強度を示しているのに比べ、従来例の場合
には、テープピーリング試験および金ワイヤーピール試
験の双方において金めっき層５の剥離を発生させ、さら
に、ピール強度の平均値においても金ワイヤー本来の強
度に至らない低いレベルにとどまっている。本発明によ
る効果が明確に認められる。According to Table 1, none of the examples cause peeling of the gold plating layer 5 in the tape peeling test, and further, in the gold wire peel test, high peel strength without peeling is shown. In the case of the conventional example, peeling of the gold plating layer 5 occurs in both the tape peeling test and the gold wire peeling test, and the average peel strength remains at a low level that does not reach the original strength of the gold wire. ing. The effect of the present invention is clearly recognized.
【００２０】[0020]
【発明の効果】以上のように、本発明による半導体装置
用テープキャリアによれば、硬質性を保証するために配
線パターンに形成されるリン含有量８重量％以上のニッ
ケルめっき層と金めっき層の間に、リン含有量が２重量
％以下のニッケルめっき層を形成するか、あるいはホウ
素ニッケルめっき層を形成することによってニッケルめ
っき層と金めっき層の密着性を向上させるものであり、
従って、金めっき層が剥離する恐れのない良質な半導体
装置用テープキャリアを提供することができる。As described above, according to the tape carrier for a semiconductor device of the present invention, the nickel plating layer and the gold plating layer having a phosphorus content of 8% by weight or more, which are formed in the wiring pattern to ensure the hardness, are formed. To form a nickel plating layer having a phosphorus content of 2% by weight or less, or a boron nickel plating layer to improve the adhesion between the nickel plating layer and the gold plating layer.
Therefore, it is possible to provide a good quality tape carrier for a semiconductor device in which the gold plating layer is not likely to peel off.
【図１】本発明による半導体装置用テープキャリアの実
施の形態を示す説明図。FIG. 1 is an explanatory view showing an embodiment of a tape carrier for a semiconductor device according to the present invention.
【図２】図１のテープキャリアを使用して構成した半導
体装置を示す説明図。FIG. 2 is an explanatory diagram showing a semiconductor device configured by using the tape carrier of FIG.
【図３】本発明の半導体装置用テープキャリアの他の実
施の形態によるテープキャリアに基づいて構成した半導
体装置を示す説明図。FIG. 3 is an explanatory diagram showing a semiconductor device configured based on a tape carrier according to another embodiment of the semiconductor device tape carrier of the present invention.
【図４】従来の半導体装置用テープキャリアを示す説明
図。FIG. 4 is an explanatory diagram showing a conventional tape carrier for a semiconductor device.
１ ポリイミドフィルム ２ 配線パターン ３ ニッケルめっき層 ４ めっき層 ５ 金めっき層 1 Polyimide film 2 wiring pattern 3 Nickel plating layer 4 plating layer 5 gold plating layer
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平８−139228（ＪＰ，Ａ) 特開 平10−303231（ＪＰ，Ａ) 特開 平３−173144（ＪＰ，Ａ) 特開 平７−268640（ＪＰ，Ａ) 特開 平10−219469（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-8-139228 (JP, A) JP-A-10-303231 (JP, A) JP-A-3-173144 (JP, A) JP-A-7- 268640 (JP, A) JP-A-10-219469 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 H01L 23/12
Claims (4)
に形成された配線パターンと、前記配線パターンの上に
形成されたニッケルめっき層と、前記ニッケルめっき層
の上に形成された金めっき層から構成される半導体装置
用テープキャリアにおいて、 前記ニッケルめっき層は、８重量％以上のリンを含む第
１のニッケルめっき層と、２重量％以下のリンを含む第
２のニッケルめっき層によって構成されることを特徴と
する半導体装置用テープキャリア。1. An insulating film, a wiring pattern formed on the surface of the insulating film, a nickel plating layer formed on the wiring pattern, and a gold plating layer formed on the nickel plating layer. In the tape carrier for a semiconductor device configured, the nickel plating layer includes a first nickel plating layer containing 8% by weight or more of phosphorus and a second nickel plating layer containing 2% by weight or less of phosphorus. A tape carrier for a semiconductor device, which is characterized in that
は、無電解めっきによって形成されることを特徴とする
請求項１項記載の半導体装置用テープキャリア。2. The tape carrier for a semiconductor device according to claim 1, wherein the first and second nickel plating layers are formed by electroless plating.
に形成された配線パターンと、前記配線パターンの上に
形成されたニッケルめっき層と、前記ニッケルめっき層
の上に形成された金めっき層から構成される半導体装置
用テープキャリアにおいて、前記ニッケルめっき層は、
８重量％以上のリンを含むニッケルめっき層と、ホウ素
ニッケルめっき層によって構成されることを特徴とする
半導体装置用テープキャリア。3. An insulating film, a wiring pattern formed on the surface of the insulating film, a nickel plating layer formed on the wiring pattern, and a gold plating layer formed on the nickel plating layer. In the tape carrier for a semiconductor device configured, the nickel plating layer,
A tape carrier for a semiconductor device comprising a nickel plating layer containing 8% by weight or more of phosphorus and a boron nickel plating layer.
ルめっき層は、無電解メッキによって形成されることを
特徴とする請求項３項記載の半導体装置用テープキャリ
ア。4. The tape carrier for a semiconductor device according to claim 3, wherein the nickel plating layer and the boron nickel plating layer are formed by electroless plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01295499A JP3402238B2 (en) | 1999-01-21 | 1999-01-21 | Tape carrier for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01295499A JP3402238B2 (en) | 1999-01-21 | 1999-01-21 | Tape carrier for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000216201A JP2000216201A (en) | 2000-08-04 |
| JP3402238B2 true JP3402238B2 (en) | 2003-05-06 |
Family
ID=11819678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01295499A Expired - Fee Related JP3402238B2 (en) | 1999-01-21 | 1999-01-21 | Tape carrier for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3402238B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003110209A (en) * | 2001-10-02 | 2003-04-11 | Matsushita Electric Ind Co Ltd | Electronic component |
| JP2006200925A (en) * | 2005-01-18 | 2006-08-03 | Denso Corp | Pressure sensor |
| JP4865381B2 (en) * | 2006-03-30 | 2012-02-01 | 古河電気工業株式会社 | Film metal laminate, method for producing the same, circuit board using the film metal laminate, and method for producing the circuit board |
-
1999
- 1999-01-21 JP JP01295499A patent/JP3402238B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000216201A (en) | 2000-08-04 |
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