JP3401891B2 - Lead frame manufacturing method - Google Patents
Lead frame manufacturing methodInfo
- Publication number
- JP3401891B2 JP3401891B2 JP00435694A JP435694A JP3401891B2 JP 3401891 B2 JP3401891 B2 JP 3401891B2 JP 00435694 A JP00435694 A JP 00435694A JP 435694 A JP435694 A JP 435694A JP 3401891 B2 JP3401891 B2 JP 3401891B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- holes
- lead
- insulating sheet
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路を実装
するリードフレームの製造方法に関し、特に、リード数
が多く、リード幅・リード間隔が狭いリードフレームの
製造方法に関する。BACKGROUND OF THE INVENTION This invention relates to a method of manufacturing a lead frame for mounting the semiconductor integrated circuit, in particular, the number of leads increases, the lead width and lead spacing is narrow lead frame
It relates to a manufacturing method .
【０００２】[0002]
【従来の技術】一般にリードフレームは、４２合金（Ｎ
ｉ４２重量％、Ｆｅ残）に代表される鉄系合金や、リン
青銅に代表される銅合金などの金属板を、プレス法（所
望のパターンを有する金型でプレス加工により成形する
方法）やエッチング法（上記金属板上にフォトレジスト
膜をパターン形成した後、塩化第二鉄等のエッチング液
にて腐食させ、金属板を前記パターン形状に成形し、次
いでフォトレジスト膜を除去する方法）により製造して
いる。2. Description of the Related Art Generally, a lead frame is made of 42 alloy (N
i 42 wt%, Fe residue), a metal plate such as an iron-based alloy typified by phosphorous bronze, or a copper alloy typified by phosphor bronze, is subjected to a pressing method (a method in which a die having a desired pattern is formed by pressing) or etching Manufactured by the method (patterning a photoresist film on the metal plate, then corroding it with an etching solution such as ferric chloride to form the metal plate into the pattern shape, and then removing the photoresist film) is doing.
【０００３】近年、半導体集積回路が用いられている電
子機器では、小型化・高性能化が要求されるようになっ
てきた。これに伴い、半導体集積回路の高集積化が進
み、チップサイズの小型化・多電極化への方向に向かう
ようになってきた。従って、半導体装置を構成している
リードフレームに対しても、半導体集積回路の表面に形
成される電極に対しても、ピッチをより一層狭くする必
要が生じてきた。In recent years, electronic devices using semiconductor integrated circuits have been required to be smaller and have higher performance. Along with this, high integration of semiconductor integrated circuits has progressed, and there has been a trend toward smaller chip size and more electrodes. Therefore, it has become necessary to further reduce the pitch of both the lead frame forming the semiconductor device and the electrodes formed on the surface of the semiconductor integrated circuit.
【０００４】現状の電気的接続方法として主流となって
いるＡｕワイヤ等によるワイヤボンディング法を採用す
る場合、使用するボンディング用キャピラリ（針）の外
形に依存し、インナーリードの平坦幅・隣接するボンデ
ィング間距離が制約を受ける。しかし、インナーリード
平坦幅を約８０μｍ程度以下、半導体集積回路上の電極
間距離を約１００μｍ程度以下に縮小する事は、技術的
に困難である。When the wire bonding method using Au wire or the like, which is the main current electrical connection method, is adopted, the flat width of the inner leads and adjacent bonding depend on the outer shape of the bonding capillary (needle) used. Distance is restricted. However, it is technically difficult to reduce the flat width of the inner leads to about 80 μm or less and the distance between the electrodes on the semiconductor integrated circuit to about 100 μm or less.
【０００５】また、ワイヤボンディング法での、Ａｕワ
イヤやＡｌワイヤと半導体集積回路上に形成された電極
との金属間接合では、加熱・加圧・超音波振動などの物
理的負荷を加える必要があり、時としては、電極・電極
下の半導体集積回路そのものにもダメージを与えるとい
う問題がある。上記従来技術にかかる半導体装置を図４
の平面図に示す。Further, in the metal bonding between the Au wire or the Al wire and the electrode formed on the semiconductor integrated circuit by the wire bonding method, it is necessary to apply a physical load such as heating, pressurization and ultrasonic vibration. In some cases, there is a problem that the electrodes and the semiconductor integrated circuit itself under the electrodes are also damaged. FIG. 4 shows a semiconductor device according to the above conventional technique.
Is shown in the plan view of FIG.
【０００６】[0006]
【発明が解決しようとする課題】本発明は、以上のよう
な問題点に着目してなされたもので、リードフレームの
多ピン化・狭ピッチ化、また、半導体集積回路上の多電
極化に対応した、製造（特に、リードフレームと半導体
集積回路との接続）にあたって物理的負荷が少なく、信
頼性の高いリードフレームの製造方法を提供することを
目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is directed to a lead frame having a large number of pins and a narrow pitch, and a semiconductor integrated circuit having a large number of electrodes. It is an object of the present invention to provide a corresponding method of manufacturing a lead frame which has a small physical load and is highly reliable in manufacturing (particularly, connection between a lead frame and a semiconductor integrated circuit).
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明が提案するリードフレームの製造方法は、両
面が接着性を有する絶縁性のシートに、一方の面から反
対の面まで貫通する複数の貫通孔を設ける工程と、前記
貫通孔がインナーリードのボンディング領域に当接する
ように前記絶縁シートを接着する工程と、メッキマスク
を施す工程と、電気メッキにより貫通孔を導電体で充填
する工程よりなることを特徴とする。 In order to achieve the above object, a method of manufacturing a lead frame proposed by the present invention is to penetrate an insulating sheet having adhesiveness on both sides from one side to the opposite side. And a step of providing a plurality of through holes,
The through hole contacts the bonding area of the inner lead.
Step of adhering the insulating sheet, and plating mask
Filling the through holes with a conductor by electroplating
It is characterized by comprising the step of
【０００８】また、本発明が提案するリードフレームの
製造方法は、両面が接着性を有する絶縁性のシートに、
一方の面から反対の面まで貫通する複数の貫通孔を設け
る工程と、前記貫通孔がインナーリードのボンディング
領域に当接するように前記絶縁シートを接着する工程
と、前記貫通孔及び前記絶縁シートの接着面とは反対側
の面を除き、メッキマスクを施す工程と、前記インナー
リードと前記絶縁シートの非接着面上の間を電気メッキ
し貫通孔を導電体で充填する工程よりなることを特徴と
する。 The lead frame proposed by the present invention is
The manufacturing method is an insulating sheet with adhesive on both sides,
Providing multiple through holes from one surface to the other
And the through holes are bonded to the inner leads
Step of adhering the insulating sheet so as to abut the area
And the side opposite to the bonding surface of the through hole and the insulating sheet
Except for the surface of the
Electroplating between the lead and the non-bonded surface of the insulation sheet
It is characterized by comprising a step of filling the through hole with a conductor.
To do.
【０００９】[0009]
【作用】このような構成とすることにより、使用するボ
ンディング用キャピラリ（針）の外形に依存し、インナ
ーリードの平坦幅・隣接するボンディング間距離が制約
を受けることがない。また、ワイヤボンディング法によ
らずに電気的導通が図れるため、前記した各種の物理的
負荷（加熱・加圧・超音波振動など）を受けず、半導体
集積回路にダメージの少ない高信頼性の半導体装置が提
供される。With this structure, the flat width of the inner lead and the distance between adjacent bondings are not restricted, depending on the outer shape of the bonding capillary (needle) used. In addition, since electrical conduction can be achieved without using the wire bonding method, the semiconductors are highly reliable semiconductors that are not subject to the various physical loads described above (heating, pressurization, ultrasonic vibrations, etc.) and have little damage to semiconductor integrated circuits. A device is provided.
【００１０】[0010]
【実施例】以下、図面を参照して本発明の参考の為の実
施例について説明する。図１(a)は、本参考の為の実施
例にかかる半導体装置を説明する平面図であり、図１
(b)は、図１(a) のＡ−Ａ線における断面説明図であ
る。接続用部材（３）を用いて、インナーリード先端部
（１）と電極（６）とを位置合わせをした後に貼り合わ
せ固定する。この時、接続用部材（３）に形成された微
小導体部（４）によって、リードフレームのインナーリ
ード先端部（１）と電極（６）とは電気的に接続される
ことになる。EXAMPLES The following describes the actual <br/>施例for reference of the present invention with reference to the drawings. FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment for reference .
1B is a cross-sectional explanatory view taken along the line AA of FIG. The tip (1) of the inner lead and the electrode (6) are aligned using the connecting member (3), and then bonded and fixed. At this time, the inner conductor tip portion (1) of the lead frame and the electrode (6) are electrically connected by the minute conductor portion (4) formed on the connecting member (3).
【００１１】次に、本参考の為の実施例にかかるリード
フレームについて説明する。本発明では、アイランドの
無いリードフレームを用いる。板厚は０．１５ｍｍ、イ
ンナーリードピッチが０．１５ｍｍ、インナーリード平
坦幅が０．０５ｍｍ、アウターリードピッチが０．３ｍ
ｍ、アウターリード幅が０．１ｍｍ、ピン数は１６０ピ
ンのものを用いた。Next, a lead frame according to an embodiment for reference will be described. In the present invention, a lead frame having no island is used. Thickness is 0.15mm, inner lead pitch is 0.15mm, inner lead flat width is 0.05mm, outer lead pitch is 0.3m.
m, the outer lead width was 0.1 mm, and the number of pins was 160 pins.
【００１２】このリードフレームのインナーリード先端
部分（１）に、１６０個の微小導体部（４）を有する接
続用部材（３）を、前記微小導体部とリードフレームの
インナーリード部（１）とが対応するように配置させ
る。その後、インナーリード先端部（１）と半導体集積
回路上に形成された電極（６）とを位置合わせし、熱プ
レス法により、１５０℃・３０分間の条件で加熱圧着を
行うことにより一括接続を行う。At the tip (1) of the inner lead of the lead frame, a connecting member (3) having 160 minute conductors (4) is connected to the minute conductors and the inner lead (1) of the lead frame. So that they correspond. After that, the inner lead tip (1) and the electrode (6) formed on the semiconductor integrated circuit are aligned with each other, and thermocompression bonding is performed at a temperature of 150 ° C. for 30 minutes by a hot pressing method to collectively connect them. To do.
【００１３】図２(a) 〜図２(d) は、接続用部材（３）
の各種例を示す説明図である。接続用部材（３）とし
て、厚さ０．０５ｍｍの、東亜合成化学工業株式会社製
接着剤シートＢＸ−６０を用いた。2 (a) to 2 (d) show a connecting member (3).
It is an explanatory view showing various examples of. As the connecting member (3), an adhesive sheet BX-60 manufactured by Toa Gosei Chemical Industry Co., Ltd. having a thickness of 0.05 mm was used.
【００１４】接続用部材（３）は、単一の接着剤層（図
２(b) ）であっても良いし、或いは、ガラス転移点が接
着剤の接着温度以上の高分子フィルム（１１）を中間層
として用い、その両面に接着剤が塗布されている構成の
シート（図２(c) ）であっても良く、そのいずれかを使
用する事ができる。The connecting member (3) may be a single adhesive layer (FIG. 2 (b)), or a polymer film (11) whose glass transition point is equal to or higher than the adhesive bonding temperature of the adhesive. May be used as an intermediate layer and an adhesive is applied to both surfaces thereof (FIG. 2 (c)), either of which can be used.
【００１５】微小導体部（４）は、インナーリードの本
数分だけ形成しても良いし、（図２(a) ）或いは、イン
ナーリードの本数を超える多数個形成しても良い。（図
２(d) ）The minute conductors (4) may be formed by the number of inner leads (FIG. 2 (a)) or a large number of inner leads may be formed. (Fig. 2 (d))
【００１６】次に、接続用部材の製造方法について、そ
の一例を説明する。東亜合成化学工業株式会社製接着剤
シートＢＸ−６０を所定のサイズ・形状（図２(a) に示
す形状）に加工する。Next, an example of a method of manufacturing the connecting member will be described. The adhesive sheet BX-60 manufactured by Toagosei Kagaku Kogyo Co., Ltd. is processed into a predetermined size and shape (shape shown in FIG. 2 (a)).
【００１７】この際、ステンレス製のマスクを用い、波
長が、２４８ｎｍのＫｒＦエキシマレーザー光を照射し
て貫通孔（１４）を、所望個数だけ形成した。At this time, a stainless mask was used to irradiate KrF excimer laser light having a wavelength of 248 nm to form a desired number of through holes (14).
【００１８】貫通孔（１４）の各上面形状は、０．０５
ｍｍ径の円形で、個数は、１辺が４０個の計１６０個
で、そのピッチは０．１５ｍｍである。The shape of each top surface of the through hole (14) is 0.05
It is a circle with a diameter of mm, and the total number is 160, which is 40 on each side, and the pitch is 0.15 mm.
【００１９】また、この貫通孔を、より微小な孔とし、
多数形成する場合（図２(d) ）は、インナーリードとの
位置合わせがより容易となる。Further, this through hole is made into a finer hole,
When forming a large number (FIG. 2 (d)), the alignment with the inner lead becomes easier.
【００２０】この貫通孔に、電気伝導性の良好な金属ま
たは導電性樹脂（８）を充填し、導体部を形成する。A metal or a conductive resin (8) having a good electric conductivity is filled in the through hole to form a conductor portion.
【００２１】金属を充填する方法の一例として、電気メ
ッキで銅の導体部を形成する方法を説明する。As an example of a method of filling a metal, a method of forming a copper conductor portion by electroplating will be described.
【００２２】接着剤シートを陰極金属板であるステンレ
ス板上に密着させ、硫酸銅メッキ液中で、４Ａ／ｄｍ2
の条件で６０分間電解メッキを行った。ステンレス板の
露出した貫通孔の部分にメッキが析出し、孔が金属で充
填されることになる。メッキ後、ステンレス板から接着
剤シートをはがし、接続用部材が完成した。The adhesive sheet was brought into close contact with a stainless steel plate which is a cathode metal plate, and 4 A / dm 2 in a copper sulfate plating solution.
Electrolytic plating was carried out for 60 minutes under the conditions described above. Plating is deposited on the exposed through holes of the stainless steel plate, and the holes are filled with metal. After plating, the adhesive sheet was peeled off from the stainless plate to complete the connecting member.
【００２３】次に、図面を参照して本発明の実施例につ
いて説明する。本発明のリードフレームの製造方法で
は、貫通孔を成形後、インナーリード先端部にシート状
接着剤を貼り付け、図３に示すように、メッキマスク
（９）を用い、リードフレーム上に直接導体部を形成す
る。 Next, an embodiment of the present invention will be described with reference to the drawings.
And explain. In the lead frame manufacturing method of the present invention,
After forming the through-hole, a sheet-like adhesive is attached to the tip of the inner lead, and the conductor portion is directly formed on the lead frame using the plating mask (9) as shown in FIG.
It
【００２４】[0024]
【発明の効果】本発明のような接続用部材を用いたリー
ドフレームの製造方法で、インナーリード先端部と半導
体集積回路上に形成された電極とを接続することによ
り、使用するボンディング用キャピラリ（針）の外形に
依存し、インナーリードの平坦幅・隣接するボンディン
グ間距離が制約を受けることがなく、リードフレームの
多ピン化・狭ピッチ化、また、半導体集積回路上の多電
極化が可能となる。According to the lead frame manufacturing method using the connecting member of the present invention, the bonding capillaries to be used by connecting the tips of the inner leads to the electrodes formed on the semiconductor integrated circuit ( The flat width of the inner leads and the distance between adjacent bondings are not restricted by the outer shape of the (needle), and the lead frame can have multiple pins and pitches, and multiple electrodes on the semiconductor integrated circuit can be used. Becomes
【００２５】また、接続用部材の貫通孔形成加工にエキ
シマレーザーを用いることにより、微細加工は充分に可
能であり、メッキ等により、導体部は容易に形成でき
る。Further, by using an excimer laser for forming the through hole of the connecting member, fine processing can be sufficiently performed, and the conductor portion can be easily formed by plating or the like.
【００２６】さらに、本発明では、ワイヤボンディング
を必要としないため、ワイヤ不着という問題や、各種の
物理的負荷（加熱・加圧・超音波振動など）に起因する
半導体集積回路へのダメージの問題を回避でき、高信頼
性の半導体装置が提供される。Further, in the present invention, since wire bonding is not required, there is a problem of wire non-adhesion and a problem of damage to the semiconductor integrated circuit due to various physical loads (heating, pressurization, ultrasonic vibration, etc.). A highly reliable semiconductor device that can avoid the above problems is provided.
【００２７】[0027]
【図１】本発明の一実施例にかかる半導体装置を示す説
明図。FIG. 1 is an explanatory diagram showing a semiconductor device according to an embodiment of the present invention.
【図２】接続用部材の各種例を示す説明図。FIG. 2 is an explanatory view showing various examples of connecting members.
【図３】接続用部材の製造方法の一例を示す説明図。FIG. 3 is an explanatory view showing an example of a method for manufacturing a connecting member.
【図４】従来技術にかかる半導体装置を示す説明図。FIG. 4 is an explanatory diagram showing a semiconductor device according to a conventional technique.
１…インナーリード先端部分 ２…リードフレーム ３…接続用部材 ４…微小導体部 ５…半導体集積回路 ６…電極 ７…金属メッキ ８…導電性樹脂 ９…メッキマスク １０…スパージャノズル １１…高分子フィルム １２…メッキ液 １３…Ａｕワイヤ １４…貫通孔 1 ... Tip of inner lead 2 ... Lead frame 3 ... Connection member 4 ... Micro conductor part 5 ... Semiconductor integrated circuit 6 ... Electrode 7 ... Metal plating 8 ... Conductive resin 9 ... Plating mask 10 ... sparger nozzle 11 ... Polymer film 12 ... Plating liquid 13 ... Au wire 14 ... Through hole
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/50 H01L 21/60 311 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 23/50 H01L 21/60 311
Claims (2)
一方の面から反対の面まで貫通する複数の貫通孔を設け
る工程と、前記貫通孔がインナーリードのボンディング
領域に当接するように前記絶縁シートを接着する工程
と、メッキマスクを施す工程と、電気メッキにより貫通
孔を導電体で充填する工程よりなることを特徴とするリ
ードフレームの製造方法。 1. An insulating sheet having adhesiveness on both sides,
Providing multiple through holes from one surface to the other
And the through holes are bonded to the inner leads
Step of adhering the insulating sheet so as to abut the area
And the step of applying a plating mask and penetrating by electroplating
A process characterized by comprising the step of filling the holes with a conductor.
Method of manufacturing a frame.
一方の面から反対の面まで貫通する複数の貫通孔を設け
る工程と、前記貫通孔がインナーリードのボンディング
領域に当接するように前記絶縁シートを接着する工程
と、前記貫通孔及び前記絶縁シートの接着面とは反対側
の面を除き、メッキマスクを施す工程と、前記インナー
リードと前記絶縁シートの非接着面上の間を電気メッキ
し貫通孔を導電体で充填する工程よりなることを特徴と
するリードフレームの製造方法。 2. An insulating sheet having adhesiveness on both sides,
Providing multiple through holes from one surface to the other
And the through holes are bonded to the inner leads
Step of adhering the insulating sheet so as to abut the area
And the side opposite to the bonding surface of the through hole and the insulating sheet
Except for the surface of the
Electroplating between the lead and the non-bonded surface of the insulation sheet
It is characterized by comprising a step of filling the through hole with a conductor.
Method of manufacturing lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00435694A JP3401891B2 (en) | 1994-01-20 | 1994-01-20 | Lead frame manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00435694A JP3401891B2 (en) | 1994-01-20 | 1994-01-20 | Lead frame manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07211848A JPH07211848A (en) | 1995-08-11 |
| JP3401891B2 true JP3401891B2 (en) | 2003-04-28 |
Family
ID=11582126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP00435694A Expired - Fee Related JP3401891B2 (en) | 1994-01-20 | 1994-01-20 | Lead frame manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3401891B2 (en) |
-
1994
- 1994-01-20 JP JP00435694A patent/JP3401891B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07211848A (en) | 1995-08-11 |
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