JP3400838B2 - Background correction circuit of the document reading device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a background correction circuit in a document reading device such as an image scanner or a facsimile device.

[0002]

2. Description of the Related Art In a document reading device such as an image scanner or a facsimile device, background correction is performed in order to prevent the background of the original from becoming black when binarizing a document with a dark background such as a newspaper. .

As a correction method therefor, when using a correction format in which the degree of correction of the background correction is made to follow depending on the state of the image, either of the following is performed.

When the binarization threshold value is fixed, the image signal is 8
In the case of bits, the image signal is standardized so that the background image signal becomes ffH.

The image signal is not converted and the binarization threshold value is changed according to the density of the background.

First, the above will be described.

Usually, the background of a text original is brighter than the text, so the maximum value of the brightness of the original is considered to be the background of the original.
Taking an 8-bit image signal as an example, the brightness of the background is "25".
When the brightness is converted to 5 ", the background becomes white when binarized. Also, the brightness of the characters is usually sufficiently dark that the brightness does not exceed the binarization threshold even if the brightness is converted. Therefore, the character is blackened and binarized, and the background correction is performed.

At this time, the maximum value is detected for each main scanning line and the following correction calculation is performed.

(Corrected image signal) = (image signal) × 2
55 / (maximum value) (1) If formula (1) is calculated simply by using the maximum value of the original, it becomes easy to be affected by noise such as dust on the original, so the maximum after smoothing processing by moving average Use value.

Next, the above will be described.

In the above case, correction is performed so that a binarization threshold value is set between the brightness of the background of the document and the brightness of the characters.
When binarizing a normal original with a white background, the threshold Th is determined as follows.

[0012]         (Threshold Th) = 255 / C (2) C is a constant.

As in the above case, since the maximum value of the brightness of the original is considered to be the brightness of the background, the brightness of the background can be known by detecting the maximum value for each main scanning line.

Therefore, the background correction can be performed by correcting the value calculated by the equation (2) as shown in the equation (3).

(Corrected threshold value Th ') = Th / (maximum value) × 255 (3) As in the above case, if the maximum value of the original is simply used, it is easily affected by noise, and therefore the movement is made. The maximum value after smoothing with the average is used.

[0016]

However, the above correction equations (1) and (3) include multiplication and division, and the circuit scale becomes large in order to realize the background correction. Even if the 255 times of the above equations (1) and (3) are approximated to 256 times and the multiplication is performed by the scale, the division remains. Usually, the circuit scale of the divider is several times larger than that of the multiplier, so the cost increase is inevitable in any case.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a background correction circuit for a document reading apparatus which can suppress an increase in circuit size and reduce costs.

[0018]

In order to achieve the above object, the background correction circuit of the present invention uses a digital image signal (V
a shading correction circuit (4) for performing a calculation on a d) by a divider (45), and an image signal (V) after the shading correction.
In a document reading device having a scaling circuit (6) for performing a calculation by a multiplier (62) on d ′), a circuit (5) for detecting a background signal from a shading-corrected image signal, and the divider (6) 45), the background signal is input to the divider during the period for reading the dummy bit of the line sensor, and the correction parameter (C
A switch (44) for causing the divider (45) to calculate E),
The image signal (Vd ′) corrected by the shading correction circuit and the correction parameter (C) of the background correction are provided in the multiplier (62) before the effective pixel is read out.
A switch (63) for inputting E) and causing the multiplier (62) to multiply the two is provided (Claim 1).

In the present invention, the divider (45) causes the difference (Vd-V) between the image signal (Vd) and the black reference signal (Vb).
It can be a divider (45) that divides b) by the white reference signal Vw '(claim 2), and the multiplier can be an interpolator (62) (claim 3).

Further, a background correction circuit according to another embodiment of the present invention is a shading correction circuit (4) for performing an arithmetic operation on a digital image signal (Vd) by a divider (45), and an image signal after the shading correction ( In a document reading device having a circuit (7a) for comparing Vd ') with a threshold value (Th) and binarizing the circuit, a circuit (5) for detecting a background signal from a shading-corrected image signal, and the divider. Switched to input the background signal to the divider to cause the divider (45) to calculate the correction of the background correction threshold (Th) in the period before reading the dummy bit of the line sensor, which is preceded by (45). (44) and circuit means (48) for holding the corrected threshold value (Th ') obtained by the divider (45) for one main scanning line period and giving it to the binarization circuit (7a). And is provided (claim ).

The binarization circuit (7a) is a comparator (72).
And a switching device (71) disposed in front of the switching device (71), and when the background correction is performed, the corrected threshold value (Th ′) is passed through the switching device and given to the binarization circuit (7a). (Claim 5).

[0022]

The invention according to claim 1 belongs to the above-mentioned correction form. In this case, during the period of reading the dummy bit of the line sensor, the background signal of the background detection circuit (5) is input to the divider (45) of the shading correction circuit (4) through the switch (44), The divider (45)
Thus, the correction parameter (CE) for the background correction is calculated. Then, in the subsequent period for reading out effective pixels,
The corrected image signal (V
d ') and the correction parameter (CE) of the background correction are
It is input to the multiplier (62) of the enlargement / reduction circuit (6) through the switch (63), and the multiplier (62) multiplies both.

For example, the above equation (1) is divided into the form of the product of the division unit and the multiplication unit, and the former operation is performed by the divider (45) of the shading correction circuit (4) and the latter multiplication unit. Is calculated by the multiplier (62) of the scaling circuit (6).

As described above, according to the first aspect, the arithmetic circuit (divider, multiplier) for image processing used in the period for reading out the effective pixels of the line sensor is used for the period for reading out the pixels which are not the effective pixels of the line sensor. In this case, since it is used for calculation for another image processing (background correction), the calculation circuit is shared and an increase in circuit scale can be suppressed.

In the second and third aspects, the divider (4
5) is the difference (V) between the image signal (Vd) and the black reference signal (Vb).
Divider (45) that divides d-Vb) by the white reference signal Vw '
Alternatively, since the multiplier is an interpolator (62), a simpler configuration can be obtained.

The invention of claim 4 belongs to the above correction format. In the case of this background correction circuit, the switching device (4
The background signal of the background detection circuit (5) is input to the divider (45) of the shading correction circuit (4) through 4), and the threshold (Th) of the background correction is performed by the divider (45).
Is calculated. The threshold value (Th ') corrected by the divider (45) is held by the circuit means (48) for the period of one main scanning line and given to the binarization circuit (7a). The binarization circuit (7a) compares the image signal (Vd ') after shading correction with this threshold value (Th) and binarizes it.
Therefore, also in the fourth aspect, the arithmetic circuit can be shared, and the increase in circuit scale can be suppressed.

In claim 5, the binarization circuit (7a)
The comparator (72) is preceded by the switch (71), and when the background correction is performed, the corrected threshold value (Th ') is given to the binarization circuit (7a) through the switch. Therefore, a more practical and simple configuration can be obtained.

[0028]

The present invention will be described below with reference to the illustrated embodiments.

FIG. 1 shows a schematic structure of a document reading apparatus, in which 1 is a line sensor, 2 is an amplifier for amplifying the output of the line sensor, and 3 is an A / D for converting an analog signal into a digital signal. Converter 4, shading correction circuit, 5 background detection circuit, 6 scaling circuit, 7a
Is a binarization circuit, 7b is a 16-valued circuit, and 8 is a selector for selecting an image signal of a desired data length from among binary, 16-valued and multi-valued image signals. Reference numeral 10 is a register for holding various operation parameters of the document reading apparatus, which is written from the personal computer 12. Reference numeral 11 is an interface for communicating with a personal computer.

Reference numeral 100 denotes an original reading apparatus main body, which appropriately amplifies the output of the line sensor 1 by an amplifier 2 and converts an image signal into a digital signal by an A / D converter 3. The image signal converted into the digital value is subjected to shading correction by the shading correction circuit 4, and the size of the image is converted by the enlargement / reduction circuit 6 at a desired magnification. After that, the image signal is binarized by the binarization circuit 7a and 16-valued by the 16-value binarization circuit 7b, and the data of the desired output form is selected by the selector 8 from the binary, 16-value, and multi-value. Then, it is transferred from the interface 11 to the host personal computer 12. The image processing parameters are set in the register 10 by the personal computer 12. The memory (RAM) 9 stores reference data for shading correction and is used as a work area required for enlargement / reduction.

FIG. 2 shows a circuit configuration of the shading correction circuit 4, the background detection circuit 5, and the enlargement / reduction circuit 6. 3 and 4 are timing charts thereof. Note that the scaling circuit 6 is configured so that only the scaling operation is possible in order to simplify the timing chart of FIG. 4, but the configuration is not limited to this.

The shading correction circuit 4 produces a difference (Vd-Vb) between the image signal and the black reference signal by a subtractor (A-
B) 43 and this difference (Vd-Vb) as the white reference signal Vw '.
A divider (A / B) 45 that divides by and a clip circuit 46 that fixes the image signal to a predetermined value when the calculation result of shading correction overflows or underflows.
Have and. A switch 44 is placed in front of the divider 45, and the switch 44 is detected by the background detector 5 by the divider 45 during a period in which the dummy bit of the line sensor 1 is read. The background color signal is switched to the input, and the correction parameter (CE) for background correction is calculated by the divider 45.

The enlarging / reducing circuit 6 determines a position to be interpolated by linear interpolation and simultaneously outputs a signal for controlling sampling availability and linear interpolation [(1-P) Xn + PXn + 1]. And an interpolator 62 that outputs an interpolation value. “P” of the interpolator 62 is an interpolation coefficient having a value in the range of 0 ≦ P <1, and the interpolation coefficient P interpolates between two points Xn and Xn + 1. A switch 63 is placed in front of the interpolator 62, and during the period for reading out the effective pixels, the corrected image signal Vd ′ from the shading correction circuit 4 and the correction parameter for the background correction are passed through the switch 63. (CE) is input. And
The interpolator 62 is used as a multiplier in the period for reading out the effective pixels, and the multiplier (62) multiplies both.

For convenience of explanation, the function before adding the switch 44 and the switch 63 will be described below.

(1) Shading correction function Shading correction is performed by the following equation, where Vw is an image signal obtained when a white reference document is read and Vb is an image signal obtained when the illumination is turned off. The 8-bit digital image signal Vd is corrected to Vd '.

[0036]

[Equation 1] FIG. 5 shows a basic circuit of the shading correction circuit 4, and FIG. 6 shows a timing chart thereof. In FIG. 6, n indicates the number of the pixel in the main scanning line corresponding to the signal.

In FIG. 5, Vd is a digital image signal output from the A / D converter 3, and D is a data bus of the memory 9. PCLK is a clock (control signal) that transfers the image signal at the rising edge thereof in synchronism with the image signal, and WCLK is a clock for controlling the white component correction of the shading correction, and for controlling the division. used. Vb is a black reference signal used for shading correction, Vw 'is a white reference signal used for shading correction, and the Vb component is subtracted in advance. V
d'is an image signal that has been subjected to shading correction.

The data read from the memory 9 is loaded into the flip-flop 41 at the rising edge of the image signal transfer clock PCLK and used as the black reference signal Vb. Further, the data read from the memory 9 is loaded into the flip-flop 42 at the rising edge of the clock WCLK for white component correction control and used as the white reference signal Vw '. The white reference signal Vw 'is Vw' = Vw on the personal computer 12 side.
It is assumed that -Vb is calculated and written in the memory. Difference between image signal Vd and black reference signal Vb (Vd-Vb)
Is calculated by the subtractor 43 and is output in synchronization with the rising edge of the clock WCLK. The division between the difference Vd−Vb and the white reference signal Vw ′ is calculated in the divider 45,
It is output at the rising edge of the clock WCLK. At this time, the output signal is scaled by 256, and the above equation (4) is calculated. With respect to the result, as shown in the above equation (5), if "0 or less", "0" is applied, and if "256 or more", "255" is applied, and the shading correction ends. .

(2) Enlarging / Reducing Function Next, the basic function of the enlarging / reducing circuit 6 will be described. Here, in order to make it easy to understand, a case of enlarging / reducing only in the main scanning direction will be described as an example, and enlarging / reducing by theoretical linear interpolation will be described first.

The scaling using linear interpolation is to increase the number of data by interpolating the image signal output from the sensor by linear interpolation. In the example shown in FIG. 7, the data indicated by X is generated from the output data of the sensor indicated by O, and the number of data is increased four times. In order to enlarge or reduce, the data increased by the linear interpolation is sampled at the data interval according to the following equation (6).

(Sampling interval St) = a × 100 /
(Magnification [%]) (6) a in the equation (6) is a constant indicating how many times the data is increased by linear interpolation.

When reducing to 80%, in the example of FIG.
= 4, the sampling interval is "5" from the above equation (6). When the data is sampled at the sampling interval “5”, the data indicated by the arrow in FIG. 7 is selected and reduced to 80%. Further, if the sampling interval St is a (a = 4 in the case of FIG. 7), an image of the same size can be obtained. The constant a in the above equation (6) is determined in consideration of the accuracy of the enlargement / reduction ratio, the image quality, and the circuit scale.

FIG. 8 shows a circuit of the enlargement / reduction circuit 6 in which the switch 63 system is omitted. In the figure, P is a sampling counter 6
1 is a signal indicating a position (interpolation coefficient) to be interpolated by linear interpolation, and F is valid data output by the interpolator.
A signal indicating invalidity, Vs', is an enlarged or reduced image signal. PCLK2 is a signal having a frequency twice that of PCLK, and the rising edge of PCLK2 is synchronized with the rising edge of PCLK.

The sampling counter 61 is a counter for determining a position (hereinafter referred to as an interpolation coefficient) P to be interpolated by linear interpolation, and if it can be expanded to 200%, once or twice for each pixel, the following ( 7) Output as in equation (8). At the same time, the flag F indicating whether or not sampling is possible is output as in the following equations (9) and (10). If sampling is possible with the first output in one pixel, then Pn
Although the state of Fn changes, if sampling cannot be performed for the first time, Pn and Fn maintain the same state until the next pixel.
The flag F indicates that sampling is performed when it is zero.

[0045]

[Equation 2] The subscript n indicates the pixel number, and the operator% indicates the remainder of division.

The interpolated coefficient P is used to perform linear interpolation as follows to calculate the scaled image signal Vs.

Vs = (1-Pn / a) × Vd'n +
Pn / a × Vd′n + 1 (11) A timing chart is shown in FIG. In FIG. 9, Fn
Indicates the validity / invalidity of the nth pixel.

Shading-corrected image signal Vd '
Flip-flop 6 at the rising edge of PCLK
Two image signals loaded with 0 and shifted by one pixel are input to the interpolator 63 as Xn and Xn + 1. In addition, the sampling counter 61 outputs a signal PCLK2 having a frequency twice that of PCLK.
Transition to the next state at the rising edge of, the output interpolation coefficient is also input to the interpolator 62, linear interpolation is calculated in the interpolator 62, and the result is loaded into the flip-flop 67 at the rising edge of PCLK2. It Further, the sampling flag is loaded into the flip-flop 68 at the rising edge of PCLK2 and indicates whether or not the data loaded into the flip-flop 67 is valid. Above (1
The interpolation coefficient is obtained by dividing the sampling position Pn by the constant a in the equation (1). However, if the constant a is set to a power of 2, division is performed by the scale of the output of the interpolator 62. The increase can be suppressed.

(3) Background Correction Function A method for realizing the background correction function in the document reading apparatus having the above-described configuration without increasing the circuit scale will be described below.

Returning to FIG. 2, the correction equations (1) and (3) include division. The divider 45 is used for shading correction by digital operation, but normally, since division requires more calculation time than other four arithmetic operations,
When a valid image signal is being read, it is difficult to use it for a plurality of purposes in a time-division manner, especially in a document reading apparatus that requires high speed.

However, a line sensor is usually used in the document reading apparatus, and the line sensor is provided with dummy bits whose signal level is not guaranteed on the reading start side and the reading side.

Therefore, the period for reading the dummy bit is
Paying attention to not performing image reading, the arithmetic circuit used for shading correction during this period is used for background correction to suppress an increase in circuit scale.

First, an example of background correction based on the correction formula (1) will be described.

The calculation of the correction formula (1) described above is performed as follows.
Divide into stages.

(Correction coefficient CE) = 255 / (maximum value) (12) (corrected image signal) = (image signal) × (correction coefficient CE) (13) During the period for reading the dummy bit, (12) ) Is calculated using the divider 45 used for shading correction, and the calculation of (13) above is performed using the time-division scaling interpolator 62 during the period in which effective pixels are read. Divider 45
In the interpolator 62, if the number of input bits is the same, the normal interpolator 62 is three times or more faster, and the time division operation is possible during the effective pixel reading.

The operation of the interpolator 62 is (output) = (1−P) Xn + PXn + 1 (14) However, since 0 ≦ P <1, it is set to “0” at the input terminal Xn of the interpolator. Since it is a multiplier, the correction coefficient CE is applied to the input terminal P.
When an image signal is input to the input terminal Xn + 1,
Since the normal multiplication can be calculated with, the corrected image signal is obtained as an output.

In FIG. 2, a switch 44 and a switch 63 are provided in order to perform the calculations of the equations (12) and (13). The block 6 is configured so that only the reduction operation is possible in order to simplify the timing chart of FIG.

When the control signal PX is at the H level, it indicates that the read-out effective pixel of the line sensor is being read out. Shading correction circuit 4 when PX is at H level
Performs shading correction.

The data D read from the memory 9 is flip-flop 41 at the rising edge of the clock PCLK.
To the black reference signal Vb. Also, the clock W
At the rising edge of CLK, the data read from the memory is loaded into the flip-flop 42, and the white reference signal V
w '. In addition, Vw '= Vw-V on the personal computer 12 side
It is assumed that b is calculated and written in the memory 9. The subtractor 43 calculates the difference between the image signal Vd and the black reference signal Vb, and outputs the difference in synchronization with the rising edge of WCLK.

The switch 44 outputs the input signal on the A side to the output terminals C0 and C1 when the input terminal S is at the H level, and outputs the input signal on the B side when the input terminal S is at the L level.
Output to C1.

Since the control signal PX is at the H level, the difference signal (Vd-Vb) between the image signal on the A side and the black reference signal,
The switch 44 outputs the white reference signal Vw ′. Difference Vd
The division between −Vb and the white reference signal Vw ′ is the divider 45.
And is output at the rising edge of WCLK. At this time, it is multiplied by 256 depending on the scale of the output signal,
The formula is calculated. As shown in the above equation (5), if the value is "0 or less", the value "0" is processed, and if the value is "256 or more", the value is changed to "255". Is loaded into the flip-flop 47 at the rising edge of PCLK, and the shading correction for one pixel is completed.

When PX is at L level, the switch 44 outputs the input signal on the B side. A fixed value of "255" and an image signal corresponding to the background output from the background detection circuit 5 are input to the B side, and the divider 45 outputs the correction coefficient C of the above equation (12).
Output E. As shown in FIG. 3, the correction coefficient CE is the timing at which the signal read from the line sensor 1 becomes effective,
That is, at the rising edge where PX becomes H level, it is loaded into the flip-flop 48 and held for one main scanning line period.

Next, in the reduction circuit 6, the shading-corrected image signal Vd 'and the correction coefficient CE for the background correction.
Based on the above, the background correction is first performed according to the above equation (13), and then the reduction is performed. In order to use one interpolator 62 for two calculations of the background correction and the reduction, the interpolator 62 is switched by the switching unit 63 and used in a time division manner.

A timing chart of the reduction circuit is shown in FIG.

A switch 63 for switching the input of the interpolator 62
Has a structure of 6 inputs and 3 outputs. If the input terminal S is at L level, the A side is output, and if the input terminal S is at H level, the B side input is output. The clock PCLK line is connected to the input terminal S, the interpolator 62 performs background correction calculation while PCLK is at the H level, and the scaling calculation is performed while PCLK is at the L level.

The background correction calculation result Y is loaded into the flip-flop 64 at the falling edge of PCLK, and its output is loaded into the flip-flop 65 at the rising edge of PCLK. The flip-flop 65 is PCL
The background-corrected image data Va synchronized with K is held,
The flip-flop 66 holds the signal delayed by one pixel for the linear interpolation calculation.

During the period in which the clock PCLK is L, the interpolator 62
The scaled image signal Vs calculated by
It is loaded into flip-flop 67 on the rising edge of CLK. The sampling flag Fn output from the sampling counter 61 is loaded into the flip-flop 68 at the rising edge of PCLK to indicate whether the image signal held by the flip-flop 67 is valid.

According to the above-described embodiment, the original reading apparatus having the divider 45 and the multiplier 62 is configured to calculate the correction parameter for the background correction during the period for reading the dummy bit of the line sensor. As the correction calculation circuit, the shading correction and scaling calculation circuit can be shared, and an increase in the circuit scale can be suppressed.

(4) Other Embodiments An embodiment of background correction based on the correction equation (2) described above will be shown.

By approximating the above equation (2),       (Corrected threshold Th ′) = Th / (maximum value) × 256 (15) And

While the dummy bit of the line sensor 1 is being read, the above equation (15) is calculated using the shading correction divider 45, and after reading the effective pixel, the result of equation (15) is set to the threshold value. The image signal is binarized as.

FIG. 1 shows a configuration in which the background is corrected and binarized.
It shows in 0. Further, FIG. 11 shows a timing chart for performing the correction calculation of the binarization threshold during the period of reading the dummy bit.

The shading correction circuit 4 corrects the binarization threshold value as shown in the above expression (15) during the period for reading the dummy bit of the line sensor 1.

When the control signal PX is at H level, the shading correction circuit 4 executes shading correction.

When the control signal PX is at L level, the switch 4
4 outputs the input signal on the B side. Unlike the case of FIG. 2, the threshold value Th for binarization and the background signal output by the background detection circuit 5 are input to the B side input of the switch 44, and the divider 45 uses the equation (15) above. Is calculated, and the corrected threshold value Th ′ for binarization is output. The corrected binarization threshold Th ′ is a flip-flop 4 as a holding means at the timing when the signal read from the line sensor 1 becomes effective, that is, at the rising edge when the control signal PX becomes H level.
8 and is held for one main scan line period. The corrected binarization threshold Th ′ from the flip-flop 48 serving as the holding unit is input to the binarization circuit 7a.

On the other hand, while the control signal PX is at the H level, the shading-corrected image signal Vd 'becomes the image signal Vs converted into a desired image size by the enlarging / reducing circuit 6, and is input to the binarizing circuit 7a. It

The binarization circuit 7a comprises a switch 71 for selecting the threshold values Th and Th ', and a comparator 72 for binarization. The switch 71 has a configuration that outputs the B-side input when the input terminal S is at the H level and outputs the A-side input when the input terminal S is at the L level. Then, to the input terminal S, the control signal ABG that is at the H level when the background correction is performed is input.

When the background correction is performed, the control signal ABG is H
Since it is a level, the switching unit 71 has the corrected threshold value T on the B side.
Output h '. The comparator 72 compares the corrected threshold value Th ′ with the scaled image signal Vs, and if the image signal Vs is greater than or equal to the threshold value Th ′, an H level signal (binarized signal).
Output Vbin. At the same time, the enlarging / reducing circuit 6 outputs a signal F indicating whether or not the binarized signal Vbin is valid.

[0079]

In summary, according to the present invention, the following excellent effects can be obtained.

(1) According to the first aspect, in the document reading apparatus having the divider and the multiplier, the correction parameter of the background correction is calculated during the period of reading the dummy bit of the line sensor. A shading correction and scaling operation circuit can be shared as a background correction operation circuit, and an increase in circuit scale can be suppressed.

(2) According to claims 2 and 3, a concrete and simple structure can be obtained.

(3) According to the fourth aspect, since the threshold value which is the correction parameter of the background correction is calculated during the period of reading the dummy bit of the line sensor, the arithmetic circuit for the background correction performs the shading correction. It is possible to share the arithmetic circuit, and it is possible to suppress an increase in circuit scale.

(4) According to claim 5, a more practical and simple structure can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a document reading apparatus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a background correction circuit according to an embodiment of the present invention.

FIG. 3 is a timing chart when a shading correction circuit calculates a correction coefficient for background correction.

FIG. 4 is a timing chart when the background correction is performed by the scaling circuit.

FIG. 5 is a block diagram of a shading correction circuit by digital calculation.

FIG. 6 is a timing chart of a shading correction circuit by digital calculation.

FIG. 7 is a principle diagram of scaling by linear interpolation.

FIG. 8 is a block diagram of a scaling circuit.

FIG. 9 is a timing chart of the scaling circuit.

FIG. 10 is a configuration diagram showing a background correction circuit according to another embodiment of the present invention.

FIG. 11 is a timing chart when the corrected binarization threshold is calculated by a shading circuit when the binarization threshold is corrected by background correction.

[Explanation of symbols]

1 line sensor 2 amplifier 3 A / D converter 4 shading correction circuit 5 background detection circuit 6 enlargement / reduction circuit 7a binarization circuit 7b 16 digitization circuit 8 selector (switch) 9 memory (RAM) 10 register 11 interface 12 personal computer 41 flip-flop 42 flip-flop 43 subtractor 44 switcher 45 divider 46 clip circuit 47 flip-flop 48 flip-flop 60 flip-flop 61 sampling counter 62 interpolator (multiplier) 63 switcher 64 flip-flop 65 flip-flop 66 flip-flop 67 Flip-flop 68 Flip-flop 71 Switching device 72 Comparator 100 Document reading device main body a Constant ABG indicating how many times the data is increased by linear interpolation ABG Control signal C for performing background correction C Constant C Correction coefficient D Data bus F of memory F Signal P indicating valid / invalid of interpolator output data P Interpolation coefficient (0 ≦ P <1) Pn Sampling position PCLK Image signal transfer clock PCLK2 Signal PX having a frequency twice that of PCLK Control signal (valid Pixel reading) St Sampling interval Th Threshold for binarization Th 'Corrected threshold WCLK Clock for white component correction control Va Image data Vbin binarized signal Vb bin reference signal Vd Black reference signal Vd Digital image signal Vd' Image signal after shading correction Vs Enlarged / reduced image signal Vw Image signal Vw ′ obtained when a white reference document is read White reference signal Y Calculation result of background correction

Claims (5)

(57) [Claims] 1. A divider (4) for the digital image signal (Vd).
In a document reading apparatus having a shading correction circuit (4) for performing an operation in 5) and an enlargement / reduction circuit (6) for performing an operation in a multiplier (62) on the image signal (Vd ′) after the shading correction, shading A circuit (5) for detecting a background signal from the corrected image signal and the divider (45) before the background signal are input to the divider while the dummy bit of the line sensor is read out. Then, the shading correction circuit is placed in front of the switch (44) for causing the divider (45) to calculate the correction parameter (CE) of the background correction and the multiplier (62) and for reading the effective pixel. The corrected image signal (Vd ') and the correction parameter (C
A background correction circuit comprising a switch (63) for inputting E) and causing the multiplier (62) to perform a multiplication of both. 2. A divider (45) calculates a difference (Vd-Vb) between an image signal (Vd) and a black reference signal (Vb) as a white reference signal V.
The background correction circuit according to claim 1, wherein the background correction circuit is a divider (45) that divides by w '. 3. The background correction circuit according to claim 1, wherein the multiplier is an interpolator (62). 4. A divider (4) for the digital image signal (Vd).
The shading correction circuit (4) that performs the calculation in 5) and the image signal (Vd ′) after the shading correction are set to the threshold value (T).
In a document reading device having a circuit (7a) for binarizing the image signal in comparison with (h), a circuit (5) for detecting a background signal from a shading-corrected image signal, and a front side of the divider (45). During the period in which the dummy bit of the line sensor is read, the background signal is input to the divider to correct the background correction threshold (Th) by the divider (4
5) the switch (44) to be operated and the corrected threshold value (T) obtained by the divider (45).
h ') is held for one main scanning line, and the binarization circuit (7
and a circuit means (48) for giving to (a); 5. The binarization circuit (7a) is a comparator (72).
And a switching device (71) placed in front of the switching device (71), the switching device performing the background correction, the corrected threshold value (Th ′).
5. The background correction circuit according to claim 4, wherein the background correction circuit is applied to the binarization circuit (7a) through