JP3398524B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device which can suppress interwiring capacitance by forming a cavity between wirings of the semiconductor device. The present invention relates to a manufacturing method.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of elements of semiconductor integrated circuits, the distance between wirings connecting between elements has narrowed. For this reason, the problem that the capacitance between the wirings increases and the signal propagation speed decreases is becoming apparent.

For this reason, various measures have been taken to reduce the inter-wiring capacitance in the formation of the wiring and the insulating film between the wirings. As one example thereof, Japanese Patent Laid-Open No. 5-2161
Japanese Laid-Open Patent Publication No. 7-74 discloses a method of forming a cavity between wirings in order to reduce the capacitance between the wirings. Generally, a silicon oxide film having a relative dielectric constant of about 3.5 to 4.0 or a silicon nitride film having a relative dielectric constant of about 7 to 10 is used for insulation between wirings. Therefore, in this example, in order to reduce the capacitance, the wirings are insulated from each other by the cavity having the relative dielectric constant of about 1.

Next, a method for forming a cavity between the wirings will be described. As shown in FIG. 17, a silicon oxide film 2 is formed on the semiconductor substrate 1, and aluminum wirings 3 a and 3 b are formed on the silicon oxide film 2. Next, a silicon oxide film 4 is formed so as to cover the aluminum wirings 3a and 3b.
After applying the SOG (Spin-On-Glass) film 5, 40
Tighten at 0 ° C.

Next, as shown in FIG. 18, the SOG film 5 is etched back to expose the surface of the silicon oxide film 4 on the aluminum wirings 3a and 3b.

Then, as shown in FIG. 19, a silicon oxide film 6 is further formed on the entire surface, and an opening 6a is formed in the silicon oxide film 6 between the aluminum wirings so that the surface of the SOG film 5 is exposed by a predetermined mask. To form.

Further, as shown in FIG. 20, a silicon oxide film having a predetermined thickness is formed on the entire surface, and the silicon oxide film side wall 7 is formed by anisotropic etching. The width of the opening 6a is further narrowed by the side wall 7 of the silicon oxide film.

Next, as shown in FIG. 21, a hydrofluoric acid solution, for example, is introduced from the opening 6a to form the silicon oxide films 4, 6, and 7.
Then, only the SOG film 5 is selectively removed by etching. In this way, the cavity 8 is formed between the aluminum wirings 3a and 3b.

As shown in FIG. 22, a silicon oxide film 9 is further deposited on the silicon oxide film 6 to close the opening 6a,
Form a closed cavity 8a.

Next, as shown in FIG. 23, an SOG film 10 is formed on the silicon oxide film 9. As described above, a cavity is formed between the wiring.

In general, the metal wiring is formed in the minimum design size in order to cope with high integration. Therefore, in order to form the opening 6a between the wirings, the opening is formed in the side wall of the opening 6a. It is necessary to form a side wall for narrowing the width.

[0012]

As described above,
When forming a cavity between wirings, the opening width is usually narrower than the wiring interval formed with the minimum design dimension. It is necessary to reduce the hole width. Therefore, there is a problem that the number of sidewall forming steps is increased.

Alternatively, when the opening width is formed with the minimum design dimension in order to omit the side wall forming step, it is necessary to widen the wiring interval, so that the area of the semiconductor device is widened and the number of chips in the wafer is reduced. .

According to the present invention, since the cavity is formed between the wirings, the step of forming the side wall in the opening portion is not added, and the area of the semiconductor device is not widened. Part is formed, an etchant is introduced from the opening to selectively remove the inter-wiring film, and the opening is closed to form a cavity between the wirings, resulting in a small inter-wiring capacitance and high-speed operation. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain the semiconductor device according to the present invention.

[0015]

According to the method of manufacturing a semiconductor device of the first aspect for achieving the above object, an insulating film is formed on the main surface of a semiconductor substrate. A plurality of wirings arranged at a predetermined interval are formed on the insulating film. An inter-wiring film having etching characteristics different from those of the insulating film is formed on the insulating film so as to fill the space between the wirings. A first interlayer film having an etching characteristic different from that of the inter-wiring film is formed on the wiring and the inter-wiring film. An opening is formed in the first interlayer film so that a part of the wiring surface and a part of the inter-wiring film surface are continuously exposed through the boundary between the wiring and the inter-wiring film. The inter-wiring film is selectively etched and removed from the opening portion under etching conditions in which the etching rate of the inter-wiring film is faster than the etching rates of the first interlayer film and the insulating film. A cavity is formed in the area surrounded by the film. A second interlayer film is formed on the first interlayer film including a part of the surface of the wiring and a part of the surface of the inter-wiring film which are continuously exposed through the boundary portion to close the opening.

Therefore, unlike the prior art, there is no need to add a step of forming a hole on the inter-wiring film with a minimum design dimension to further narrow the opening portion, and without widening the wiring interval, A portion of the surface of the mesentery can be exposed. Further, even if the mask displacement of the opening portion occurs, the displacement is equal to or smaller than the minimum design dimension, so that the surface of the inter-wiring film can be accurately exposed.

Then, after selectively removing the inter-wiring film from a part of the surface of the inter-wiring film by etching, the opening is closed to be surrounded by the wiring, the insulating film and the first interlayer film. Since the cavity is formed in the region, the inter-wiring capacitance can be reduced.

According to the method of manufacturing a semiconductor device of the second aspect of the present invention, a part of the surface of the inter-wiring film located on both sides of the wiring and a part of the wiring surface are continuous through the boundary portion. Then, an opening is formed in the first interlayer film so as to be exposed.

Therefore, the surface of the inter-wiring film for selectively etching the inter-wiring film by opening a hole having a size larger than the width of the wiring without adding a step of narrowing the opening is formed. Can be exposed. Further, since the surfaces of the inter-wiring films on both sides of the wiring are sandwiched in one opening, the inter-wiring films can be efficiently and selectively removed by etching.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described step by step with reference to the drawings. As shown in FIG. 1, the semiconductor substrate 1
Of the gate electrode 10 on the memory cell portion 101 on the main surface of
And a capacitor lower electrode 106 and a capacitor upper electrode 1 connected to the transistor.
After forming a semiconductor element including a capacitor having 07 and forming peripheral circuit elements (not shown) in the peripheral circuit section 102, a silicon oxide film 110 is formed by a low pressure chemical vapor deposition method so as to cover these elements. Form. Then, the first metal wiring 111 is formed.

Next, as shown in FIG. 2, a silicon nitride film 112 is formed as an inter-wiring film on the silicon oxide film 110 and the first metal wiring 111. Then, as shown in FIG. 3, the silicon nitride film 112 is etched back to expose the upper surface of the first metal wiring 111, and the first metal wiring 111 is exposed.
The silicon nitride film 112 is left only between the metal wirings 111.

Further, as shown in FIG. 4, a silicon oxide film 114 is formed on the upper surface of the first metal wiring 111 and the silicon nitride film 112. The film thickness of the silicon oxide film 114 is preferably 5000 Å or less because it is necessary to reduce the step difference of the base in order to favorably perform photolithography when forming the second metal wiring in a later step.

Then, as shown in FIG. 5, an opening is formed in the silicon oxide film 114 so that a part of the surface of the silicon nitride film and a part of the surface of the wiring are continuously exposed through the boundary part 102. 115 is formed. 13 or 14 is a top view of the opening 115. FIG. 5 shows A-
A sectional view taken along line A'or BB 'is shown. The width of the exposed part 121 of the silicon nitride film 112 is 1
It is preferably μm or less. The length in the wiring direction may be any length.

Next, as shown in FIG. 6, by introducing phosphoric acid as an etchant through the opening 115, a part 121 of the surface of the silicon nitride film 112 is etched and the silicon nitride film 112 is gradually removed. To be done.

This is a silicon nitride film 1 for phosphoric acid.
12 has an etching rate of silicon oxide films 114 and 110.
Of the silicon oxide film 114, 1 because the etching rate of the first metal wiring 111 is higher than that of the first metal wiring 111.
This is because the silicon nitride film 112 can be etched while leaving 10 and the first metal wiring 111.

In this way, the cavity 117 can be formed in the region surrounded by the first metal wiring 111 and the silicon oxide films 114 and 110.

Thereafter, as shown in FIG. 7, a silicon oxide film 119 is further deposited on the silicon oxide film 114.
The silicon oxide film 11 is partially formed in the vicinity of the fine opening 121a.
9 is filled with silicon oxide film 119, but while the silicon oxide film 119 is being deposited, the silicon oxide film 114 in the vicinity of the fine opening 121a and the silicon oxide film 119 gradually deposited on the first wiring 111 closes the silicon oxide film 119 from both sides. Once filled, it will not be filled any further.

After forming the silicon oxide film 119, the first
A through hole 116 for connecting to the wiring is formed. Then, as shown in FIG.
A second metal wiring 118 is formed on top.

Next, a second embodiment will be described. Figure 1
Up to the above, it is the same as that of the first embodiment. Next, as shown in FIG. 9, TEOS (Tetra-Ethyl-Ortho-Si) is formed on the silicon oxide film 110 and the first metal wiring 111 by atmospheric pressure chemical vapor deposition or plasma chemical vapor deposition.
licateglass) type silicon oxide film 113 is formed. The TEOS-based silicon oxide film 113 may be a TEOS-based BPSG film containing boron and phosphorus as impurities.

Thereafter, as shown in FIG. 10, the TEOS based silicon oxide film 113 is etched back to expose the upper surface of the first metal wiring 111, and the TEOS based silicon oxide film is provided only between the first metal wirings. Leave 113.

Next, as shown in FIG. 11, the upper surface of the first metal wiring 111 and the TEOS type silicon oxide film 113.
A silicon oxide film 114 is formed thereon by plasma-enhanced chemical vapor deposition. The film thickness of the silicon oxide film 114 is preferably 5000 Å or less for the same reason as in the first embodiment.

Then, as shown in FIG. 12, a part of the surface of the TEOS-based silicon oxide film and a part of the surface of the wiring are exposed in the silicon oxide film 114 so as to be continuously exposed through the boundary portion 120. The hole 115 is formed. The shape and width of the opening 115 are the same as those in the first embodiment.

Next, as shown in FIG. 6, a part of the surface 12 of the TEOS type silicon oxide film 113 is introduced by introducing hydrofluoric acid vapor as an etchant through the opening 115.
1 is etched to form a TEOS-based silicon oxide film 113
Are removed.

This is because the etching rate of the TEOS type silicon oxide film 113 with respect to the vapor of hydrofluoric acid is higher than the etching rate of the silicon oxide films 114 and 110, and the first metal wiring 111 is not etched by the vapor of hydrofluoric acid. As a result, the silicon oxide films 114 and 110
This is because the TEOS-based silicon oxide film 112 can be etched while leaving the first metal wiring 111.

In this way, the cavity 117 can be formed in the region surrounded by the first metal wiring 111 and the silicon oxide films 114 and 110.

In the subsequent steps, as described in the first embodiment, as shown in FIG. 7, the silicon oxide film 119 is formed.
Is deposited to close the opening 115 and a second metal wiring 118 is formed on the silicon oxide film 119, as shown in FIG.

In the first embodiment, the insulating film 11 is used.
0 and 114 are silicon oxide films, the inter-wiring film 112 is a silicon nitride film, and the etchant is phosphoric acid.
In the embodiment described above, the insulating films 110 and 114 are silicon oxide films, the inter-wiring film 113 is a TEOS-based oxide film, and the etchant is hydrofluoric acid vapor. However, the etching rate of the inter-wiring film 112 is higher than that of the etchant. Is the insulating film 11
As long as the material is faster than 0 or 114, the material is not limited to the above example and can be applied.

The top surface shape of the opening 115 may be the shape shown in FIG. 15 or 16 in addition to the top surface shape as shown in FIG. 13 or 14, and the surface of the first metal wiring 111 may be formed. In the first embodiment or the second embodiment, as long as it is an opening portion that exposes a part of the above and a part of the surface of the silicon oxide film 112 continuously through the boundary portion 120. The method can form a cavity between the first wirings.

As described above, according to the method for manufacturing a semiconductor device of the present invention, the opening for introducing the etchant into the inter-wiring film between the wirings is not restricted to the minimum design size, and the opening is not restricted. It can be easily formed without adding an extra step of reducing the width.

Further, by introducing an etchant through the opening, the inter-wiring film between the wirings is selectively etched, and by closing the opening, a cavity is formed, and the inter-wiring capacitance is low and high speed operation is possible. It is possible to obtain a possible semiconductor device.

As described above, the embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the scope described above but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0042]

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, the opening for selectively etching the interwiring film is provided with a boundary portion from a part of the surface of the interwiring film. Since it is formed so as to be continuously exposed to a part of the surface of the wiring through the, it is not necessary to add a step of narrowing the opening portion or to widen the wiring interval. Further, even if the aperture portion is displaced due to the mask displacement, the displacement is equal to or smaller than the minimum design dimension, so that the surface of the inter-wiring film can be exposed with high accuracy.
Then, after selectively removing the inter-wiring film from a part of the surface of the inter-wiring film by etching, the opening portion is closed, and the inter-wiring capacitance can be reduced by forming a cavity between the wirings. A reduction in speed of the semiconductor device can be suppressed, and a semiconductor device that operates stably can be provided.

Further, in the manufacturing method according to the second aspect of the invention, such an opening is formed so as to expose a part of the surface of the inter-wiring film located on both sides of the wiring with the wiring interposed therebetween, so that it is efficient. The inter-wiring film can be removed by etching. After that, a void can be formed between the wirings and the capacitance between the wirings can be reduced, so that it is possible to provide a highly stable semiconductor device in which the speed reduction of the semiconductor device is suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG.

5 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 8 is a sectional view of a semiconductor device obtained through the steps of FIGS.

FIG. 9 is a cross-sectional view showing a step of a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG.

12 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 13 is a top view showing a first example of the shape of the opening according to the first or second embodiment of the invention.

FIG. 14 is a top view showing a second example of the shape of the opening according to the first or second embodiment of the invention.

FIG. 15 is a top view showing a third example of the shape of the opening according to the first or second embodiment of the invention.

FIG. 16 is a top view showing a fourth example of the shape of the opening according to the first or second embodiment of the invention.

FIG. 17 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17.

FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG.

21 is a cross-sectional view showing a step performed after the step shown in FIG.

22 is a cross-sectional view showing a step performed after the step shown in FIG.

FIG. 23 is a cross-sectional view of a semiconductor device obtained through the steps of FIGS.

[Explanation of symbols]

111 first metal wiring, 112 silicon nitride film, 1
13 TEOS-based silicon oxide film, 114 silicon oxide film, 115, 116 apertures, 117 cavities, 118
Second metal wiring, 119 silicon oxide film, 120
Boundary part, 121 Part of the surface of the silicon nitride film, 122
A part of the surface of the TEOS-based silicon oxide film, 121a fine opening.

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (2)

(57) [Claims] 1. A step of forming an insulating film on a main surface of a semiconductor substrate, a step of forming a plurality of wirings arranged at a predetermined interval on the insulating film, and a step of forming on the insulating film. A step of forming an inter-wiring film having an etching characteristic different from that of the insulating film so as to fill a space between the wirings; and a first etching characteristic different from that of the inter-wiring film on the wiring and the inter-wiring film. And a step of forming a part of the surface of the wiring and a part of the surface of the inter-wiring film through the boundary between the wiring and the inter-wiring film. The step of forming an opening in the interlayer film; and the step of forming an opening in the opening between the wiring film by an etching condition in which the etching rate of the wiring film is faster than the etching rates of the first interlayer film and the insulating film. Is selectively removed by etching, A step of forming a cavity in a region surrounded by a line, the insulating film and the first interlayer film, and a part of the wiring surface and the inter-wiring film surface which are continuously exposed through the boundary portion. And a step of forming a second interlayer film on the first interlayer film including a part of the first interlayer film to close the opening portion. 2. The first interlayer so that a part of the surface of the inter-wiring film and a part of the wiring surface located on both sides of the wiring are continuously exposed through the boundary portion. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming an opening in the film.