JP2861918B2 - MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a MOS type semiconductor device, and more particularly to an arrangement of transistors on a semiconductor substrate.

[0002]

2. Description of the Related Art In a conventional MOS type semiconductor device, elements such as a transistor and a capacitor are formed on a semiconductor substrate and are connected to each other by a metal wiring such as aluminum to realize a desired circuit.

In the case of a semiconductor device using a MOS transistor, the capacitor also has a MOS structure, and one electrode of the capacitor is formed simultaneously with the gate electrode of the MOS transistor. This will be described below with reference to the drawings. FIG. 3 (a),
2B is a plan view of a conventional semiconductor device and a cross-sectional view taken along line AA of FIG.

In FIGS. 3A and 3B, after a field oxide film 5 for element isolation is formed on a semiconductor substrate 4 using a normal LOCO technique, an impurity region 3B of a MOS capacitor 10 is formed. And then the MOS transistor Q3
A and Q3B gate oxide films 6 are formed. At this time, the gate oxide film 6 is also used as a capacitance insulating film of the MOS capacitor 10 at the same time. Next, after a polycrystalline silicon film is formed on the entire surface, unnecessary portions are removed by etching using a normal lithography technique to form the gate electrodes 2E and 2F and the electrode 1B of the MOS capacitor 10 at the same time. Then, impurity ions are implanted to form an impurity region 3 serving as a source / drain of the transistor. At this time, the impurity region 3B serving as the other electrode of the capacitor may be formed at the same time. Thereafter, although not shown, an insulating film is formed by a known method for manufacturing a semiconductor device, and the insulating film on the gate electrode and the source / drain is partially opened to form a wiring for connection. At this time, wiring is similarly formed for both electrodes of the capacitor.

[0005]

SUMMARY OF THE INVENTION The conventional MOS described above
In the method of manufacturing a semiconductor device, when an electrode area of a MOS capacitor is extremely large, a MOS
Finished dimensions of transistor gate electrode and MOS
A problem arises in that the finished dimensions of the gate electrode of the MOS transistor located away from the capacitance are different.

In general, in an etching step in forming a wiring layer pattern, the photoresist film slightly reacts with an etching gas to etch the photoresist film, and at the same time, the reaction product is etched into the wiring layer. Has an effect of increasing the anisotropy at the time of etching the wiring layer by adhering to the side wall of the wiring layer.

However, when there is a large-area capacitor, there is almost no portion to be etched, and there is a region with a high density of remaining patterns, a small amount of reaction product adheres to the side wall of the polycrystalline silicon layer during etching. Therefore, in the vicinity of this region, the anisotropy is weakened, and the wiring layer to be etched becomes thinner than the original dimensions. For example, FIG.
In the cases (a) and (b), the finished size of the gate electrode 2F of the MOS transistor Q3B, which is arranged close to the MOS capacitor 10, is smaller than the finished size of the gate electrode 2E of the MOS transistor Q3A. Further, the state of the replacement of the etching gas is also affected by the pattern density, which causes a variation in the finished dimensions.

According to a study by the inventor, for example, in a typical gate electrode of a 16 MDRAM, the area is 1 area.
In a gate electrode located at a distance of several tens of μm from a capacitance larger than 0000 μm ^2, a dimensional change of about 0.02 to 0.05 μm was confirmed. This value corresponds to 2.5 to 8% of the channel length of the transistor.

As an adverse effect due to such a change in the finished size of the gate electrode, the threshold voltage changes, which deteriorates the circuit operation margin and lowers the reliability. When the change in the channel length is converted into a threshold voltage, 0.02
乃至 0.06V. In addition, when the manufacturing conditions are changed, the amount of the change may further increase. For this reason, the above-described difference in characteristics occurs between a transistor located far from the capacitor electrode and a transistor disposed immediately near the capacitor electrode. In a normal circuit, such a difference in characteristics does not have much effect. However, in a circuit such as a differential amplifier circuit in which the symmetry of the performance of a pair of transistors is emphasized, if there is a difference close to 0.06 V, the semiconductor device The effect cannot be ignored on the stable operation of.

[0010] Further, as the size of the gate electrode is further reduced with the miniaturization of the element, such a dimensional change in manufacturing becomes a serious problem from the viewpoint of stable operation of the semiconductor device.

As a method for solving the above problem, M
It is most common practice to set the gate electrode of the OS transistor thicker to reduce the effect of the finished dimensional change. However, in this method, the performance of the MOS transistor is reduced, and the channel width of the MOS transistor must be increased in order to compensate for the reduction. Therefore, the occupied area of the transistor increases, which hinders high integration.

As another method, there is a method of equalizing the influence of dimensional change by arranging a pair of transistors adjacent to each other. However, this method imposes a restriction on the arrangement method of a pair of transistors, that is, an adjacent arrangement.
There is a problem that the degree of freedom in design is greatly limited.

As still another method, there has been proposed a method of inserting a dummy pattern irrelevant to the circuit operation into an empty area in a chip (for example, Japanese Patent Laid-Open No. 4-1307).
09 publication). In this method, as shown in FIG. 4, a dummy pattern 7 is formed in a sparse portion between the capacitor electrode 1 and the gate electrode 2, which is an actual pattern constituting a part of a circuit formed on the semiconductor substrate 4. Thus, the difference in pattern density is reduced to prevent a change in finished size.

However, when arranging the dummy pattern, it is necessary to arrange the dummy pattern so as not to adversely affect the operation of the circuit in the gap between the actual patterns, and the arrangement is considerably restricted. There is also a problem that a dummy pattern must be inserted so as to have a certain density in order to obtain the effect of suppressing the variation in the finished size.

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS type semiconductor device having improved reliability by preventing variations in the finished dimensions of the gate electrodes of a pair of MOS transistors having the same characteristics formed on a semiconductor substrate. .

[0016]

According to the present invention, there is provided a semiconductor device comprising:
A pair of MOs having the same characteristics formed on a semiconductor substrate
An S transistor and a MOS capacitor having an area of a capacitor electrode provided in the vicinity of the MOS transistor and having an area of 10,000 μm ² or more, wherein the gate electrode and the capacitor electrode of the MOS transistor are formed of the same layer and of the same material. In the MOS type semiconductor device, the pair of MOs
The gate electrode of the S transistor is disposed substantially equidistant from an end of the capacitor electrode.

[0017]

The amount of change in the finished size of the gate electrode depends on the distance between the capacitor and the transistor. It has been found that when the distance from the capacitor electrode exceeds 100 μm, the amount of change is reduced to almost half. Considering this point and the fact that the variation varies depending on the type of the etching apparatus and the photoresist and the manufacturing conditions, the remarkable effect of the present invention, that is, the variation in the threshold voltage within 0.04 V can be suppressed. This is the case where a pair of MOS transistors are arranged within 200 μm in the vicinity of a large area capacitor having a capacitance electrode area of 10000 μm ² or more. The distance from the capacitor is a distance from the end of the capacitor electrode.

Further, with respect to the distance from the capacitor electrode, it is not necessary to make the gate electrodes of the pair of transistors exactly equidistant, and the effect of the present invention can be expected if it is within 10% of the distance from the capacitor electrode. That is, in FIG. 1, d ₁
> When d _2, if _{(d 1 -d 2) / d} 1 ≦ 0.1,
It can be said that the present invention is within the applicable range.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a top view of a MOS transistor and a MOS capacitor for describing a first embodiment of the present invention.

Referring to FIG. 1, a MOS type semiconductor device comprises:
A pair of MOS transistors Q1A and Q1B formed on a semiconductor substrate made of silicon or the like and having the same characteristics, and a MOS capacitor 10 provided near these MOS transistors (within 200 μm) and having a capacitance electrode 1A having an area of 10,000 μm ² or more. , But this pair of MOs
Gate electrodes 2A, 2B of S transistors Q1A, Q1B
And the capacitance electrode 1A of the MOS capacitor 10 are formed in the same layer and of the same material (for example, polycrystalline silicon), and the distances d ₁ and d ₂ from the end of the capacitance electrode 1A to the gate electrodes 2A and 2B are different. They are substantially equidistant. In FIG. 1, Q1C and Q1D are other transistors, 3 is an impurity region serving as a source / drain of the transistor, and 3A is an impurity region forming another electrode of the MOS capacitor 10.

According to the first embodiment thus configured, the distance between the gate electrodes 2A and 2B of the pair of MOS transistors Q1A and Q1B from the capacitance electrode 1A is 10%.
The pair of gate electrodes 2A and 2B are formed to have the same dimensions because they are substantially equal in the range of: Therefore, a change in the characteristics of the pair of transistors is suppressed to, for example, a threshold voltage of 0.04 V or less, and a MOS semiconductor device with improved reliability can be obtained.

FIG. 2 is a top view of a MOS transistor and a MOS capacitor for explaining a second embodiment of the present invention. FIG. 2 is different from the embodiment shown in FIG. 1 in that gate electrodes 2C and 2D of a pair of MOS transistors Q2A and Q2B are formed in parallel with the sides of opposed capacitance electrode 1A. In FIG. 2, Q2C and Q2D are other MOS transistors.

In the method of arranging the transistors shown in FIG.
Two MOS transistors Q1A and Q1B forming a pair
Are arranged in a direction perpendicular to the sides of the capacitance electrode 1A facing these MOS transistors, so that even within one gate electrode, a portion close to the large area capacitance and a portion far from it exist. . MOS transistors with a small channel width have almost no effect,
When the channel width is increased, the finished size may be slightly different between the near portion and the far portion. In the second embodiment, the gate electrode 2 of the MOS transistor
Since C and 2D are arranged so as to be parallel to the sides of the capacitor electrode, there is an advantage that the dimensions of the gate electrodes 2C and 2D are more accurately formed.

In the above embodiment, a pair of M
Although the case where another MOS transistor is arranged between OS transistors has been described, it is needless to say that the case where there is no other MOS transistor may be used.

[0025]

As described above, according to the present invention, a MOS capacitor having an area of the capacitor electrode of 10,000 μm ² or more has a capacity of 200 μm.
When a pair of MOS transistors having the same characteristics are arranged close to each other within a distance of m
By making the distance between the gate electrodes of the transistors substantially equal, a change in the size of the gate electrode can be suppressed, so that the reliability of the MOS semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is an MO for describing a first embodiment of the present invention.
FIG. 4 is a top view of an S transistor and a MOS capacitor.

FIG. 2 is an MO for explaining a second embodiment of the present invention;
FIG. 4 is a top view of an S transistor and a MOS capacitor.

FIG. 3 is a top view and a cross-sectional view for explaining a conventional MOS type semiconductor device.

FIG. 4 is a cross-sectional view of a semiconductor chip for explaining a dimensional change of an electrode.

[Explanation of symbols]

 1, 1A, 1B Capacitance electrode 2, 2A-2F Gate electrode 3, 3A, 3B Impurity region 4 Semiconductor substrate 5 Field oxide film 6 Gate oxide film 7 Dummy pattern 10 MOS capacitance

Claims (2)

(57) [Claims] 1. A pair of MOS transistors having the same characteristics and formed on a semiconductor substrate, and a capacitor electrode provided near these MOS transistors has an area of 1000
A MOS semiconductor device having a MOS capacitance of 0 μm ² or more, wherein the gate electrode and the capacitance electrode of the MOS transistor are formed in the same layer and of the same material,
The MOS semiconductor device according to claim 1, wherein said gate electrodes of said pair of MOS transistors are arranged at substantially equal distances from an end of said capacitance electrode. 2. The MOS semiconductor device according to claim 1, wherein the difference between the maximum value and the minimum value of the distance between the gate electrode of the pair of MOS transistors and the end of the capacitance electrode is within 10% of the maximum value. .