JP3396872B2 - Voltage detection circuit and high voltage output circuit - Google Patents

Description

Detailed Description of the Invention

[Table of Contents] Industrial applications Conventional technology (Figs. 9 and 10) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 2) Action Example (1) Description of the first embodiment (FIGS. 3 and 4) (2) Description of the second embodiment (FIGS. 5 and 6) (3) Description of the third embodiment (FIGS. 7 and 8) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage detection circuit and a high voltage output circuit, and more specifically, to a nonvolatile memory device (EEPROM, EPROM, flash type EPROM) or LCD (Liquid Crystal Disk).
circuit) and a device for outputting the same, which detects a high voltage for writing data in the device.

In recent years, with the demand for higher performance, higher functionality and diversification of information processing devices, a read-only memory (hereinafter simply referred to as EPRO) capable of erasing and rewriting ultraviolet rays relating to various data.
Non-volatile semiconductor memory device such as a read-only memory (EEPROM) that is electrically erasable and rewritable
It is built into a microcomputer that controls C cards and home appliances. In addition, a liquid crystal display (LCD) device that displays an image is used as a support tool.

By the way, the conventional EEPROM, EPR
The circuit for detecting the write voltage when writing data in the OM, flash type EPROM, LCD device, etc. is composed of a level conversion circuit for dividing the high voltage and a voltage comparison section for detecting the compared voltage. The voltage control is performed by comparing the compared voltage with the reference voltage.

Therefore, variations in the threshold voltage of the transistors of the voltage detection system may cause variations in the output of the compared voltage, which may hinder accurate output control. Therefore, EEPROM, EPROM, flash type EP
By devising a detection system for a voltage supplied to a load circuit such as a ROM to perform voltage control depending on the breakdown voltage of a transistor forming the load circuit, to perform a wide range of voltage output control, and to improve its reliability. There is a demand for a circuit and a device that can be improved.

[0006]

2. Description of the Related Art FIGS. 9 and 10 are explanatory views of a conventional example. 9A and 9B are configuration diagrams of a high voltage output circuit and a voltage detection circuit according to a conventional example, and FIG. 9A is a write voltage supply circuit for an EPROM (memory element) according to the conventional example. FIG.

For example, a high voltage output circuit applied to a write voltage supply circuit of an EPROM, a drive voltage output circuit of an LCD device, or the like comprises a voltage detection circuit 1 and a high voltage generation circuit 2 in FIG. 9 (a). The voltage detection circuit 1 is connected to the detected point p1 of the high voltage generation circuit 2, and it is composed of a level conversion circuit 1A and a voltage comparison circuit 1B.

The function of the high voltage output circuit is, for example, when rewriting data in the EPROM 3, a reference voltage Vref is set in the voltage detecting circuit 1 in advance with respect to the voltage VPP related to the rewriting. Then, the high voltage generating circuit 2 outputs the voltage VPP, which is the EPROM.
3 write circuit.

At this time, in the level conversion circuit 1A of the voltage detection circuit 1, the voltage VPP is level-converted into a low voltage which becomes the compared voltage v, and the compared voltage v and the reference voltage Vref are compared. And the voltage detection signal S
V is fed back to the high voltage generation circuit 2 and the high voltage generation circuit 2
Then, the voltage VPP is constantly output based on the voltage detection signal SV.

Incidentally, FIG. 9 (b), FIG. 10 (a), (b)
Shows a configuration example of a voltage detection circuit applied to the high voltage generation circuit 2 according to the conventional example. For example, in FIG. 9B, the voltage VPP related to rewriting is related to the compared voltage v.
The first voltage detection circuit that divides the
N-type enhancement field effect transistors TN
e, a level conversion circuit 1A composed of one n-type depletion field effect transistor TNd, and a low voltage source V
It is composed of a comparator COMP connected to CC, an inverter IN, a resistor R for generating a reference voltage Vref, and a voltage comparison circuit 1B composed of an n-type depletion field effect transistor TNd.

Further, in FIG. 10A, the second reference voltage Vref is fixed with respect to the rewriting voltage VPP.
Is a level conversion circuit 1A composed of a diode D and a reference resistor Rr, a comparator COMP connected to a low voltage source VCC, an inverter IN and a reference voltage Vref.
The voltage comparator circuit 1B is composed of a resistor R and a constant current source I.

Further, in FIG. 10B, the third voltage detection circuit in which the reference voltage Vref is variable with respect to the voltage VPP related to rewriting is the level conversion circuit 1A composed of the diode D and the reference resistance Rr. A variable voltage comparison circuit 1C including four p-type enhancement field effect transistors TPe, four n-type depletion field effect transistors TNd, four switching elements SW and two n-type enhancement field effect transistors TNe.
Composed of.

In the first and second voltage detection circuits, since the reference voltage Vref is fixed, the control target voltage VPP for rewriting has a constant value. On the other hand, since the reference voltage Vref is variable in the second voltage detection circuit, the target voltage VPP for rewriting can be set within a certain control range.

[0014]

By the way, according to the first voltage detecting circuit of the conventional example, as shown in FIG.
The n number of n of the level conversion circuit 1A are related to the compared voltage v.
The voltage VPP for rewriting is divided and obtained by the enhancement type field effect transistor TNe of the type.

Therefore, the output of the compared voltage v varies due to variations in the threshold voltage of the n enhancement field effect transistors TNe. this is,
It is considered that it varies due to variations in the manufacturing process of the enhancement field effect transistor TNe, for example, the difficulty of controlling the impurity ion implantation.

As a result, the voltage detection signal SV fed back from the voltage comparison circuit 1B to the high voltage generation circuit 2 varies,
This hinders accurate output control of the voltage VPP by the high voltage generation circuit 2.

Further, according to the second voltage detection circuit of the conventional example, as shown in FIG.
Electron avalanche of diode D of level conversion circuit 1A (Ava
The voltage VPP related to rewriting is detected by utilizing the lnche Breakdown phenomenon.

For this reason, the drive voltage Vcc of the voltage detection system is low, for example, about 3 to 5 [V] for the voltage VPP for rewriting the data Data of the EPROM 3, for example, about 12.5 to 30 [V]. If there is a request to design
The diode D whose reverse withstand voltage is set high must be used. As a result, the electron avalanche current flowing through the reference resistor Rr increases.

Further, according to the third conventional voltage detecting circuit, as shown in FIG. 10 (b), the level converting circuit 1A is related to the compared voltage v and is similar to the second voltage detecting circuit.
By utilizing the electron avalanche phenomenon of the diode D, the voltage VPP related to rewriting is detected, and the compared voltage v is changed by the variable voltage comparison circuit 1C to the switching element S.
By selecting W, it is related to the voltage detection signal SV,
The control is "coarse" and "fine".

Therefore, the voltage detection signal SV fed back from the voltage comparison circuit 1B to the high voltage generation circuit 2 becomes stepwise, which hinders the smooth output control of the voltage VPP by the high voltage generation circuit 2. This makes it difficult to perform a wide voltage output control depending on the breakdown voltage of a transistor that forms the write circuit (hereinafter, also simply referred to as a load circuit) of the EPROM 3 to which the voltage VPP is supplied.

As a result, since the reliability of the first to third voltage detection circuits is lowered, the EPROM to which the voltage VPP is supplied is supplied.
There is a problem that the insulation of No. 3 is threatened, the desired data writing and erasing processing cannot be performed, and wasteful time is spent. The EPRO built in the voltage detection circuit
In M3, the reliability is lowered.

The present invention has been made in view of the problems of the conventional example, and devises the detection system of the voltage supplied to the load circuit to control the voltage depending on the breakdown voltage of the transistor constituting the load circuit. It is an object of the present invention to provide a voltage detection circuit and a high voltage output circuit capable of performing a wide range of voltage output control and improving its reliability.

[0023]

[Means for Solving the Problems] FIGS.
FIG. 3 is a principle diagram of a voltage detection circuit according to the present invention, and FIG. 2 is a principle diagram of a high voltage output circuit according to the present invention.

The first voltage detection circuit of the present invention is shown in FIG.
As shown in (a), the voltage detection part p1 and the ground line GND
A voltage output circuit 11 connected between the second voltage V1 and the second voltage V2 which is lower than the first voltage V1 based on the first voltage V1 of the voltage-detected part p1;
And a signal detection circuit 12 for outputting a voltage detection signal SV relating to the voltage detection part p1 based on the voltage V2 of the first voltage V1 including at least the voltage detection part p1.
Is connected to either the source electrode or the drain electrode of the first field effect transistor 13, the well portion of the first field effect transistor 13 is connected to the ground line GND, and the voltage output Circuit 11
The well portion is connected to a connection point connecting the signal detection circuit 12 with the first field effect transistor 13
The breakdown voltage is controlled by the gate voltage.

In the second voltage detection circuit of the present invention, as shown in FIG. 1A, the voltage output circuit 11 and the signal detection circuit 12 are connected to each other in the first voltage detection circuit. Between the connection point p2 and the voltage detection part p1,
Second field effect transistor 14 shown in (c) and (d)
A or a diode 14B is connected, and the breakdown voltage of the second field effect transistor 14A is controlled by the gate voltage.

Further, another voltage detecting circuit of the present invention is shown in FIG.
As shown in (a) and (b), the cathode is the voltage supply line V.
A diode Dr, which is electrically connected to PP and whose anode is electrically connected to a ground line, and a gate electrode 13D are formed on a well of opposite conductivity type in a semiconductor substrate of one conductivity type. One side of the gate electrode 13D is formed. The well surface has an impurity diffusion region 13C of one conductivity type and the impurity diffusion region 1
A modified field effect transistor 23 in which 3C is electrically connected to the cathode of the diode Dr, and the well is electrically connected to the anode of the diode Dr.
And the voltage of the anode of the diode Dr is input,
A signal detection circuit 22 that outputs a voltage detection signal SV that controls the voltage of the voltage supply line based on the voltage,
The break voltage of the modified field effect transistor 23 is controlled by the gate voltage of the modified field effect transistor 23.

Further, the high voltage output circuit of the present invention is shown in FIG.
As shown in FIG. 5, the load circuit 18 is provided with a variable voltage supply means 16 for supplying a voltage VPP, and a voltage detection means 17 for detecting the voltage VPP and outputting a voltage detection signal SV to the variable voltage supply means 16. It is characterized in that the voltage detecting means 17 comprises a first or second voltage detecting circuit or another voltage detecting circuit.

[0028]

[0029]

[0030]

[Operation] According to the first voltage detection circuit of the present invention, FIG.
As shown in (a), the voltage output circuit 11 and the signal detection circuit 12 are provided, and the first voltage V including the voltage-detected portion p1.
1 current supply dummy field effect transistor 1
3 are connected.

For example, by the voltage output circuit 11 connected between the voltage detection part p1 and the ground line GND, the detection part p
The first voltage V1 according to No. 1 is converted to a voltage level (V2 <V1) lower than the voltage V1 and is output to the signal detection circuit 12.

In addition, a current detecting dummy field effect transistor 13 connected between the voltage-detected portion p1 and the ground line GND, for example, a bias element 15 is connected in series to its back gate, and the bias element is connected to the bias element 15. A voltage converted into a voltage level lower than the first voltage V1 of the detection section p1 by the current detection dummy field effect transistor 13 of which 15 is connected to the ground line GND is a signal detection circuit 12
Is output to.

At this time, in the dummy field effect transistor 13 for current detection, a current flows from the voltage detection part p1 to the back gate due to the breakdown phenomenon of the gate junction based on the gate voltage Vg1 and the first voltage V1. As a result, a voltage drop occurs in the bias element 15. The voltage detection information is output to the signal detection circuit 12 together with the second voltage V2 whose level has been converted by the voltage output circuit 11.

Therefore, by variably controlling the gate voltage vg1 of the current detecting dummy field effect transistor 13,
Break voltage VBD of the gate junction is VBD ≈ VBD
It is possible to control the voltage at 0 + vg1. However, the break voltage VBD1 is a break voltage when the gate voltage vg1 = 0.

As a result, even if the threshold voltage of the transistor forming the voltage detection circuit varies as in the conventional example, the gate voltage vg1 is variably controlled to become the compared voltage. It is possible to output the voltage V2 of 2 with good stability.

As a result, the output control of the other circuits can be performed with high reliability based on the accurate voltage detection signal SV. According to the second voltage detection circuit of the present invention, FIG.
As shown in (a), in the first voltage detection circuit, the current detection dummy field effect transistor 13 is assisted between the point p2 connecting the voltage conversion circuit 11 and the signal detection circuit 12 and the voltage detection part p1. The voltage detection auxiliary element 14 is connected.

For example, the voltage detection auxiliary element 14 composed of the field effect transistor 14A or the diode 14B is connected between the voltage detection part p1 and the connection point p2. For this reason,
The first voltage V1 related to the detection part p1 is the voltage output circuit 1
1. The voltage is converted into a voltage level (V2 <V1) lower than the voltage V1 by the current detecting dummy field effect transistor 13, the field effect transistor 14A and the diode 14B, and the voltage level is collectively output to the signal detection circuit 12. .

At this time, in the voltage detection auxiliary element 14, based on the gate voltage Vg2, the field effect transistor 14A concerned.
A current flows from the voltage detection part p1 to the bias element 15 due to the switchback phenomenon and the punch-through phenomenon related to the operation of the lateral bipolar transistor parasitic on the bias bipolar element 15, and a voltage drop occurs in the bias element 15 based on this.

Further, due to the breakdown phenomenon of the diode 14B, a current flows from the voltage-detected portion p1 to the bias element 15, and accordingly, a voltage drop occurs in the bias element 15.

Therefore, by variably controlling the gate voltage Vg2 of the field effect transistor 14A, it becomes possible to assist the voltage control of the dummy field effect transistor 13 for current detection. As a result, even when the threshold voltage of the transistor forming the voltage detection circuit is varied as in the conventional example, the gate voltage vg2 is variably controlled, so that the first voltage detection circuit can be controlled in the same manner as the first voltage detection circuit. , The second voltage V2 can be output with good stability.

As a result, the output control of the other circuits can be executed with high reliability based on the accurate voltage detection signal SV. Further, according to the third voltage detection circuit of the present invention, as shown in FIG. 1B, in the first and second voltage detection circuits, the dummy electric field effect for current detection connected to the voltage detection part p1 is connected. The other of the transistor 13 and the voltage detection auxiliary element 14 is connected to the ground line GND by connecting the bias element 15 in series.

For example, the dummy field effect transistor 13 for current detection, the voltage detection auxiliary element 14 and the bias element 15 are used.
The voltage information regarding the connection point p3 with is input to the signal detection circuit 12.

Therefore, the first voltage V1 related to the detecting portion p1 is lower than the voltage V1 by the voltage output circuit 11, the current detecting dummy field effect transistor 13, the field effect transistor 14A and the diode 14B. It is converted to (V2 <V1), which is individually output to the signal detection circuit 12.

As a result, in the signal detection circuit 12,
It is possible to diversify the voltage detection function by performing signal processing such as logical sum or exclusive logical sum of the individually input voltage detection signals.

Thus, for example, the first voltage V1
The dummy field effect transistor 13 for current detection and the voltage detection auxiliary element 14 are formed under the same conditions as the transistors constituting the load circuit to which the voltage is supplied, thereby accurately controlling the output of other circuits based on the voltage detection signal SV. It becomes possible to execute well.

Further, according to the high voltage output circuit of the present invention, as shown in FIG. 2, the variable voltage supply means 16 and the voltage detection means 17 are provided, and the voltage detection means 17 is the first to third aspects of the present invention. Voltage detection circuit.

For example, the first and the first transistors each having a structure similar to that of the load circuit 18 are formed.
Second and third voltage detection circuits are provided in the high voltage output circuit. In addition, from the variable voltage supply means 16 to the load circuit 18
When the voltage VPP is supplied to the
The voltage detection signal SV is detected by the voltage detection means 17 such as a third voltage detection circuit or the like, and the voltage detection signal SV is output from the voltage detection means 17 to the variable voltage supply means 16.

Therefore, in the voltage detecting means 17, the electron avalanche phenomenon of the diode for level conversion is utilized,
For example, when the load circuit 18 is an EPROM or the like and the voltage VPP for rewriting the data is detected, the drive power supply of the voltage detection system is designed to be a low voltage with respect to the write voltage (high voltage). Even if there is a request to do so, the reference current of the detection circuit can be set small.

As a result, it is possible to suppress the useless current flowing through the reference resistance of the voltage detecting means 17 to a small value. Also, from the voltage detection means 17 to the variable voltage supply means 1
The voltage detection signal SV fed back to 6 is the gate voltage vg1 or v
Since it is obtained by smooth control depending on g2, the target voltage can be stably output by the voltage supply means 16.

As a result, it is possible to perform a wide range of voltage output control depending on the breakdown voltage of the transistors forming the load circuit 18 such as EPROM and EEPROM. As a result, the reliability of the first to third voltage detection circuits is improved, so that desired data writing and erasing processing can be performed, and wasteful time can be omitted. Further, it is possible to improve the reliability of the semiconductor integrated circuit device incorporated in the high voltage output circuit.

[0051]

Embodiments of the present invention will now be described with reference to the drawings. 3 to 8 are diagrams illustrating a voltage detection circuit and a high voltage output circuit according to each embodiment of the present invention.

(1) Description of First Embodiment FIG. 3 is a block diagram of a voltage detection circuit according to a first embodiment of the present invention, and FIG. 3 (a) is a circuit diagram thereof. Three
3B is a sectional view of the dummy field effect transistor for current detection.

For example, 12.5 to 30 required by the load circuit
The first voltage detection circuit for detecting the voltage VPP of the voltage detection part (hereinafter also referred to as the detection point p1) of about [V] is shown in FIG.
In (a), it comprises a level conversion circuit 21, an analog signal detection circuit 22, an n-type modified field effect transistor (hereinafter simply referred to as n-type modified MOSFET) 23 and a resistor R11.

That is, the level conversion circuit 21 is an example of the voltage output circuit 11, and is composed of the diode D and the reference resistance Rr. The cathode (−) of the diode D is connected to the voltage detection part p1, and the anode (+) thereof is connected to the reference resistance Rr and connected to the ground line GND. Further, a point (hereinafter referred to as a connection point p2) connected to the anode (+) and one end of the reference resistance Rr is the analog signal detection circuit 22.
Of the n-type depletion field effect transistor Td1.

The function of the level conversion circuit 21 is to detect the second voltage V2 [V2 <V1] which is the detected voltage based on the voltage VPP related to the detected point p1 = the first voltage V1 as an analog signal. It is output to the circuit 22.

The analog signal detection circuit 22 is an embodiment of the signal detection circuit 12, and outputs the voltage detection signal SV related to the detected point p1 to the outside based on the second voltage V2. For example, the analog signal detection circuit 22 has two n
Type depletion field effect transistors Td1, Td2, 4
P-type enhancement field effect transistors Tp1
Tp4, two n-type enhancement field effect transistors Te1 and Te2, and an inverter IN1. The signal detection circuit 22 is connected to a low voltage source Vcc of about 3 to 5 [V].

The n-type modified MOSFET 23 is one example of the dummy field effect transistor 13 for current detection, and is connected to the supply line of the first voltage V1 including the detected point p1.
The n-type modified MOSFET 23 has a structure in which only one n-channel region corresponding to the source of the n-type MOSFET is formed.

For example, the n-type modified MOSFET 23 is shown in FIG.
As shown in (b), an n-type Si (silicon) substrate 13A is provided with a p-type well layer 13B, and the p-type well layer 13B is n-type.
+ Gate electrode via impurity diffusion layer 13C and gate oxide film
13D is formed.

Further, in FIG. 3B, the parasitic diode D11 is generated by the pn junction, and the breakdown phenomenon of the gate junction based on the gate voltage Vg1 and the first voltage (VPP) V1 causes the p-type well from the detected point p1. An electric current is passed through the layer (back gate) 13B.

The resistor R11 is one embodiment of the bias element 15, is connected between the back gate of the n-type modified MOSFET 23 and the ground line (n-type Si substrate 13A) GND, and is a current generated by the breakdown phenomenon of the gate junction. A voltage drop is generated based on

The voltage detection information is output to the analog signal detection circuit 22 together with the voltage detection information of the detected point p2. Further, the gate voltage vg1 is supplied to the gate G of the n-type modified MOSFET 23, and the breakdown of the gate junction is controlled.

As described above, the first voltage detection circuit of the present invention is provided with the level conversion circuit 21 and the analog signal detection circuit 22 as shown in FIG.
The n-type modified MOSFET 23 and the resistor R11 are connected to the supply line of the first voltage V1 including the detected point p1.

For example, by the level conversion circuit 21 connected between the detected point p1 and the ground line GND, the detection part p1
Is converted into a voltage level (V2 <V1) lower than the voltage V1 and is output to the analog signal detection circuit 22.

The n-type modified MOSFET 23 connected between the detected point p1 and the ground line GND through the resistor R11.
As a result, the voltage converted to a voltage level lower than the first voltage V1 related to the detection point p1 is converted into the analog signal detection circuit 2
2 is output.

At this time, in the n-type modified MOSFET 23, the detection point p1 is generated due to the breakdown phenomenon of the gate junction based on the gate voltage Vg1 and the first voltage V1.
Current flows from the back gate to the back gate, and based on this, the resistance R
A voltage drop occurs at 11. The voltage detection information is output to the analog signal detection circuit 22 together with the second voltage V2 whose level is converted by the level conversion circuit 21.

Therefore, by variably controlling the gate voltage vg1 of the n-type modified MOSFET 23, it is possible to control the voltage so that the break voltage VBD of the gate junction becomes VBD≈VBD0 + vg1. However, the break voltage V
BD1 is a break voltage when the gate voltage vg1 = 0.

As a result, even if the threshold voltage of the transistor forming the first voltage detection circuit varies as in the conventional example, the gate voltage vg1 is variably controlled to control the compared voltage. It becomes possible to output the second voltage V2 which becomes

As a result, the output control of the other circuits can be reliably executed based on the accurate voltage detection signal SV. Next, the high voltage output circuit of the present invention to which the first voltage detection circuit is applied will be described while supplementing the function of the detection circuit.

FIG. 4 is a block diagram of a high voltage output circuit according to the first embodiment of the present invention. For example, EEPRO
When writing data to M28, write voltage VPP
The high voltage output circuit for automatically controlling the voltage is shown in FIG. 4 as a low voltage doubling high voltage generation circuit 26 and a voltage detection circuit 101.
Consists of.

That is, the low voltage doubling high voltage generation circuit 26 is an embodiment of the variable voltage supply means 16, and the load circuit 18
The data writing voltage V is stored in the EEPROM 28 as an example.
It supplies PP. For example, the high voltage generating circuit 2
Reference numeral 6 is an oscillator 26A, a timing control circuit 26B, a plurality of switching transistors TN1 to TNn, and a plurality of charge storage capacitors C1 to Cn, and generates a voltage VPP for writing data at 12 locations based on a reference clock CK and a voltage detection signal SV. To do.

The source and gate of the switching transistor TN1 are connected to the power supply line Vcc, and the remaining switching transistors TN2 to TNn have their sources and drains connected in series between the switching transistor TN1 and the point to be detected p1. The respective gates are connected to the respective charge storage capacitors C1 to Cn and connected to the source. Further, the other end of each of the charge storage capacitors C1 to Cn is connected to the output section of the timing control circuit 26B so that the portions related to the odd columns and the portions related to the even columns are individually connected.

The voltage detection circuit 101 is an embodiment of the voltage detection means 17, and detects the voltage VPP and doubles the voltage detection signal SV to the low voltage double voltage generation circuit 26 timing control circuit 26B.
Is output to. The voltage detection circuit 101 comprises the voltage detection circuit according to the first embodiment of the present invention, and the high voltage generation circuit 26 and the voltage detection circuit 101, especially the n-type modified MO.
The SFET 23 is composed of a transistor formed by the same mask as the constituent transistor of the EEPROM 28.

Thus, according to the high voltage output circuit of the first embodiment of the present invention, the low voltage doubling high voltage generating circuit 26 and the voltage detecting circuit 101 are provided as shown in FIG. The voltage detection circuit 101 comprises the voltage detection circuit according to the first embodiment of the present invention.

For example, the high voltage output circuit is provided with a first voltage detection circuit composed of transistors having the same structure as the constituent transistors of the EEPROM 28. In addition, the low voltage doubled high voltage generation circuit 26 to the EEPROM 28
When the voltage VPP is supplied to the circuit, the voltage VPP is applied to the level conversion circuit 21 of the first voltage detection circuit and the n-type modified MOSFE.
The voltage detection signal SV detected by T23 is fed back from the voltage detection circuit 101 to the timing control circuit 26B of the low voltage doubled high voltage generation circuit 26.

Therefore, in the voltage detection circuit 101, the electron avalanche phenomenon of the diode Dr for level conversion is used to rewrite the data in the EEPROM 28 with the voltage VPP.
In the case of detecting the write voltage and there is a demand for designing the drive power supply of the voltage detection system to the low voltage Vcc for the write voltage (high voltage), the reference current of the detection circuit is set small. can do.

As a result, it is possible to suppress the useless current flowing through the reference resistor Rr of the voltage detecting circuit 101 to be small. Further, since the voltage detection signal SV fed back from the voltage detection circuit 101 to the low voltage doubled high voltage generation circuit 26 is obtained by smooth control depending on the gate voltage vg1, the target voltage VPP is stabilized by the voltage detection circuit 101. Then, it is possible to output.

From this, a wide range of voltage output control (feedback control) considering the withstand voltage of the write circuit 28A and the memory cell 28B constituting the EEPROM 28 is performed.
It becomes possible to do.

As a result, the reliability of the voltage detection circuit 101 is improved, so that desired data writing and erasing processing can be performed, and unnecessary rewriting time can be omitted. Further, it is possible to improve the reliability of the semiconductor integrated circuit device incorporated in the high voltage output circuit.

(2) Description of Second Embodiment FIG. 5 is a block diagram of a voltage detection circuit according to a second embodiment of the present invention, and FIG. 6 relates to a second embodiment of the present invention. The respective block diagrams of the high-voltage output circuit are shown.

In FIG. 5, the second embodiment is different from the first embodiment in that an n-type MOSFET 24A and a Zener diode 24B for assisting the n-type modified MOSFET 23 are provided.

That is, the n-type MOSFET 24A and the Zener diode 24B are an example of the voltage detection auxiliary element 14, and the level conversion circuit 21 and the analog signal detection circuit 22 are included.
It is connected between a point p2 that connects and the point to be detected p1.

The n-type MOSFET 24A receives a current from the detection point p1 to the resistor R12 based on the gate voltage Vg2 due to the switchback phenomenon related to the operation of the lateral bipolar transistor Q parasitic on the MOSFET 24A and the punch-through phenomenon due to the diode D12. Shed.

Further, the resistor R12 is an embodiment of the bias element 15, and the diode Dr, of the level conversion circuit 21
It serves as a back gate of the n-type modified MOSFET 23 and a common bias element of the voltage detection auxiliary element 14. The resistor R12 is connected between the connection point p2 and the ground line GND. As a result, a voltage drop occurs based on the current generated by the breakdown phenomenon of the gate junction, the switchback phenomenon, and the punchthrough phenomenon, and the second voltage V2 that is the detected voltage is generated.

In this way, according to the voltage detection circuit of the second embodiment of the present invention, as shown in FIG. 5, the point p2 connecting the level conversion circuit 21 and the analog signal detection circuit 22 and the target N-type modified MOSFET 23 between the detection point p1
N-type MOSFET 24A and Zener diode to assist the
24B is connected.

Therefore, the first voltage V1 related to the detection point p1 is the diode D11, the n-type modified MOSFET 23,
The voltage is converted to a voltage level (V2 <V1) lower than the voltage V1 by the n-type MOSFET 24A and the Zener diode 24B, and the voltage level is collected and output to the analog signal detection circuit 22.

At this time, in the n-type modified MOSFET 23, the detection point p1 is generated due to the breakdown phenomenon of the gate junction based on the gate voltage Vg1 and the first voltage V1.
Current flows from the back gate to the back gate. Further, in the n-type MOSFET 24A of the voltage detection auxiliary element 14, the gate voltage Vg2
On the basis of the first voltage V1 and the first voltage V1, the detected point p due to the switchback phenomenon or the punch-through phenomenon related to the operation of the lateral bipolar transistor parasitic on the MOSFET 24A.
A current flows from 1 to the resistor R12.

Further, a current flows from the detected point p1 to R12 due to the breakdown phenomenon of the Zener diode 24B, and a voltage drop occurs at R12 based on this, and the voltage detection information is level-converted by the level conversion circuit 21. It is output to the analog signal detection circuit 22 together with the second voltage V2.

Therefore, by variably controlling the gate voltage Vg2 of the n-type MOSFET 24A, the n-type modified MOSFET can be obtained.
It becomes possible to assist the voltage control of 23. As a result, even when the threshold voltage of the transistor that constitutes the voltage detection circuit varies as in the conventional example, the gate voltage vg2 is variably controlled, so that the same operation as in the first embodiment is performed. It is possible to control the output of the second voltage V2 with good stability.

This makes it possible to control the output of other circuits based on the accurate voltage detection signal SV.
Next, the second high voltage output circuit of the present invention will be described while supplementing the function of the detection circuit.

FIG. 6 is a block diagram of a high voltage output circuit according to the second embodiment of the present invention. In FIG. 6, the first
The second embodiment is different from the second embodiment in that the high voltage output circuit is provided with the voltage detection circuit 102 in the second embodiment.

For example, the second high voltage output circuit for automatically controlling the write voltage VPP when writing data to the EEPROM 28 is the low voltage double high voltage generating circuit 26 and the voltage detecting circuit 102 shown in FIG. Consists of. In addition,
The same names and symbols as those in the first embodiment have the same functions, so that the description thereof will be omitted.

That is, the voltage detection circuit 102 is another embodiment of the voltage detection means 17, and detects the voltage VPP and outputs the voltage detection signal SV to the timing control circuit 26B of the low voltage double high voltage generation circuit 26. It is a thing. The voltage detecting circuit 102 comprises the voltage detecting circuit according to the second embodiment of the present invention, and the high voltage generating circuit 26 and the voltage detecting circuit 101, especially the n-type modified MOSFET 23 are formed by the same mask as the constituent transistors of the EEPROM 28. It is composed of formed transistors.

In this way, according to the high voltage output circuit of the second embodiment of the present invention, the low voltage doubling high voltage generating circuit 26 and the voltage detecting circuit 102 are provided as shown in FIG. The voltage detection circuit 102 comprises the voltage detection circuit according to the second embodiment of the present invention.

For example, when the voltage VPP is supplied from the low voltage doubled high voltage generation circuit 26 to the EEPROM 28, the voltage VPP is supplied to the level conversion circuit 21 of the voltage detection circuit 102, the n-type modified MOSFET 23, the n-type MOSFET 24A and the Zener diode. The voltage detection signal S detected by 24B
V from the voltage detection circuit 102 to the low voltage doubled high voltage generation circuit 26
Is output to the timing control circuit 26B.

Therefore, similarly to the first embodiment, the reference current of the voltage detecting circuit 102 can be set small, and the useless current flowing through the resistor R11 can be suppressed small. Further, since the voltage detection signal SV fed back from the voltage detection circuit 102 to the low voltage doubled high voltage generation circuit 26 is obtained by smooth control depending on the gate voltages vg1 and vg2, the target voltage VPP is generated by the voltage detection circuit 102. Can be output stably.

As a result, the EE is the same as in the first embodiment.
A wide range of voltage output control can be performed in consideration of the breakdown voltage of the constituent transistors of the PROM 28, and the reliability of the semiconductor integrated circuit device in which the high voltage output circuit is built can be improved.

(3) Description of Third Embodiment FIG. 7 is a block diagram of a voltage detection circuit according to a third embodiment of the present invention, and FIG. 8 is a block diagram of its high voltage output circuit. Shows.

In FIG. 7, the difference from the first and second embodiments is that in the third embodiment, the n-type modified MOSFET 23 and the n-type MOSFET 24 respectively connected to the detected point p1.
A signal detection logic circuit 32 for individually detecting the detected voltages V21 to V24 of the A and level conversion circuit 21 and processing them is provided.

For example, 12.5 to 30 required by the load circuit
The third voltage detection circuit for detecting the voltage VPP at the detected point p1 of about [V] is shown in FIG. 7 and has resistors R101, R102, R103, and a reference resistor R between the detected point p1 and the ground line GND.
It is composed of an n-type modified MOSFET 23, an n-type MOSFET 24A, a level conversion circuit 21 and a signal detection logic circuit 32 which processes the signal thereof, which are connected via r.

That is, the first detected voltage V21 is obtained from the connection point p21 of the resistor R1O1 connected between the back gate of the n-type modified MOSFET 23 and the ground line GND, which is the signal detection logic circuit 32. It is input to the n-type depletion field effect transistor Td31.

The second detected voltage V22 is an n-type MOS.
It is obtained from the connection point p22 of the resistor R1O2 connected between the back gate of the FET 24 and the ground line GND, which is input to the n-type depletion field effect transistor Td32 of the signal detection logic circuit 32. Further, the third detected voltage V23 is the drain D of the n-type MOSFET 24 and the ground line G.
It is obtained from the connection point p23 of the resistor R1O3 connected to the ND line, and is input to the n-type depletion field effect transistor Td33 of the signal detection logic circuit 32.

The fourth detected voltage V24 is obtained from the connection point p24 between the diode Dr of the level conversion circuit 21 and the reference resistor Rr connected to the ground line GND, which is the n-type of the signal detection logic circuit 32. It is input to the depletion field effect transistor Td34.

The signal detection logic circuit 32 is the signal detection circuit 12
It is another example of the first to fourth detected voltages V21-
The voltage detection signal SV related to the detected point p1 is output to the outside based on V24. For example, the signal detection logic circuit 32 includes five n-type depletion field effect transistors Td31 to Td35, four p-type enhancement field effect transistors Tp31 to Tp34, two n-type enhancement field effect transistors Te31 and Te32 and an inverter IN2. It constitutes a 4-input logical sum circuit. Also,
The signal detection logic circuit 32 is connected to a low voltage source Vcc of about 3 to 5 [V].

The same names and symbols as those of the first and second embodiments have the same functions, so that the description thereof will be omitted. Thus, according to the voltage detection circuit of the third embodiment of the present invention, as shown in FIG. 7, the n-type modified MOSFET 23, the n-type MOSFET 24A and the level conversion circuit 21 connected to the detected point p1 are connected. The other electrode portion of the diode Dr is connected to the ground line GND through the resistors R101, R102, R103 and the reference resistor Rr, and the detected voltages V21 to V24 relating to the connection points p21 to p24 are individually detected. .

Therefore, the n-type modified MOSFETs 23, n
When the voltage information ([V21-V24] <V1) relating to the connection points p21-p24 individually detected by the MOSFET 24A and the diode Dr of the level conversion circuit 21 is input to the signal detection logic circuit 32, 4 of the signal is input. By performing input OR processing or the like, it becomes possible to diversify the voltage detection function as compared with the conventional example.

For example, even when the threshold voltage of the transistors forming the voltage detection circuit varies as in the conventional example, the n-type MOS is used as in the first and second embodiments.
By variably controlling the gate voltage Vg2 of the FET 24A,
It becomes possible to assist the voltage control of the mold modification MOSFET 23.

As a result, when the n-type modified MOSFET 23, the n-type MOSFET 24A and the diode Dr of the level conversion circuit 21 are formed under the same conditions as the transistors constituting the load circuit to which the first voltage V1 is supplied, If the voltage information V21 to V24 relating to the connection points p21 to p24 is detected by any one of them, the output control of other circuits can be accurately executed based on the voltage detection signal SV.

Next, the third high voltage output circuit of the present invention will be described while supplementing the function of the detection circuit. FIG. 8 is a block diagram of a high voltage output circuit according to the third embodiment of the present invention. In FIG. 8, the third embodiment differs from the first and second embodiments in that the high voltage output circuit is provided with a voltage detection circuit 103.

For example, when writing data or supplying a drive voltage to a drive circuit of an EPROM or LCD device (not shown),
A third high voltage output circuit for automatically controlling the write voltage and the drive voltage VPP is shown in FIG.
1 and a voltage detection circuit 103. It is to be noted that those having the same names and symbols as those in the first and second embodiments have the same functions, and therefore the description thereof is omitted.

That is, the voltage control circuit 31 is an embodiment of the variable voltage supply means 16, and ON / OFF controls the voltage VPP variably supplied from the outside based on the voltage control signal SV. For example, the voltage control circuit 31 includes five p-type enhancement field effect transistors (hereinafter referred to as first to fifth transistors) TP41 to TP45 and four n-type enhancement field effect transistors (hereinafter sixth to ninth transistors). TN41 to TN44 and 1
The charge storage capacitor C is provided for controlling output of a desired data write voltage or drive voltage VPP based on the voltage detection signal SV.

First and third transistors TP41, TP43
The sixth and seventh transistors TN41 and TN42 have their sources and drains connected in series with each other, and the source and drain thereof are connected to the voltage V
It is connected between the power line related to PP and the ground line GND, and
Second and fourth transistors TP42, TP44 and eighth and ninth transistors
The transistors TN43 and TN44 of which source and drain are connected in series to each other are connected between the power supply line for the voltage VPP and the ground line GND.

The fifth transistor TP45 has a voltage V
The PP is connected between an external connection point to which PP is variably supplied and the detected point p1, and the charge storage capacitance C is connected to the drain (detected point p1) portion thereof. The first transistor TP4
The gate of 1 is the second and fourth transistors TP42, TP44
Of the fifth transistor TP45 and connected to the source / drain connection part thereof.

Further, the gate of the second transistor TP42 is connected to the source / drain connection portions of the first and third transistors TP41, TP43, and the third, fourth, sixth and eighth transistors TP43, TP44, TN41, TN43. Are connected to the power supply line Vcc. Also, the gate of the seventh transistor TP42 and the ninth transistor TN4
The inverter IN3 is connected to the gate of the transistor 4 and the voltage control signal SV is input to the gate of the transistor TN42.

The voltage detection circuit 103 is an embodiment of the voltage detection means 17, and detects the voltage VPP and outputs the voltage detection signal SV to the seventh transistor TN42 of the voltage control circuit 31. The voltage detection circuit 103 is the third embodiment of the present invention.
The voltage control circuit 31 and the voltage detection circuit 103, especially the n-type modified MOSFET.
The transistors constituting the 23 and n-type MOSFET 24A are formed by the same mask.

Thus, according to the high voltage output circuit of the third embodiment of the present invention, the voltage control circuit 31 and the voltage detection circuit 103 are provided as shown in FIG. 8, and the voltage detection circuit 103 is provided. Is a third voltage detection circuit of the present invention.

For example, the third voltage detection circuit 103 formed by a transistor having a structure similar to that of a transistor forming a drive circuit of an EPROM or LCD device is provided in the high voltage output circuit. Further, when writing data or supplying a drive voltage from the voltage control circuit 31 to a drive circuit of an EPROM or LCD device (not shown), the voltage VPP is detected by a third voltage detection circuit or the like, and the voltage detection signal SV is detected. It is output from the voltage detection circuit 103 to the voltage control circuit 31.

Therefore, in the voltage detection circuit 103, for example, when the electron avalanche phenomenon of the diode DR for level conversion is used to detect the voltage VPP for rewriting data relating to the EPROM, the write voltage Even when there is a request to design the driving power supply of the voltage detection system to have a low voltage Vcc with respect to (high voltage), the reference current of the detection circuit can be set small.

As a result, it is possible to suppress the useless current flowing through the reference resistor Rr of the voltage detecting circuit 103 to be small. In addition, the voltage detection circuit 103 to the voltage control circuit 31
The voltage detection signal SV fed back to the gate voltage vg1 or vg2
Since the voltage control circuit 31 can obtain a target voltage in a stable manner, the voltage control circuit 31 can output the target voltage in a stable manner.

As a result, it becomes possible to perform a wide range of voltage output control depending on the breakdown voltage of the transistors forming the EPROM, EEPROM, LCD device and the like. As a result, the reliability of the third voltage detection circuit is improved, and it is possible to perform desired data writing and erasing processing. For example, it is possible to reduce the number of times of additional erasing of the flash memory, and it is possible to omit wasteful processing time. Further, it is possible to improve the reliability of the semiconductor integrated circuit device incorporated in the high voltage output circuit.

[0120]

As described above, according to the first voltage detection circuit of the present invention, the voltage output circuit and the signal detection circuit are provided, and the dummy electric field effect for current detection is provided in the voltage supply line of the voltage detection target portion. The transistor is connected and a voltage lower than that voltage is output to the signal detection circuit.

Therefore, by variably controlling the gate voltage of the current detecting dummy field effect transistor, it becomes possible to control the voltage related to the break voltage of the gate junction. As a result, even if the threshold voltage of the transistor forming the voltage detection circuit varies as in the conventional example, the output of the compared voltage is stabilized by variably controlling the gate voltage. It becomes possible.

Further, according to the second voltage detection circuit of the present invention, the voltage detection auxiliary element is connected between the point connecting the voltage conversion circuit and the signal detection circuit and the voltage detection target portion. Therefore, the voltage detection auxiliary element can detect the voltage information of the voltage detection target portion based on the gate voltage by the switchback phenomenon or the punch-through phenomenon related to the operation of the lateral bipolar transistor. Further, the voltage information of the voltage detection target portion can be detected by the breakdown phenomenon of the diode. From this, it becomes possible to assist the voltage control of the dummy field effect transistor for current detection by the voltage detection auxiliary element.

Further, according to the third voltage detection circuit of the present invention, the other of the current detection dummy field effect transistor and the voltage detection auxiliary element connected to the voltage detection target has the bias element connected in series. It is connected to the ground line and is individually converted to a voltage level lower than the voltage, which is individually output to the signal detection circuit.

Therefore, in the signal detection circuit, it is possible to diversify the voltage detection function by logically processing the signals individually input for voltage detection. As a result, even when the threshold voltage of the transistor that configures the voltage detection circuit is varied as in the conventional example, the gate voltage is variably controlled so that other circuits based on the voltage detection signal are controlled. The output control can be executed with high accuracy.

According to the high voltage output circuit of the present invention,
A variable voltage supply means and a voltage detection means are provided, and the voltage detection means comprises the first to third voltage detection circuits of the present invention. Therefore, even if there is a request to design the driving power supply of the voltage detection system to be a low voltage, the reference currents of the first to third voltage detection circuits can be set small.
As a result, it is possible to suppress a wasteful current flowing through the bias elements and the like of the first to third voltage detection circuits. Further, since the voltage detection signal fed back from the voltage detection means to the variable voltage supply means is obtained by smooth control depending on the gate voltage, it becomes possible to output a stable target voltage by the voltage supply means.

As a result, it becomes possible to perform a wide range of voltage output control depending on the breakdown voltage of the transistors forming the load circuit such as EPROM and EEPROM. Further, since the reliability of the voltage detection circuit is improved, it is possible to perform desired data writing and erasing processing, and it is possible to omit a wasteful time. This greatly contributes to the improvement of the reliability of the semiconductor integrated circuit device incorporated in the high voltage output circuit.

[Brief description of drawings]

FIG. 1 is a principle diagram of a voltage detection circuit according to the present invention.

FIG. 2 is a principle diagram of a high voltage output circuit according to the present invention.

FIG. 3 is a configuration diagram of a voltage detection circuit according to a first embodiment of the present invention.

FIG. 4 is a configuration diagram of a high voltage output circuit according to a first embodiment of the present invention.

FIG. 5 is a configuration diagram of a voltage detection circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a high voltage output circuit according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a voltage detection circuit according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram of a high voltage output circuit according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram of a high voltage output circuit and a voltage detection circuit according to a conventional example.

FIG. 10 is a configuration diagram of another voltage detection circuit according to the conventional example.

[Explanation of symbols]

11 ... voltage output circuit, 12 ... Signal detection circuit, 13 ... Dummy field effect transistor for current detection, 14 ... Voltage detection auxiliary element, 14A ... field effect transistor, 14B ... diode, 15 ... Bias element, 16 ... Variable voltage supply means, 17 ... Voltage detecting means, V1 ... the first voltage, V2 ... second voltage, p1 ... voltage detection point, p2, p3 ... connection point, vg1, vg2 ... Gate voltage.

Claims (4)

(57) [Claims] 1. A voltage which is connected between a voltage-detected portion and a ground line and which outputs a second voltage smaller than the first voltage based on a first voltage of the voltage-detected portion. An output circuit and a signal detection circuit that outputs a voltage detection signal according to the second voltage based on the second voltage, and at least a first voltage supply line including the voltage detected section. Either the source electrode or the drain electrode of the first field effect transistor is connected, the well portion of the first field effect transistor is connected to the ground line, and the voltage output circuit and the signal detection circuit are further connected. The voltage detecting circuit is characterized in that the well portion is connected to a connection point for connecting the above, and the breakdown voltage of the first field effect transistor is controlled by the gate voltage. 2. The voltage detection circuit according to claim 1, wherein
A second field effect transistor or a diode is connected between a connection point connecting the voltage output circuit and the signal detection circuit and the voltage detection target part, and the breakdown voltage of the second field effect transistor is a gate voltage. A voltage detection circuit characterized by being controlled by. 3. A diode having a cathode electrically connected to a voltage supply line and an anode electrically connected to a ground line, and a gate electrode formed on a well of opposite conductivity type in a semiconductor substrate of one conductivity type, The well surface on one side of the gate electrode has a one conductivity type impurity diffusion region, and the impurity diffusion region is electrically connected to the cathode of the diode,
Further, the modified field effect transistor having the well electrically connected to the anode of the diode, and the voltage detection signal for controlling the voltage of the voltage supply line based on the voltage are input to the voltage of the anode of the diode. And a signal detection circuit for outputting, wherein the break voltage of the modified field effect transistor is controlled by the gate voltage of the modified field effect transistor. 4. A variable voltage supply means for supplying a voltage to a load circuit, and a voltage detection means for detecting the voltage and outputting a voltage detection signal to the variable voltage supply means, the voltage detection means comprising: A high voltage detection circuit comprising the voltage detection circuit according to any one of items 1 to 3.