JP3384845B2 - Tuning circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel selection circuit for a television or the like.

[0002]

2. Description of the Related Art Conventionally, in a channel selection circuit of a TV or the like, particularly in a channel selection circuit of a TV for a popular machine, in order to select a broadcasting station, the value of a tuning voltage generation counter is converted into an analog value. It is known to supply the signal to the tuner section and control the operation such as counting up, counting down, or stopping the counting in the tuning voltage generation counter based on the AFT voltage from the tuner section.

FIG. 4 shows an example of a conventional tuning circuit. Figure 4
In the figure, reference numeral 17 denotes an up / down counter as a tuning voltage generation counter.
As for the clock No. 7, one kind of clock is selected by the selector 18 from the clocks generated from the clock generation circuits 19 to 22. The frequencies of the clocks supplied by the clock generation circuits 19 to 22 are all different from each other, and the search speed for channel selection can be changed by changing the selection of the clock generation circuit.
By utilizing this fact, a fast clock with a high frequency is selected when the video signal is not detected, that is, detuning, and a slow clock with a low frequency is selected when the video signal is detected, that is, the tuning voltage is driven. It realizes high-speed and reliable tuning operation.

[0004]

However, in the conventional tuning circuit, since the clocks of different frequencies are switched in order to change the search speed of the tuning,
There is a problem that the operation of the logic circuit becomes unstable because the logic circuit does not become a completely synchronous circuit.

Further, since the clock frequency is switched only by detecting or not detecting the video signal, there is a problem that an appropriate search speed cannot be selected in detail.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a tuning circuit capable of improving the stability of operation and selecting the optimum search speed in detail.

[0007]

In order to achieve the above-mentioned object, the invention of claim 1 sets a step width of a digital value of an up-down counter as a tuning voltage generation counter,
It is changed by the presence or absence of a horizontal synchronizing signal, switching between VHF reception and UHF reception, or a control signal from the outside.

[0008] SOLUTION OF THE INVENTION took a specific claim 1, comprising an up-down counter for counting the digital value in synchronization with one clock signal, the digital value outputted from this the up-down counter depending intended for channel selection circuit for performing channel selection, said up-down counter, said every clock before Symbol clock signal Digitally
The variable value from that value by a variable step size
The step width, the presence or absence of the horizontal synchronization signal,
It is configured to switch between VHF reception and UHF reception, or to change by a control signal from the outside.

The invention of claim 2 is specifically, claim 1.
Oite to the configuration of the invention, the up-down counter,
Different from the plurality of incremental feed means Ru is increased by different values of the digital values, the digital value to each other
And a plurality of decrease supply means Ru is decreased by the value, the
A plurality of increasing amount supply means and a plurality of decreasing amount supply means
Select one of the outputs to change the step size
It has a configuration that allows it .

The invention of claim 3 is, specifically, claim 2
Oite to the configuration of the invention, the up-down counter,
A flip-flop for counting a value less than 1 of the digital value is provided, and the plurality of increment supply means are incremented.
The increment of the digital value to be applied and the plurality of decreases
Of the digital value reduced by the minute supply means
At least one size of the two is less than 1.
It

[0011]

According to the structure of the first aspect of the present invention, the search speed for selecting a broadcasting station can be changed by changing the step width of the digital value of the up / down counter. Here, since the count operation of the up / down counter is performed in synchronization with the clock signal of one type of frequency regardless of the change in the step width of the digital value, a complete synchronous circuit can be configured in the logic circuit, The stability can be improved. In addition, the search speed for tuning is set to the presence / absence of the horizontal synchronization signal, VHF reception and UHF.
It can be changed with reception or by a control signal from the outside. Therefore, it is possible to select the optimum search speed in detail.

Further, according to the structure of the invention of claim 2, in the up-down counter, at the time of counting up, it is possible to select an increment supply means having an appropriate increment from a plurality of increment supply means. It is possible to obtain a digital value to which the step width is added, and at the time of countdown, by selecting the decrement supply means having an appropriate decrement from a plurality of decrement supply means, the decrement by the appropriate step width is performed. A digital value can be obtained. As described above, in order to select the optimum search speed, an up / down counter capable of changing the step width of the digital value can be realized with a simple configuration.

Further, according to the configuration of the invention of claim 3, the up-down counter has a flip-flop for counting a value less than 1, so that an increment less than 1 or a decrement less than 1 is performed. Obtainable. Therefore, it is possible to increase or decrease the counter value in units of a value less than 1, which has been impossible in the past, and it is possible to finely adjust the search speed for channel selection.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A channel selection circuit according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the tuning circuit of the first embodiment. In FIG. 1, reference numeral 1 is an up / down counter as a tuning voltage generation counter.
Is converted into an analog voltage by the digital-analog conversion circuit and supplied to the tuner section. Reference numeral 2 denotes a video signal detection circuit, which determines the presence or absence of a video signal. 3 is UHF / which performs switching between UHF reception and VHF reception.
5 shows a VHF switching circuit. A signal from the video signal detection circuit 2, a signal from the UHF / VHF switching circuit 3 and a manual signal from an external pin are selected by the selector 4 and sent to the up / down counter 1. The up / down counter 1 determines the step width of counting based on the selected signal.

FIG. 2 shows a circuit configuration of the up / down counter 1. Here, an example of a 14-bit binary up / down counter is shown. In FIG. 2, 5A is 14
14-bit DF composed of D flip-flops
It is an F block. Reference numerals 6A to 9A denote increment / decrement supply means having both a function as an incrementer (increasing amount supply means) and a function as a decrementer (decreasing amount supply means). For example, it is assumed that the incrementer is selected as the function of the increment / decrement supply means 6A to 9A by the up / down switching pin UP and the up / down counter 1 is set to the up mode. 14-bit DFF block 5A composed of 14 D flip-flops
14 outputs are supplied from the incrementer 6A whose increment amount is “+1” to the incrementer 9A whose increment amount is “+4”. Incrementer 6
The outputs from A to 9A are supplied to the selector 10A, and the output of the selector 10A is supplied to the 14-bit DFF block 5A. As a result, an up / down counter having a variable increment amount is configured. The increment amount is
It is determined by the output of the video signal detection circuit 2, the output of the UHF / VHF switching circuit 3, or the output from the external pin.

The same applies when the up / down counter 1 is set to the down mode.

A channel selection circuit according to a second embodiment of the present invention will be described below with reference to the drawings. The configuration of the channel selection circuit of the second embodiment is the same as that of the first embodiment except for the up / down counter.

FIG. 3 shows a circuit configuration of an up / down counter included in the channel selection circuit of the second embodiment. In FIG.
5B is composed of 16 D flip-flops 16
It is a bit DFF block. The two added D flip-flops are weighted to 1/2 and 1/4, respectively, and only the upper 14 bits are output as the counter output. Reference numerals 6B to 9B are increment / decrement supply means similar to those of the first embodiment having both the function as an incrementer and the function as a decrementer, and 10B is a selector similar to that of the first embodiment. With this configuration, for example, when the up / down counter is set to the up mode, the increment amount becomes 1/4, 1/2, 3/4, 1. As a result, the search speed can be adjusted more finely.

The same applies when the up / down counter is set to the down mode.

[0021]

As described above, according to the tuning circuit of the first aspect of the invention, the step width of the digital value of the up / down counter as the tuning voltage generation counter is changed to select the broadcasting station. The search speed of can be changed. Here, since the count operation of the up / down counter is always performed in synchronization with one type of clock signal, a complete synchronous circuit can be configured and the stability of operation can be improved. In addition, since the search speed for channel selection can be changed by the presence or absence of a horizontal sync signal, switching between VHF reception and UHF reception, or an external control signal, the optimum search speed can be selected in detail. can do.

According to the channel selection circuit of the second aspect of the invention, it is possible to realize an up-down counter capable of changing the step width of the digital value with a simple structure.

Further, according to the channel selection circuit of the invention of claim 3, it is possible to increase / decrease the counter value in units of a value less than 1 which has been impossible in the past, and it is possible to further adjust the search speed of channel selection. It can be done in detail.

As described above, according to the present invention, it is possible to provide a tuning circuit capable of improving the operation stability and selecting the optimum search speed in detail.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a channel selection circuit according to a first example of the present invention.

FIG. 2 is a block diagram showing a configuration of an up / down counter of the channel selection circuit according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of an up / down counter of a channel selection circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional channel selection circuit.

[Explanation of symbols]

1 Up-down counter 2 Video signal detection circuit 3 UHF / VHF switching circuit 4 Selector 5A 14-bit DFF block 5B 16-bit DFF block 6A-9A, 6B-9B Increase / decrease supply means (incrementer, decrementer) 10A, 10B selector

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Obayashi 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) References JP-A-54-120501 (JP, A) JP-A-SHO 54-131809 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/44 H03J 5/02 H03J 7/18

Claims (3)

(57) [Claims] 1. An up-down counter that counts a digital value in synchronization with one type of clock signal is provided , and the digital value output from the up-down counter is converted into a digital value .
A tuning circuit which performs channel selection response Ji, said up-down counter, the digital value for each clock of the previous SL clock signal
It increases or decreases by a variable step width from that value.
Yes, the step width, the presence or absence of the horizontal sync signal, switching between the VHF receiver and UHF reception, or channel selection circuit, characterized in that it is configured to change the control signal from the outside. Wherein said up-down counter is used, the number a plurality of incremental feed means Ru is increased by different values of said digital values, and a plurality of decrease supply means Ru is decreased by different values of said digital values However , the plurality of increment supply means and the plurality of decrement supply hands
Select one of the stage outputs to change the step size.
Channel selection circuit according to claim 1, characterized in that to reduction. Wherein said up-down counter, said digital to the equipped with full <br/> flip-flop for counting the value of less than 1 digital value, the plurality of incremental feed means increases
The increase of the value and the decrease of the plurality of supply means decrease
At least one of the decrements in the digital value
The channel selection circuit according to claim 2 , wherein the magnitude is less than 1 .