JP4323880B2 - Clock signal generating circuit, receiving apparatus, and receiving method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a receiving apparatus that performs digital signal processing based on a received signal, and a technique related to a clock signal generation circuit used in such a receiving apparatus.
[0002]
[Prior art]
  In recent years, with the advancement of digital transmission technology, semiconductor integrated circuit technology, etc., digitalization of broadcasting and communication has been promoted. For example, in a receiving apparatus, control processing for performing various types of control is often performed by a digital circuit, and further, processing such as demodulation necessary for reception is being performed by a digital signal processing circuit. The digital circuit and digital signal processing circuit as described above operate based on a predetermined clock signal. For this reason, the receiving device is provided with, for example, an operation clock signal generating circuit using a crystal oscillator and a timing clock signal generating circuit for generating a timing clock signal based on the received signal.
[0003]
  By the way, the clock signal as described above may cause radiation of electromagnetic waves, fluctuations in power supply voltage, and the like. For this reason, for example, in the receiving apparatus, if the harmonics of the clock signal match or approach the frequency of the received signal, reception interference may be caused and reception performance may be reduced.
[0004]
  As a technique for avoiding such reception interference, a technique is known in which a PLL circuit is provided in a semiconductor integrated circuit constituting a digital circuit. That is, by inputting a relatively low frequency clock signal to the semiconductor integrated circuit and multiplying it internally by a PLL circuit to obtain a desired frequency, the influence of the high frequency clock signal applied to the outside of the semiconductor integrated circuit is affected. (See, for example, Patent Document 1).
[0005]
  Also known are those that reduce the influence of harmonics by changing the frequency of the clock signal by changing the circuit constant of the crystal oscillation circuit or changing the setting of the PLL circuit according to the reception channel. (For example, see Patent Documents 2 and 3).
[0006]
[Patent Document 1]
        JP-A 64-15820
[0007]
[Patent Document 2]
        Japanese Patent Laid-Open No. 5-199155
[0008]
[Patent Document 3]
        JP 2000-341165 A
[0009]
[Problems to be solved by the invention]
  However, in the method of multiplying the frequency of the clock signal inside the semiconductor integrated circuit, although the influence of the high frequency clock signal directly on the outside of the semiconductor integrated circuit can be reduced, the data output from the semiconductor integrated circuit is processed. In addition, the influence of the clock signal output together with the data cannot be prevented.
[0010]
  In the method of changing the frequency of the clock signal, a certain amount of time is required until the operation of the crystal oscillation circuit or the PLL circuit is stabilized, and the frequency and level of the clock signal tend to fluctuate during that time. For this reason, for example, in the receiving apparatus, an appropriate reception operation is not performed until a stable clock signal is obtained, and thus there is a problem that a response time when switching the reception channel becomes long.
[0011]
  In view of the above problems, the present invention can reliably avoid the influence of the clock signal on the received signal or the like even when receiving signals of various channels, and the response time can be changed when the reception channel is switched. It is an object of the present invention to provide a receiving device that can prevent a long time and a clock signal generation circuit that can be used in such a receiving device.
[0012]
[Means for Solving the Problems]
  In order to solve the above problems, the solution taken by the invention of claim 1 is:
  A clock signal generation circuit for generating a burst clock signal having a burst period in which the signal level changes and a blank period in which the signal level does not change,
  A continuous clock signal output circuit for outputting a continuous clock signal whose signal level continuously changes;
  Based on the continuous clock signal, a burst that selectively outputs any one of at least two types of burst clock signals having different frequencies in the burst period and having the same average frequency throughout the burst period and the blank period. A clock signal output circuit;
  With,
  The burst clock signal output circuit is
  Based on the first continuous clock signal which is the continuous clock signal or a signal synchronized therewith and a predetermined burst control signal, a first burst clock signal of the at least two types of burst clock signals is output. A first burst clock signal output circuit;
  A burst period and a blank period based on the second continuous clock signal having a frequency different from that of the first continuous clock signal and the first burst clock signal. A second burst clock signal output circuit that outputs a second burst clock signal of the at least two types of burst clock signals,
  A clock signal selection circuit for selectively outputting one of the first and second burst clock signals;
  It is provided with.
[0013]
  As a result, even if any burst clock signal is selectively output, the average frequency is equal to each other, so that the processing amount of data processing using the burst clock signal can be kept equal, and each burst clock signal Since the frequencies in the burst period are different from each other, the frequency of the harmonic can be easily controlled by selecting one of the burst clock signals.
[0014]
  That is,The same amount of data can be processed for the first burst clock signal generated based on a predetermined burst control signal, and the influence of harmonics can be avoided by different harmonic frequencies. A burst clock signal can be obtained.
[0015]
here,
  The burst clock signal output circuit is configured to generate burst clock signals having different frequencies in the burst period by changing a signal level in synchronization with a rising edge or a falling edge in the same continuous clock signal.do it,The burst clock signal as described above can be easily generated by a digital circuit.You may do.
[0016]
Also,
  The continuous clock signal output circuit is configured to multiply the input clock signal and output the continuous clock signal.do it,Since the frequency of the input clock signal can be lowered and a high-frequency continuous clock signal can be generated only in the vicinity of the circuit that requires the continuous clock signal, the influence of the continuous clock signal on other circuits is reduced. Can be suppressedYou may do.
[0017]
  Also,Claim 2The invention of
  Claim 1A clock signal generating circuit of
  The second burst clock signal output circuit includes:
  Based on the number of clock pulses included in the burst period of the first burst clock signal and the number of clock pulses included in the burst period of the second burst clock signal, the second burst clock signal includes Configure the average frequency throughout the burst period and blank period to be equal to each other by controlling the burst period and blank periodWhich has been
  A first counter for counting the number of clock pulses included in the burst period of the first burst clock signal;
  A second counter for counting the number of clock pulses included in the burst period of the second burst clock signal;
  A comparator for comparing the count values of the first and second counters;
  A burst control circuit for controlling the burst period and the blank period in the second burst clock signal based on the output of the comparator;
  It is provided with.
[0018]
  Also,Claim 3The invention of
  Claim 2A clock signal generating circuit of
  The burst control circuit outputs the second continuous clock signal when the count value of the first counter is larger than the count value of the second counter, while the count value of the first counter When the count value of the second counter is equal, the output of the second continuous clock signal is stopped.
[0019]
  Thus, the second burst clock whose average frequency over the burst period and the blank period is equal to the first burst clock signal as described above by using a counter that counts up or down the number of clock pulses. A signal can be easily generated.
[0020]
  Also,Claim 4The invention of
  A receiving device comprising the clock signal generating circuit according to claim 1,
  The burst clock signal output circuit is configured to selectively output one of the at least two types of burst clock signals according to the frequency of the received signal.,
  The selectively output burst clock signal is a burst clock signal in which an integer multiple of the frequency in the burst period does not match the frequency of the received signal, or an integer multiple of the frequency in the burst period matches the frequency of the received signal, and Harmonics of that frequencyDoes not affect receptionIt is a burst clock signal.
[0021]
  Also,Claim 5The invention of
  Claim 4Receiving device,
  The frequency of each of the at least two types of burst clock signals in the burst period is set so that the frequency of the common multiple thereof is not included in the reception band of the receiving apparatus.
[0022]
  Also,Claim 6The invention of
  Claim 4Receiving device,
  The frequency of each of the at least two types of burst clock signals in the burst period is a frequency that is a common multiple of them and a harmonic of the frequency.Among them, harmonics that affect reception operationIt is set so as not to be included in the reception band of the receiving device.
[0023]
  As described above, the harmonic frequency can be controlled without changing the average frequency throughout the burst period and the blank period as described above, thereby avoiding the influence of the harmonic on the received signal while maintaining the data processing amount. can do. In particular, by setting the frequency in the burst period of each burst clock signal that can be selected as described above, it is possible to select any burst clock signal to receive harmonics regardless of the transmission signal of any frequency. Can be avoided.
[0024]
  Also,Claim 7The invention of
  Claim 1A clock signal generation circuit of
  A demodulation circuit for demodulating the received signal;
  A buffer that temporarily holds the demodulated data output from the demodulation circuit in synchronization with the first burst clock signal, and that outputs the held demodulated data in synchronization with the second burst clock signal;
  A data selection circuit that selectively outputs one of demodulated data output from the demodulation circuit and demodulated data output from the buffer;
  With
  The demodulation circuit performs demodulation processing according to the first burst clock signal,
  The data selection circuit is configured to selectively output demodulated data corresponding to the first or second burst clock signal selected by the clock signal selection circuit.
[0025]
  As a result, the influence of the harmonics of the burst clock signal on the received signal can be suppressed as described above, and demodulated data synchronized with the burst clock signal can be output.
[0026]
  Also,Claim 8The invention of
  Claim 1A clock signal generation circuit of
  A demodulation circuit for demodulating the received signal;
  The pre-demodulation data input to the demodulation circuit based on the received signal is temporarily held in synchronization with the first burst clock signal, and the pre-demodulation data held is synchronized with the second burst clock signal. A buffer to output and input to the demodulation circuit;
  A data selection circuit that selectively outputs either pre-demodulation data input to the buffer and pre-demodulation data output from the buffer;
  With
  The data selection circuit selectively outputs pre-demodulation data corresponding to the first or second burst clock signal selected by the clock signal selection circuit;
  The demodulation circuit is configured to perform a demodulation process based on the first or second burst clock signal selected by the clock signal selection circuit and the pre-demodulation data selected by the data selection circuit. It is characterized by that.
[0027]
  As a result, the influence of the harmonics of the burst clock signal on the received signal is suppressed, and demodulation is performed using such a burst clock signal. Even when the power supply voltage and the ground level fluctuate accordingly, the fluctuation corresponds to the harmonics of the burst clock signal, and the influence on the received signal due to the fluctuation can be easily avoided. .
[0028]
  Also,Claim 9The invention of
  Claims 7 and 8A receiving device according to any one of the above,
  The clock signal selection circuit includes a burst clock signal in which an integer multiple of the frequency in the burst period does not match the frequency of the received signal among the first and second burst clock signals, or an integer multiple of the frequency in the burst period is the received signal. And the harmonics of that frequencyDoes not affect receptionIt is configured to select a burst clock signal.
[0029]
  Thus, as described in the inventions of claims 4 to 6, the harmonic frequency can be controlled without changing the average frequency throughout the burst period and the blank period, while maintaining the data processing amount, The influence of harmonics on the received signal can be avoided. In particular, by setting the frequency in the burst period of each burst clock signal that can be selected as described above, it is possible to select any burst clock signal to receive harmonics regardless of the transmission signal of any frequency. Can be avoided.
[0030]
here,
  The second burst clock signal output circuit includes:
  Based on the number of clock pulses included in the burst period of the first burst clock signal and the number of clock pulses included in the burst period of the second burst clock signal, the second burst clock signal includes Configure the average frequency throughout the burst period and blank period to be equal to each other by controlling the burst period and blank perioddo it,Using a counter or the like that counts up or down the number of clock pulses, the second burst clock signal whose average frequency over the blank period is equal to the first burst clock signal can be generated as described above. Can easilyYou may do.
[0031]
  Also,Claim 10The invention of
  A receiving method for receiving a transmitted signal and outputting demodulated data demodulated based on the received signal and a burst clock signal having a burst period in which the signal level changes and a blank period in which the signal level does not change ,
  Generating a first burst clock signal based on the received signal;
  Depending on the frequency of the received signal, the frequency in the burst period differs from the first burst clock signal or the first burst clock signal, and the average frequency throughout the burst period and the blank period is the same. Selectively output second burst clock signalAnd
  The demodulated data demodulated based on the first burst clock signal is output in synchronism with the selectively output first or second burst clock signal.With
  The selectively output burst clock signal is a burst clock signal in which an integer multiple of the frequency in the burst period does not match the frequency of the received signal, or an integer multiple of the frequency in the burst period matches the frequency of the received signal, and Harmonics of that frequencyDoes not affect receptionIt is a burst clock signal.
[0032]
  Also,Claim 11The invention of
  A receiving method for receiving a transmitted signal and outputting demodulated data demodulated based on the received signal and a burst clock signal having a burst period in which the signal level changes and a blank period in which the signal level does not change ,
  Generating a first burst clock signal based on the received signal;
  Depending on the frequency of the received signal, the frequency in the burst period differs from the first burst clock signal or the first burst clock signal, and the average frequency throughout the burst period and the blank period is the same. Selectively output second burst clock signalAnd
  Output demodulated data demodulated based on the selectively output burst clock signalWith
  The selectively output burst clock signal is a burst clock signal in which an integer multiple of the frequency in the burst period does not match the frequency of the received signal, or an integer multiple of the frequency in the burst period matches the frequency of the received signal, and Harmonics of that frequencyDoes not affect receptionIt is a burst clock signal.
[0033]
  As described above, the influence of the harmonics on the received signal can be avoided while maintaining the processing amount of the data processing using the burst clock signal in the same manner as described for the receiving device.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, as an embodiment of the present invention, an example of a receiving apparatus that receives digital broadcasting will be described with reference to the drawings.
[0035]
  (Embodiment 1)
  First, a mechanism for avoiding reception interference by a clock signal according to the present invention will be briefly described. As shown in FIG. 5, as a timing clock signal indicating the timing synchronized with the demodulated data, any of the two types of signals of timing clock signals A and B corresponding to the reception channel is received from the receiving apparatus of this embodiment. Either one is selectively output. The timing clock signals A and B are burst clock signals in which a period in which a signal level changes, that is, a period in which a clock is included (burst period) and a period in which a clock is not included (blank period) are repeated every predetermined period Td. The frequency of the clock in the burst period is 50 MHz or 40 MHz, respectively. Further, the average frequency (the number of clocks included in the period Td) through the period Td in both is set to be equal. Thus, for example, as shown in FIGS. 7 and 8, when receiving a 21-channel broadcast, a timing clock signal A (50 MHz) is output, whereas when receiving a 26-channel broadcast, a timing clock signal is output. Since B (40 MHz) is output in any case, the harmonics of the timing clock signal in the burst period do not match the frequency of the reception signal, so the influence of the timing clock signal on the reception operation is avoided. Is done. Hereinafter, the receiving apparatus according to the present embodiment will be specifically described.
[0036]
  (Schematic configuration of receiver)
  FIG. 1 is a block diagram showing a configuration of a main part of the receiving apparatus according to Embodiment 1. In FIG. As shown in the figure, the receiving apparatus is provided with a tuner unit 101 and a received signal processing unit 102. The tuner unit 101 receives, for example, an RF (Radio Frequency) signal that is a radio wave of digital broadcasting, and selects and outputs an RF signal having a frequency to be received based on channel information indicating a reception channel. . The reception signal processing unit 102 is configured by, for example, a one-chip semiconductor integrated circuit, demodulates data included in the RF signal based on the RF signal input from the tuner unit 101, and demodulates the demodulated data at a predetermined timing. It is designed to output. Further, a timing clock signal indicating the predetermined timing, that is, a clock signal serving as a reference for processing each part (not shown) of the demodulated data output from the reception signal processing unit 102 is output.
[0037]
  Specifically, the received signal processing unit 102 includes a rate conversion unit 103, a demodulation unit 104, a timing control unit 105, a PLL circuit 106, and a clock generation unit 107.
[0038]
  The rate conversion unit 103 samples (A / D conversion) the RF signal input from the tuner unit 101 based on a sampling clock signal input from the clock generation unit 107, for example, as described later, and converts the RF signal into a digital signal. The sampling rate is converted to match the clock signal on the transmission side. Further, in response to the rate conversion, a burst control signal indicating a distinction between a period in which the clock in the timing clock signal is included and a period in which the clock is not included is output.
[0039]
  Based on the digital signal output from the rate conversion unit 103 and the timing clock signal A output from the clock generation unit 107, the demodulation unit 104 performs demodulation processing according to the modulation method of the received signal, and as a demodulation result, For example, demodulated data A (D [i]: i is an integer) that is 1-bit serial data and the timing clock signal A are output. The timing clock signal A may be a signal obtained by performing various processes on the timing clock signal A input from the clock generation unit 107. Here, for simplicity, the same signal is used as it is without being demodulated data. In the following description, it is assumed that the clock is output as a clock indicating the timing synchronized with the clock.
[0040]
  The timing control unit 105 outputs the timing clock signal A input from the demodulation unit 104 and the demodulated data as they are according to the channel information (that is, the frequency of the received signal), or the timing is adjusted as described later. The timing clock signal B and the demodulated data B that is once held in the buffer and synchronized with the timing clock signal B are output.
[0041]
  The PLL circuit 106 multiplies a clock signal having a predetermined frequency input from the outside, and outputs a reference clock signal of 100 MHz, for example.
[0042]
  The clock generator 107 outputs clock signals for operating the rate converter 103, demodulator 104, and timing controller 105, respectively. A specific configuration of the clock generation unit 107 and each clock signal output to each unit will be described later.
[0043]
  (Configuration of timing control unit 105)
  More specifically, the timing control unit 105 of the received signal processing unit 102 includes, for example, a frequency conversion unit 201, clock number counters 202 and 203, a comparator 204, a burst control unit 205, as shown in FIG. A buffer 206 and selectors 207 and 208 are provided.
[0044]
  The frequency converter 201 generates a clock signal of 40 MHz (a cycle 1.25 times the sampling clock signal) based on a 100 MHz reference clock signal.
[0045]
  The clock number counter 202 counts the number of clocks of the timing clock signal B output from the burst control unit 205 (the number of clock pulses in the burst period).
[0046]
  On the other hand, the clock number counter 203 counts the number of clocks of the timing clock signal A input from the demodulator 104.
[0047]
  The comparator 204 compares the count numbers by the clock number counters 202 and 203. Strictly speaking, since the values that can be counted by the clock number counters 202 and 203 are limited, when the count value returns to 0, an appropriate comparison is performed based on, for example, a carry signal.
[0048]
  Based on the output of the comparator 204, the burst control unit 205 is output from the frequency conversion unit 201 only when the count value (a) of the clock number counter 203 is larger than the count value (b) of the clock number counter 202. The clock signal is output as the timing clock signal B. That is, the value (a) of the clock number counter 203 increases at a timing faster than the value (b) of the clock number counter 202 when the timing clock signal A is in the burst period, and increases when the blank period is reached. Then, when the value (b) of the clock number counter 202 becomes equal to the value (a) of the clock number counter 203, the timing clock signal B is also in a burst period.
[0049]
  The buffer 206 holds the demodulated data A output from the demodulator 104 at a timing based on the timing clock signal A and outputs it at a timing based on the timing clock signal B.
[0050]
  The selector 207 selectively outputs the demodulated data output from the demodulator 104 or the buffer 206 according to the channel information.
[0051]
  The selector 208 selectively outputs the timing clock signals A and B output from the demodulator 104 or the burst controller 205 according to the channel information.
[0052]
  In place of using the clock number counters 202 and 203 and the comparator 204 as described above, for example, an up / down counter that counts up based on the timing clock signal A and counts down based on the timing clock signal B is used. When the count value is larger than “0”, a clock signal output from the frequency conversion unit 201 may be output. In addition, the clock signal output from the frequency conversion unit 201 is output when the accumulated amount of the buffer 206 is not less than a predetermined amount and is not directly based on the timing clock signal A, and is stopped when the amount is less than the predetermined amount. Also good.
[0053]
  (Configuration of Frequency Conversion Unit 201 of Timing Control Unit 105)
  Specifically, for example, as shown in FIG. 3, the frequency conversion unit 201 of the timing control unit 105 includes a counter 301, comparators 302 to 304, D flip-flops 305 to 307 and 310, and a logic inversion circuit 308. 309 and an OR circuit 311 are provided.
[0054]
  The counter 301 includes a D flip-flop 301a that holds a 3-bit value, an incrementer 301b that adds 1 to the value output from the D flip-flop 301a, a value output from the incrementer 301b, or a D flip-flop 301a. Is provided with a logical product circuit 301c for outputting a value “0” for resetting the reference signal, counting the reference clock signal, and successively outputting values “0” to “4” repeatedly.
[0055]
  Each of the comparators 302 to 304 compares the value output from the counter 301 with the value “4”, “0”, or “2”, and outputs an H (High) level signal if they match. It is supposed to be.
[0056]
  The D flip-flops 305 to 307 hold the outputs from the comparators 302 to 304 in synchronization with the rising timing of the reference clock signal.
[0057]
  The output of the D flip-flop 305 is inverted by the logic inversion circuit 308 and input to the AND circuit 301c. That is, every time the value “4” is output from the counter 301 (logical product circuit 301c), the logical product circuit 301c outputs the value “0” at the next rising timing in the reference clock signal.
[0058]
  On the other hand, the outputs of the D flip-flops 306 and 307 are input to the OR circuit 311 directly or via the D flip-flop 310, respectively.
[0059]
  The D flip-flop 310 holds the output of the D flip-flop 307 in accordance with the signal obtained by inverting the reference clock signal by the logic inverting circuit 309, that is, in synchronization with the falling timing of the reference clock signal. .
[0060]
  The OR circuit 311 outputs a logical sum of the outputs of the D flip-flop 306 and the D flip-flop 310.
[0061]
  (Configuration of clock generation unit 107)
  The clock generation unit 107 (FIG. 1) of the reception signal processing unit 102 includes a frequency divider 107a and a timing clock generation unit 107b as shown in FIG. 4, for example. The frequency divider 107a divides the reference clock signal multiplied by the PLL circuit 106 by 2 and outputs it as a sampling clock signal.
[0062]
  Also, the timing clock generator 107b is based on the burst control signal generated by the rate converter 103 in accordance with the conversion of the sampling rate, and only the clock signal having the burst period and the blank period, that is, the burst period 2 A timing clock signal A from which the divided sampling clock signal is output is output. Based on the timing clock signal A, the demodulator 104 performs demodulation processing on the data after the sampling rate conversion.
[0063]
  The clock generator 107 further outputs the reference clock signal input from the PLL circuit 106 to the timing controller 105 as it is.
[0064]
  (Receiver operation)
  The operation of the receiving apparatus configured as described above will be described. FIG. 5 is a timing chart showing the timing of each part of the receiving apparatus.
[0065]
  When a clock signal having a predetermined frequency is input to the PLL circuit 106, the PLL circuit 106 multiplies the clock signal and outputs a reference clock signal of 100 Mz, for example. The frequency divider 107a of the clock generation unit 107 divides the reference clock signal by 2 and outputs a 50 MHz sampling clock signal.
[0066]
  The rate conversion unit 103 samples the RF signal input from the tuner unit 101 based on the sampling clock signal, further converts the sampling rate, and outputs the digital data to the demodulation unit 104. Further, according to the rate conversion, a burst control signal that changes to H (high) level or L (Low) level at the timing synchronized with the sampling clock signal is output to the clock generation unit 107.
[0067]
  The timing clock generation unit 107b of the clock generation unit 107 outputs a timing clock signal A having a burst period and a blank period in accordance with the burst control signal. That is, when the burst control signal becomes L level, the 50 MHz sampling clock signal output from the frequency divider 107a is output (burst period), while when the burst control signal becomes H level, the output of the timing clock generator 107b. Is maintained at the L level (blank period). Although not particularly limited, in FIG. 5, in consideration of a circuit delay or the like in the clock generation unit 107, the burst control signal level is changed until the burst period or the blank period is reached. An example in which a delay of one clock of the sampling clock signal occurs is shown.
[0068]
  Based on the timing clock signal A, the demodulator 104 demodulates the digital data output from the rate converter 103, and outputs demodulated data A and the timing clock signal A.
[0069]
  The timing control unit 105 is output from the timing clock signal A and the demodulated data A or the burst control unit 205 and the buffer 206 according to selection by the selectors 207 and 208 (FIG. 2) according to the channel information indicating the reception channel. Timing clock signal B and demodulated data B are output. The timing clock signal B and the demodulated data B are generated in detail as follows.
[0070]
  First, the frequency conversion unit 201 outputs a 40 MHz frequency conversion clock based on the 100 MHz reference clock signal input from the clock generation unit 107. More specifically, as shown in FIG. 6, the counter 301 (FIG. 3) repeatedly outputs values “0” to “4” that are counted up every rising edge of the reference clock signal. That is, the incrementer 301b increments the value output from the D flip-flop 301a, and the incremented value is held in the D flip-flop 301a via the AND circuit 301c for each rising edge of the reference clock signal. Further, every time the value output from the AND circuit 301c becomes “4”, the output of the comparator 302 becomes H level, and at the rising edge of the next reference clock signal, the output of the D flip-flop 305 becomes H level. The signal input from the logical inversion circuit 308 to the logical product circuit 301c becomes L level, the value output from the logical product circuit 301c becomes "0" (reset), and the next reference clock signal The above-mentioned value “0” is held in the D flip-flop 301a at the rising edge.
[0071]
  The output of the AND circuit 301c of the counter 301 is also input to the comparator 303 and the comparator 304. The comparator 303 becomes H level every time the value becomes “0”, and the next reference clock is output. The output of the D flip-flop 306 becomes H level at the rising edge of the signal. The comparator 304 becomes H level whenever the output of the counter 301 becomes “2”, and the output of the D flip-flop 307 becomes H level at the rising edge of the next reference clock signal. At the falling edge of the clock signal (the rising edge of the output of the logic inversion circuit 309), the output of the D flip-flop 310 becomes H level. That is, the output of the D flip-flop 306 becomes H level every 5 clocks of the reference clock signal, and the output of the D flip-flop 310 becomes H level at a timing delayed by 2.5 clocks from the above. Therefore, from the OR circuit 311, a 40 MHz (period is 1.25 times) frequency conversion clock signal that is H level only four times is output while the 50 MHz sampling clock signal is H level five times. .
[0072]
  The frequency conversion clock signal is input to the burst control unit 205 (FIG. 2), and the timing clock signal B is generated according to the output of the comparator 204 that compares the outputs of the clock number counters 202 and 203. Specifically, for example, if the initial values of the clock number counters 202 and 203 are equal, the output of the clock number counter 203 when the clock pulse is input to the clock number counter 203 during the burst period of the timing clock signal A. Is incremented and a> b, so that the output of the comparator 204 becomes H level, and the burst control unit 205 outputs the frequency conversion clock signal output from the frequency conversion unit 201 as the timing clock signal B as it is. (The timing clock signal B also has a burst period). Therefore, although the output of the clock number counter 202 is also incremented, since the frequency of the timing clock signal A is higher, the state of a> b is continued. Thereafter, when the timing clock signal A enters a blank period, the output of the clock number counter 203 does not change, but the increment of the output of the clock number counter 202 continues. When a = b is reached, the output of the comparator 204 becomes L The output of the burst control unit 205 is maintained at the L level, and the timing clock signal B also enters a blank period.
[0073]
  The buffer 206 sequentially holds the demodulated data A output from the demodulator 104 at a timing based on the timing clock signal A, and is output from the buffer 206 as demodulated data B at a timing based on the timing clock signal B. Is done.
[0074]
  As described above, the timing clock signals A and B have a clock frequency in the burst period of 50 MHz or 40 MHz, respectively (where the clock period of the timing clock signal A is T, the clock period of the timing clock signal B is Is T × 1.25). On the other hand, the number of clocks (the number of rises or falls) in the burst period is equalized by the control based on the counts of the clock number counters 202 and 203 as described above. That is, in the example of FIG. 5, for example, the number of clocks in the burst period corresponding to the four data D [i] to D [i + 3] is four, so that the total period Td of the burst period and the blank period is passed through. The average frequency is equal to each other (1 / Td) × 4. Therefore, regardless of which of the timing signal A and the demodulated data A or the timing signal B and the demodulated data B is selected by the selectors 207 and 208, the average data of the demodulated data output from the receiving device The throughput is kept the same.
[0075]
  Here, in the spectrum of the timing clock signals A and B, power concentrates on the clock frequency f in the burst period and the harmonic frequency f × n (n is an integer satisfying n ≧ 2). Therefore, for example, when receiving a UHF band 21-channel or 27-channel broadcast in Japanese terrestrial television broadcasting, as described at the beginning, when receiving a 21-channel broadcast, the timing clock signal A (50 MHz) is generated. On the other hand, the timing clock signal B (40 MHz) is output when the 26-channel broadcast is received, so that in either case, as shown in FIGS. The harmonics of the timing clock signal in the period do not coincide with the frequency of the reception signal, and the influence of the timing clock signal on the reception operation is avoided.
[0076]
  Specifically, the frequency band of the 21 channel is 518 MHz to 524 MHz, and the harmonic frequencies for the clock frequency of 50 MHz in the vicinity thereof are 10th order f × 10 = 500 MHz and 11th order f × 11 = 550 MHz, Since none of them overlaps the band of the received signal, the received signal is not affected.
[0077]
  The frequency band of 26 channels is 548 MHz to 554 MHz, and the frequency of the harmonics with respect to the clock frequency of 40 MHz in the vicinity thereof is 13th order f × 10 = 520 MHz and 14th order f × 14 = 560 MHz. Since it does not overlap the band of the received signal, it does not affect the received signal.
[0078]
  Here, if a timing clock signal opposite to the above is used, the reception band of 518 MHz to 524 MHz overlaps the frequency 520 MHz of the 13th harmonic of 40 MHz, or the reception band of 548 MHz to 554 MHz is the 11th order of 50 MHz. Since the harmonic frequency of 550 MHz overlaps, reception interference occurs due to interference with the received signal, but as described above, the timing clock signal (and demodulated data synchronized therewith) is selectively switched according to the channel information. As a result, interference with the received signal due to harmonics can be avoided.
[0079]
  In addition, as described above, the clock frequency of the burst period is different, but the period of time during which the clock is not output is controlled, and two types of signals having the same average frequency are used, so that processing performed using these timing clock signals is performed. Processing power is kept equal. Further, the above two types of timing clock signals (and demodulated data synchronized therewith) are generated in advance based on a reference clock signal having a constant frequency and switched to be input to the received signal processing unit 102. Since it is not necessary to change the frequency of the clock signal or the multiplication factor of the PLL circuit 106, a stable oscillation state can be maintained. Therefore, even when the reception channel is switched, reception of a new channel can be performed with almost no response time. In addition, by generating the two types of timing clock signals as described above by digital processing using the rising timing and falling timing of the reference clock signal, these timing clock signals can be obtained reliably and the timing adjustment can be performed. Simplification, design simplification (reduction of design margin in consideration of variation, etc.) can be achieved.
[0080]
  (Embodiment 2)
  FIG. 9 is a block diagram showing a configuration of a main part of the receiving apparatus according to the second embodiment. In the second embodiment, components having the same functions as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0081]
  The reception signal processing unit 402 of this reception device is different from the reception signal processing unit 102 (FIG. 1) of the reception device of the first embodiment in the flip-flop 404 between the rate conversion unit 103 and the demodulation unit 104. The difference is that a timing control unit 105 is provided. The flip-flop 404 temporarily holds the digital data output from the rate conversion unit 103 based on the timing clock signal A output from the clock generation unit 107.
[0082]
  Although not demodulated data but digital data output from the flip-flop 404 is input to the timing control unit 105, the operation is the same as that of the first embodiment. That is, based on the channel information, the input data is output as it is or is output after being held in the buffer 206, and the timing clock signal A input from the flip-flop 404 is output as it is, or internally. Whether to output the generated timing clock signal B is switched.
[0083]
  The operation of the demodulator 104 is the same as that of the first embodiment, but the operation timing is controlled based on the timing clock signals A and B selectively output from the timing controller 105. Since the digital data input to the demodulator 104 is via the flip-flop 404, the demodulator 104 may be replaced with the input stage flip-flop omitted. Furthermore, some processing in the demodulation unit 104 may be performed before the timing control unit 105.
[0084]
  As described above, the timing controller 105 is provided in front of the demodulator 104, and the demodulator 104 is operated by the timing clock signals A and B corresponding to the reception channel, so that a clock having a fixed frequency regardless of the reception channel. Since it is possible to suppress the number of parts that operate with signals, it is possible to more easily suppress reception interference caused by (timing) of the timing clock signal. Furthermore, if the circuit scale of the demodulator 104 is large, fluctuations in power supply voltage and ground level are likely to occur. However, reception interference due to the influence of the demodulator 104 also causes the demodulator 104 to operate based on the timing clock signal selected as described above. This can be easily avoided.
[0085]
  In the above example, two types of timing clock signals A and B of 50 MHz or 40 MHz are selectively used. However, the present invention is not limited to the above frequency, and three or more types of timing clock signals are used. It may be used. That is, the harmonic frequency of each timing clock signal matches the frequency that is equal to the common multiple of the frequency of each timing clock signal, so that, for example, the frequency of the least common multiple is higher than the highest reception frequency of the receiver. If the frequency of the common multiple does not fall within the reception band of the receiver, such as by selecting one of the timing clock signals, the influence of the harmonics must be avoided when receiving any channel. Can do. In general, the higher the order is, the lower the harmonic power is. Therefore, considering this point, even if the frequency of the common multiple is within the reception band, it should be at least higher than the order that affects reception interference. That's fine.
[0086]
  In addition, the selection of the timing clock signal is not limited to the selection based on the reception channel (channel information) as described above, and there is no influence of reception interference based on information related to reception quality such as a bit error rate. Alternatively, it may be selected to be within an allowable range (or minimum). Such a configuration is particularly effective when the harmonic spectrum is not concentrated on the theoretical harmonic frequency.
[0087]
  Further, as described above, by using the rising timing and falling timing of the 100 MHz reference clock signal in order to generate the 40 MHz frequency conversion clock signal, the frequency of the reference clock signal is generally kept low or the circuit scale is reduced. However, the present invention is not limited to this. For example, only one of rising timing and falling timing of a faster clock signal may be used. Further, by adjusting the L level period in the frequency conversion clock signal, the frequency conversion clock signal of 40 MHz is not necessarily obtained, but the H level period may be adjusted, or both the H and L levels may be adjusted. The duty ratio may be maintained at 1: 1 by adjusting the period.
[0088]
  In addition, although it has been described that the reception signal processing unit 102 is configured by a one-chip semiconductor integrated circuit, the present invention is not limited to this. That is, when configured as described above, the influence of signals other than the timing clock signal output from the reception signal processing unit 102 (for example, the sampling clock signal) on the circuit outside the reception signal processing unit 102 is reduced. Although it can be easily suppressed, even if the received signal processing unit 102 is configured by a plurality of semiconductor integrated circuits, it can be suppressed by a mounting technique or the like. It is not an essential problem. The provision of the PLL circuit 106 in the reception signal processing unit 102 is advantageous in reducing the influence of the reference clock signal, but is not limited thereto.
[0089]
【The invention's effect】
  As described above, according to the present invention, a plurality of timing clock signals having a burst period in which a clock signal is included and a blank period in which the clock signal is not included and having different clock signal frequencies in the burst period are received. By selectively using according to the frequency, it is possible to avoid the influence of the harmonics of the clock signal on the received signal. In addition, since a plurality of timing clock signals as described above are generated based on a clock signal having a fixed frequency, the response time does not take long when the reception channel is switched.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a main part of a receiving apparatus according to Embodiment 1;
FIG. 2 is a block diagram showing a configuration of a timing control unit 105. FIG.
3 is a block diagram showing the configuration of a frequency conversion unit 201. FIG.
4 is a block diagram showing a configuration of a clock generation unit 107. FIG.
FIG. 5 is a timing chart showing the operation of the timing control unit 105;
6 is a timing chart showing the operation of the frequency conversion unit 201. FIG.
7 is an explanatory diagram showing the relationship between the harmonic frequency of the timing clock signal A and the frequency of the received signal. FIG.
FIG. 8 is an explanatory diagram showing the relationship between the harmonic frequency of the timing clock signal B and the frequency of the received signal.
9 is a block diagram showing a configuration of a main part of a receiving apparatus according to Embodiment 2. FIG.
[Explanation of symbols]
        101 Tuner
        102 Received signal processor
        103 Rate converter
        104 Demodulator
        105 Timing controller
        106 PLL circuit
        107 Clock generator
        107a divider
        107b Timing clock generator
        201 Frequency converter
        202/203 clock counter
        204 Comparator
        205 Burst controller
        206 buffers
        207/208 selector
        301 counter
        301a D flip-flop
        301b Incrementer
        301c AND circuit
        302-304 comparator
        305-307 ・ 310 D flip-flop
        308/309 logic inversion circuit
        311 OR circuit
        402 Received signal processor
        404 flip-flop

Claims (11)

A clock signal generation circuit for generating a burst clock signal having a burst period in which the signal level changes and a blank period in which the signal level does not change,
A continuous clock signal output circuit for outputting a continuous clock signal whose signal level continuously changes;
Based on the continuous clock signal, a burst that selectively outputs any one of at least two types of burst clock signals having different frequencies in the burst period and having the same average frequency throughout the burst period and the blank period. A clock signal output circuit;
Equipped with a,
The burst clock signal output circuit is
Based on the first continuous clock signal which is the continuous clock signal or a signal synchronized therewith and a predetermined burst control signal, a first burst clock signal of the at least two types of burst clock signals is output. A first burst clock signal output circuit;
A burst period and a blank period based on the second continuous clock signal having a frequency different from that of the first continuous clock signal and the first burst clock signal. A second burst clock signal output circuit that outputs a second burst clock signal of the at least two types of burst clock signals,
A clock signal selection circuit for selectively outputting one of the first and second burst clock signals;
A clock signal generation circuit comprising: The clock signal generation circuit according to claim 1 ,
The second burst clock signal output circuit includes:
Based on the number of clock pulses included in the burst period of the first burst clock signal and the number of clock pulses included in the burst period of the second burst clock signal, the second burst clock signal includes By controlling the burst period and the blank period, the average frequency throughout the burst period and the blank period is configured to be equal to each other ,
A first counter for counting the number of clock pulses included in the burst period of the first burst clock signal;
A second counter for counting the number of clock pulses included in the burst period of the second burst clock signal;
A comparator for comparing the count values of the first and second counters;
A burst control circuit for controlling the burst period and the blank period in the second burst clock signal based on the output of the comparator;
A clock signal generation circuit comprising: The clock signal generation circuit according to claim 2 ,
The burst control circuit outputs the second continuous clock signal when the count value of the first counter is larger than the count value of the second counter, while the count value of the first counter A clock signal generation circuit configured to stop outputting the second continuous clock signal when the count value of the second counter is equal. A receiving device comprising the clock signal generating circuit according to claim 1 ,
The burst clock signal output circuit is configured to selectively output one of the at least two types of burst clock signals according to the frequency of the received signal ;
The selectively output burst clock signal is a burst clock signal in which an integer multiple of the frequency in the burst period does not match the frequency of the received signal, or an integer multiple of the frequency in the burst period matches the frequency of the received signal, and A receiving apparatus, wherein a harmonic of the frequency is a burst clock signal that does not affect the receiving operation . The receiving device according to claim 4 ,
The frequency of each of the at least two types of burst clock signals in the burst period is set so that frequencies of their common multiples are not included in the reception band of the reception device. The receiving device according to claim 4 ,
The frequency in each burst period of the at least two types of burst clock signals is a frequency that is a common multiple of them, and among the harmonics of the frequencies, harmonics that affect the reception operation are included in the reception band of the receiver. It is set so that it may not be received. A clock signal generation circuit according to claim 1 ;
A demodulation circuit for demodulating the received signal;
A buffer that temporarily holds the demodulated data output from the demodulation circuit in synchronization with the first burst clock signal, and that outputs the held demodulated data in synchronization with the second burst clock signal;
A data selection circuit that selectively outputs one of demodulated data output from the demodulation circuit and demodulated data output from the buffer;
With
The demodulation circuit performs demodulation processing according to the first burst clock signal,
The receiving apparatus, wherein the data selection circuit is configured to selectively output demodulated data corresponding to the first or second burst clock signal selected by the clock signal selection circuit. A clock signal generation circuit according to claim 1 ;
A demodulation circuit for demodulating the received signal;
The pre-demodulation data input to the demodulation circuit based on the received signal is temporarily held in synchronization with the first burst clock signal, and the pre-demodulation data held is synchronized with the second burst clock signal. A buffer to output and input to the demodulation circuit;
A data selection circuit that selectively outputs either pre-demodulation data input to the buffer and pre-demodulation data output from the buffer;
With
The data selection circuit selectively outputs pre-demodulation data corresponding to the first or second burst clock signal selected by the clock signal selection circuit;
The demodulation circuit is configured to perform demodulation processing based on the first or second burst clock signal selected by the clock signal selection circuit and the pre-demodulation data selected by the data selection circuit. A receiving apparatus. A receiving device according to any one of claims 7 and 8 , comprising:
The clock signal selection circuit includes a burst clock signal in which an integer multiple of the frequency in the burst period does not match the frequency of the received signal among the first and second burst clock signals, or an integer multiple of the frequency in the burst period is the received signal. A receiving device configured to select a burst clock signal that matches the frequency of the received signal and whose harmonics do not affect the receiving operation . A receiving method for receiving a transmitted signal and outputting demodulated data demodulated based on the received signal and a burst clock signal having a burst period in which the signal level changes and a blank period in which the signal level does not change ,
Generating a first burst clock signal based on the received signal;
Depending on the frequency of the received signal, the frequency in the burst period differs from the first burst clock signal or the first burst clock signal, and the average frequency throughout the burst period and the blank period is the same. Selectively outputting a second burst clock signal ;
The demodulated data demodulated based on the first burst clock signal is output in synchronization with the selectively output first or second burst clock signal ,
The selectively output burst clock signal is a burst clock signal in which an integer multiple of the frequency in the burst period does not match the frequency of the received signal, or an integer multiple of the frequency in the burst period matches the frequency of the received signal, and A receiving method, wherein a harmonic of the frequency is a burst clock signal that does not affect the receiving operation . A receiving method for receiving a transmitted signal and outputting demodulated data demodulated based on the received signal and a burst clock signal having a burst period in which the signal level changes and a blank period in which the signal level does not change ,
Generating a first burst clock signal based on the received signal;
Depending on the frequency of the received signal, the frequency in the burst period differs from the first burst clock signal or the first burst clock signal, and the average frequency throughout the burst period and the blank period is the same. Selectively outputting a second burst clock signal ;
While outputting demodulated data demodulated based on the selectively output burst clock signal ,
The selectively output burst clock signal is a burst clock signal in which an integer multiple of the frequency in the burst period does not match the frequency of the received signal, or an integer multiple of the frequency in the burst period matches the frequency of the received signal, and A receiving method, wherein a harmonic of the frequency is a burst clock signal that does not affect the receiving operation .

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