JP3384375B2 - Driving method and driving device for liquid crystal display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a driving device for a liquid crystal display device, and more particularly to a driving method and a driving device suitable for driving a liquid crystal display device with low power consumption.

[0002]

2. Description of the Related Art In a liquid crystal display device, when a data line of a liquid crystal panel is driven by a horizontal driver IC which is a driving device, as shown in FIG. 8, n-bit, for example, 8-bit digital data signals D1 to D8 are generated. Based on the ROM decoder 10, a gray scale voltage V1 of 256 gray scales, which is 2 to the 8th gray scale,
One of V256 to V256 is selected as the output Vx from the ROM decoder 10, the driving capability is increased by the voltage follower connection operational amplifier 20, and the driving voltage Vo is output from the output terminal 30 to the data line. Has been.

As the drive voltage Vo described above, a positive voltage and a negative voltage with respect to the voltage of the common electrode must be alternately applied to each pixel for each pixel because of the characteristic of the liquid crystal. For example, when applying a positive voltage as the drive voltage Vo to the data line,
8 bit digital data signals D1 to D
In the PROM decoder 10P based on No. 8, one of 256 positive gradation voltages VP1 to VP256 is a ROM.
A positive drive voltage V is selected from the output terminal 30 via the operational amplifier 20P selected as the output VPx from the decoder 10P.
It is output to the data line as Po. Also, 2 on the data line
When applying a negative voltage of 56 gradations, as shown in FIG. 10, the NROM decoder 10N outputs negative gradation voltages VN1 to VN256 of 256 gradations based on 8-bit digital data signals D1 to D8. One is ROM decoder 1
The operational amplifier 20 selected as the output VNx from 0N
A negative drive voltage VNo is output to the data line from the output terminal 30 via N.

As shown in FIG. 11, the PROM decoder 10P includes a P-type first transistor 1P, which is a MOS transistor, and a P-type second transistor 2P, which is always turned on by short-circuiting a source and a drain, at predetermined positions. The matrix is arranged in 256 rows and 16 columns. In each row, a transistor series 1P and a transistor 2P are connected in series to form a pair, and eight more pairs are combined to form a transistor series circuit 3P. Each pair of each row has a gate column 4Pa in which one gate (left side in the drawing) of each pair of transistors is commonly connected to each column, and another gate (right side in the drawing) to which each gate is commonly connected in each column. Row 4P
and b form a gate column pair 4P. On one end side (the left side in the drawing) of each transistor series circuit 3P, a positive gradation voltage VP of 256 gradations is output from a gradation voltage generating circuit (not shown).
1 to VP256 are supplied respectively. Each gate row pair 4
P is an 8-bit digital data signal D corresponding to the data line of the liquid crystal display panel from the preceding circuit in the driver IC.
, D1 (D8 is the higher-order bit side) is the positive phase D from the first column (left side in the drawing) to the eighth column of the gate column 4Pa.
P8, DP7, ..., DP1 are supplied to the gate row 4Pb.
, DP1 bar from the first column (on the left side in the drawing) to the eighth column. The other end side (right side in the drawing) of each transistor series circuit 3P is commonly connected, and the positive gradation voltage VP1 to the operational amplifier 20P.
8-bit digital data signal D1 of VP256
One corresponding to D8 is output from the PROM decoder 10P as the output VPx.

As shown in FIG. 12, the NROM decoder 10N includes an N-type first transistor 1N, which is a MOS transistor, and a P-type second transistor 2N, which is always on by short-circuiting the source and the drain, at a predetermined position.
The matrix is arranged in 56 rows and 16 columns. Each row has a pair of transistors 1N and 2N connected in series, and eight pairs of them are combined to form a transistor series circuit 3N. Each pair of each row has a gate column 4Na in which one gate (left side in the drawing) of each pair of transistors is commonly connected to each column, and another gate (right side in the drawing) of each pair is commonly connected to each column. The row 4Nb forms a gate row pair 4N. On one end side (on the left side in the drawing) of each transistor series circuit 4N, a negative gradation voltage VN1 of 256 gradations is output from a gradation voltage generating circuit (not shown).
VN256 is supplied respectively. Each gate column pair 4N has an 8-bit digital data signal DN8, which corresponds to the data line of the liquid crystal display panel from the preceding circuit in the driver IC.
DN7 is a positive phase DN8, DN7, ..., DN from the first column (left side in the drawing) to the eighth column of the gate column 4Na.
1, and the reverse phase DN8 bar, DN7 bar, ..., D from the first column (left side in the drawing) to the eighth column of the gate column 4Nb.
Supplied at N1 bar. The other end side (right side in the drawing) of each transistor series circuit 3N is commonly connected, and the operational amplifier 2
One of the negative gradation voltages VN1 to VN256 corresponding to 0N corresponds to 8-bit digital data signals D1 to D8.
It is output as the output VNx from the ROM decoder 10N.

The operations of the PROM decoder 10P and the NROM decoder 10N having the above configurations will be described. The gradation voltages VP1 to VP256 and VN1 to VN256 of 256 gradations are applied to one end side of each transistor series circuit 3P, 3N. In this state, predetermined data signals DP8, DP7, ... Of "1 (high level)" or "0 (low level)"
DP1, DN8, DN7, ..., DN1 are gate rows 4P
The positive phase DP8, DP in the first to eighth columns of a, 4Na
, ..., DP1, DN8, DN7, ..., DN1 respectively, and the first to eighth gate columns 4Pb and 4Nb.
Reverse phase DP8 bar, DP7 bar, ..., DP1 bar in the row
When supplied by DN8 bar, DN7 bar, ..., DN1 bar, all the transistors 1P, 1N of one selected transistor series circuit 3P, 3N among the transistor series circuits 3P, 3N are in the ON state (transistor 2P, 2N is always on), and the gradation voltage applied to the transistor series circuits 3P and 3N is VP.
x, VNx.

[0007]

By the way, as described above, when a positive voltage and a negative voltage are alternately applied to the common voltage for each pixel as the drive voltage of the liquid crystal panel, the waveform of the drive voltage is a negative voltage. From the positive voltage rising waveform and from the positive voltage to the negative voltage falling waveform. The rising and falling waveforms are required to have a steep slope in order to write the liquid crystal panel normally. The rising and falling waveforms are
When the bias current of the MOS transistor included in the operational amplifier is constant, as the liquid crystal panel becomes larger and the load becomes larger, the slope becomes gentle as shown in the example of the rising waveform in FIG. Therefore, in order to write normally in the liquid crystal panel, it is necessary to increase the bias current of the MOS transistor included in the operational amplifier as the load of the liquid crystal panel increases, which causes a problem that the current consumption increases. It was Therefore, the present invention has been made to solve the above-mentioned problems, and a voltage for urging the rising and falling slopes in a steep direction at the rising and falling of the waveform of the driving voltage is set to R.
An object of the present invention is to provide a driving method and a driving device for a liquid crystal display device in which an OM decoder directly supplies the output side of an operational amplifier without passing through the operational amplifier.

[0008]

(1) According to a method of driving a liquid crystal display device of the present invention, an n of 2 is used as a drive voltage of a data line of a liquid crystal panel to be driven based on an n-bit digital data signal. In the driving method of a liquid crystal display device, wherein one gradation voltage of the gradation voltages of the multiplicative gradation is selected by a ROM decoder and the driving capability is increased by an operational amplifier connected to a voltage follower, and then output. At the rising and falling edges of one of the n-th power gradation voltages based on the digital data signal, one gradation voltage for urging the rising and falling slopes in a steep direction is set. It is characterized in that it is selected by the ROM decoder with low impedance and is directly supplied to the output side of the operational amplifier. (2) In the method of driving a liquid crystal display device according to the present invention, in the above item (1), the grayscale voltage selected with the low impedance is selected based on upper m bits of the digital data signal. Is characterized by. (3) A driving device for a liquid crystal display device according to the present invention includes a ROM decoder for selecting one of grayscale voltages of 2n grayscales based on an n-bit digital data signal, and a ROM decoder. In a driving device of a liquid crystal display device, comprising: a voltage follower-connected operational amplifier that outputs a selected grayscale voltage to a data line of a liquid crystal panel to be driven with an increased driving capability, At the rising and falling edges of one of the n-th power grayscale voltages based on the digital data signal, one grayscale voltage that biases the rising and falling slopes in a steep direction is lowered. It is characterized in that it is selected by impedance and is directly supplied to the output side of the operational amplifier. (4) In the driving device of the liquid crystal display device according to the present invention, in (3) above, the grayscale voltage selected with the low impedance is selected based on the upper m bits of the digital data signal. Is characterized by. (5) In the drive device for a liquid crystal display device according to the present invention, in the above-mentioned item (4), the ROM decoder forms a pair of two first transistors that can be ON / OFF controlled and second transistors that are always on. There are n pairs of 2n columns, and both transistors are arranged in a matrix of 2 n rows and 2n columns, and each row has a transistor series circuit in which the transistors are connected by a source and a drain, and one of the pairs The gates of the transistors are commonly connected in each column, and the gates of the other transistors are commonly connected in each column. One end is connected to each gradation voltage of the nth power of 2 and each other end of each transistor series circuit is commonly connected and connected to the input of the operational amplifier. Both, RO said the one gate array connected to the other gate array to the positive phase of the digital data signals are connected to the opposite phase of the digital data signal
It is characterized by comprising an M decoder. (6) In the driving device of the liquid crystal display device according to the present invention, in the above-mentioned item (5), the ROM decoder is arranged so that among the n pairs of gate row pairs, a gate row pair to which data of upper m bits is supplied. A third n-th power transistor series circuit capable of on / off control for each (2−m) th power
A pair of a transistor and a normally-on fourth transistor is arranged in the same gate column as the third transistor and the second transistor, and the fourth transistor and the second transistor are respectively arranged in the same gate row. And a second transistor series circuit connected with each other, one end of each of the second transistor series circuits is connected to one of the grayscale voltages corresponding to each of the (n−m) th powers of 2 respectively. The other end of the two-transistor series circuit is commonly connected and connected to the output of the operational amplifier. (7) The driving device of the liquid crystal display device according to the present invention is the operational device described in the above item (3). The ROM decoder connected to the rising operational amplifier, wherein the amplifier comprises a rising operational amplifier and a falling operational amplifier. Da is PROM decoder, the ROM decoder connected to said fall operational amplifier is characterized in that it is a NROM decoder. (8) The driving device of the liquid crystal display device according to the present invention is the operational amplifier according to the above item (3), in which the operational amplifier outputs both a rising waveform and a falling waveform, and the ROM decoder is a PROM decoder and an NROM.
A decoder and an operational amplifier are alternately connected to the operational amplifier.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION A driving method for driving a data line of a liquid crystal panel in a liquid crystal display device according to the present invention will be described below. As shown in FIG. 1, as n bits,
For example, based on the 8-bit digital data signals D1 to D8, the ROM decoder 11 has 256 gray scales of 2 8
One of the grayscale voltages V1 to V256 of the grayscale is selected as the output Vx1 from the ROM decoder 11, and the driving capability is increased by the operational amplifier 20 of the voltage follower connection to obtain the driving voltage Vo from the output terminal 30 to the data line. In addition to outputting the grayscale voltage Vx1 as the drive voltage Vo via the operational amplifier 20, the drive voltage Vo rises from a negative voltage to a positive voltage and from a positive voltage to a negative voltage. A voltage for urging the rising and falling slopes in a steep direction at the time of falling is directly supplied to the output side of the operational amplifier 20 as the output Vx2 from the ROM decoder 11 without passing through the operational amplifier 20 with a low impedance.

This output Vx2 is the upper m bits of the n-bit digital data signal, in the present embodiment, 8-bit digital data signals D1 to D8 (D8 is the upper bit side).
, For example, based on the upper 2 bits D8 and D7, output from the ROM decoder 11 as follows. Based on 8-bit digital data signals D1 to D8, gradation voltages V1 to V1
When one of V256 is selected as the output Vx1, the upper 2 bits of the 8-bit digital data signals D1 to D8 are selected.
When the bits D8 and D7 are "00", the 1st to 64th gradation voltages V1 to V64, and when they are "01", the 65th to 1st gradation voltages
28 gradation voltages V65 to V128, the first when the value is "10"
29th to 192nd gradation voltages V129 to V192, and 193rd to 256th gradation voltages V19 when "11"
Each gradation voltage group of 3 to V256 is selected. For each of these gradation voltage groups, for example, 64th
Gradation voltage V64, 128th gradation voltage V128, 192nd
The gradation voltage V192 and the 256th gradation voltage V256 are designated, and these four gradation voltages V64, V128, V192, based on the upper 2 bits D8, D7 of the 8-bit digital data signals D1 to D8. 1 out of V256
ROM decoder 1 by selecting one as the output Vx2
Output from 1.

In the above driving method, when the driving voltage Vo is output from the output terminal 30 to the data line, a positive voltage and a negative voltage are alternately applied to the voltage of the common electrode. For example, when applying a positive voltage of 256 gradations to the data line,
As shown in FIG. 2, an 8-bit digital data signal D1
Based on D8 to D8, the ROM decoder 11P outputs one of 256 positive gradation voltages VP1 to VP256 to RO.
It is selected as the output VPx1 from the M decoder 11P, and the positive drive voltage V is output to the output terminal 30 via the operational amplifier 20P.
In addition to being supplied as Po, the voltage for urging the rising slope in a steep direction in a steep direction in synchronization with the pulse period of the latch signal STB at the rising of the waveform of the driving voltage VPo is output with low impedance from the PROM decoder 11P.
The operational amplifier 2 as Px2 without the operational amplifier 20P.
Supply directly to the output side of 0P. Also, the data line has 256
When applying a gradation negative voltage, as shown in FIG.
RO based on the bit digital data signals D1 to D8
256 gradations of negative gradation voltage VN1 by M decoder 11N
~ VN256 is selected as the output VNx1 from the ROM decoder 11N, supplied as the drive voltage VNo to the output terminal 30 via the operational amplifier 20N, and the latch signal STB is output when the output waveform of the operational amplifier 20N falls. The voltage for energizing the falling slope in a steep direction in synchronization with the pulse period of
The output VNx2 from the ROM decoder 11N is directly supplied to the output side of the operational amplifier 20N without passing through the operational amplifier 20N.

Circuit configurations of the PROM decoder 11P and the NROM decoder 11N will be described with reference to FIGS. 4 and 5. The same parts as those in FIGS. 11 and 12 are designated by the same reference numerals and the description thereof will be omitted. The difference from the PROM decoder 10P and the NROM decoder 10N is that the voltage VPx2 biases the rising and falling slopes in a steep direction in synchronization with the pulse period of the latch signal STB at the rising and falling of the drive voltage waveform. , VNx2 with low impedance are added respectively. This circuit is used for high-order 2 bits D of 8-bit digital data signals D1 to D8.
8 and D7, the grayscale voltages VP64, VP128, and
VP192, VP256, and VN64, VN12
One of the output signals VPx2 and VNx2 is selected and output from the output signals VPx2 and VNx2.

As shown in FIG. 4, the PROM decoder 11P is driven based on the same circuit configuration as that of the conventional PROM decoder 10P, and based on the upper 2 bits D8 and D7 of the 8-bit digital data signals D1 to D8. When the voltage waveform rises and falls, the gradation voltage VP6
4, VP128 (not shown), VP192, VP256
The following circuit is added to select and output one of them as the output VPx2. This circuit is used for each gradation voltage VP64, VP128, VP192, V
It consists of four low impedance transistor series circuits 5P corresponding to P256.
One end side of P (on the left side in the drawing) has gradation voltages VP64 and VP.
128, VP192 and VP256 are respectively connected to one end side of each transistor series circuit 3P, and the other end side of each transistor series circuit 5P is commonly connected to output V
It is set to Px2. Each transistor series circuit 5P has 8
Based on the upper 2 bits D8 and D7 of the bit digital data signals D1 to D8, the gradation voltages VP64 and VP12
In order to select one of 8, VP192 and VP256 with low impedance, it is composed of a MOS transistor gate-connected to the gate column pair 4P of the first and second columns to which the high-order 2 bits D8 and D7 are supplied. It has a P-type third transistor 6P and a P-type fourth transistor 7P which is always on by shorting the source and drain, and further, selects the selected grayscale voltage at the rising and falling edges of the waveform of the drive voltage. At the time, in order to output as the output VPx2, the anti-phase STB bar of the latch signal STB is "0".
It has a P-type fifth transistor 8P which is on-controlled at the time of (low level). The transistor 6P is configured by multiplying the size of the transistor 1P by, for example, 10 times, and the gradation voltages VP64, VP128, VP192, VP
The gates are connected in the same arrangement as the transistor 1P of each transistor series circuit 3P to which 256 is supplied.
Grayscale voltages VP64, VP128, V
Gates are connected in the same arrangement as the transistor 2P of each transistor series circuit 3P to which P192 and VP256 are supplied. Of the transistor series circuits 5P, the transistor series circuit 5P in which the normally-on control transistor 7P is arranged in the gate row 4Pb of the second gate row pair 4P does not include the transistor 7P The transistor 6P in the gate line 4Pa of the second gate line pair 4P may be directly connected to the transistor 8P by wiring.

As shown in FIG. 5, the NROM decoder 11N is driven on the basis of the upper 2 bits D8 and D7 of the 8-bit digital data signals D1 to D8 in addition to the same circuit configuration as the conventional NROM decoder 10N. When the voltage waveform rises and falls, the gradation voltage VN6
4, VN128 (not shown), VN192, VN256
The following circuit is added to select and output one of them as the above output VNx2. This circuit is provided for each gradation voltage VN64, VN128, VN192, V
It consists of four low impedance transistor series circuits 5N corresponding to N256.
One end side of N (on the left side in the drawing) has gradation voltages VN64 and VN.
128, VN192 and VN256 are respectively connected to one end side of each transistor series circuit 3N, and the other end side of each transistor series circuit 5N is commonly connected to output V
Nx2. Each transistor series circuit 5N has 8
Based on the upper 2 bits D8 and D7 of the bit digital data signals D1 to D8, the grayscale voltages VN64 and VN12
In order to select one of 8, VN192 and VN256 with low impedance, it is composed of a MOS transistor gate-connected to the gate column pair 4P of the first and second columns to which the high-order 2 bits D8 and D7 are supplied. It has an N-type third transistor 6N and an N-type fourth transistor 7N which is always in an ON state by shorting the source and drain, and further selects the selected gradation voltage at the rising and falling edges of the waveform of the drive voltage. At times, it has an N-type fifth transistor 8N which is on-controlled when the latch signal STB is "1 (high level)" in order to output it as the output VNx2. The transistor 6N is configured by multiplying the size of the transistor 1P by, for example, 10 times, and has a grayscale voltage VN6.
4, VN128, VN192, and VN256 are gate-connected in the same arrangement as the transistor 1N of each transistor series circuit 3N to which the transistor 7N is supplied.
Gradation voltage VN64, VN128, VN192, VN25
6 are connected to the transistors 2N of each transistor series circuit 3N in the same arrangement and are gate-connected. In the transistor series circuit 5N, the transistor 7 that is always on is connected to the gate line 4Nb of the second gate line pair 4N.
Regarding the transistor series circuit 5N in which N is arranged,
The transistor 6N of the gate row 4Na of the second gate row pair 4N may be directly connected to the transistor 8N by wiring without disposing the transistor 7N.

The operations of the PROM decoder 11P and the NROM decoder 11N having the above configurations will be described. The gradation voltages VP1 to VP256 and VN1 to VN256 of 256 gradations are given to one end side of each transistor series circuit 3P, 3N, and the gradation voltages VP64, VP128, VP192, VP256 are provided to one end side of each transistor series circuit 5P, 5N. ，
VN64, VN128, VN192 and VN256 are provided. In this state, "H (high level)" or "L"
Predetermined data signals D8, D7, ..., D1 of the positive columns D8, D on the first to eighth columns of the gate columns 4Pa, 4Na.
, ..., D1, respectively, and gate lines 4Pb, 4
In the first to eighth columns of Nb, the reverse phase D8 bar, D7 bar,
When supplied by D1 bar, all the transistors 1P and 1N of the selected one transistor series circuit 3P and 3N among the transistor series circuits 3P and 3N are turned on (transistors 2P and 2N are always on). , The gradation voltage applied to the transistor series circuit 3P, 3N is taken out as the output VPx1, and the transistor 6P, 6N of one selected transistor series circuit 5P, 5N among the transistor series circuits 5P, 5N is selected. Are all on (transistor 7P,
7N is always on), and the gradation voltage applied to the transistor series circuits 5P and 5N is output VPx2.
Is taken out with low impedance.

In the following, in the liquid crystal display device according to the present invention, the horizontal driver IC, which is the driving device of the first embodiment for driving the liquid crystal panel, is connected to the data line 384 of the liquid crystal panel.
6 and 1 as having the ability to drive the main part
This will be described with reference to FIG. The same parts as those in FIGS. 2 and 3 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 6, the horizontal driver IC 100 has an N of 384 data lines.
The (N = 1,3, ..., 383) and (N + 1) th are 1
As a set, a voltage follower connection of 19 is arranged as an operational amplifier 20P corresponding to 192 data line pairs.
Two rising-only operational amplifiers 21 and two operational amplifiers 2
192 falling-edge-only operational amplifiers 22 connected as voltage followers and each operational amplifier 21.
192 PROM decoders 11P connected to the (operational amplifier 20P) in the connection relationship shown in FIG. 2 and 192 NROM decoders 11N connected to each operation amplifier 22 (operational amplifier 20N) in the connection relationship shown in FIG. An odd-numbered 192 output terminals 30o connected to the odd-numbered data lines, an even-numbered 192 output terminals 30e connected to the even-numbered data lines, and an 8-bit digital data signal, First changeover switch 40 for alternately supplying to each ROM decoder 11P, 11N corresponding to each odd-numbered and even-numbered data line, and each output terminal 30o, 3
0e for alternately supplying positive and negative voltages on the output side of the operational amplifiers 21 and 22 as the drive voltage Vo.
A changeover switch 41 and an output stage are provided, and an input of the first changeover switch 40 is connected to an output of a level shifter of a preceding stage circuit in which a shift register, a data register, a latch, and a level shifter (not shown) in the horizontal driver IC 100 are sequentially connected. There is. This driver IC 100 can be used in the dot inversion driving method.

Next, the operation when the horizontal driver IC 100 is connected to the data line of the liquid crystal panel will be described. When the latch signal STB is supplied to the latch of the preceding circuit in the horizontal driver IC 100 in a certain horizontal period, the positive and negative gradation voltages VP1 to VP of 256 gradations of the output stage are provided.
Each ROM to which 256, VN1 to VN256 are supplied
8-bit digital data signals D8o, D7o, ..., Corresponding to the odd-numbered and even-numbered data lines, respectively, via the first changeover switch 40 to the decoders 11P, 11N.
D1e, D8e, D7e, ..., D1e are supplied, and the latch signal STB is supplied. In each of the ROM decoders 11P and 11N, digital data signals D8o and D7
o, ..., D1o, D8e, D7e, ..., D1e, the positive and negative gradation voltages VP1 to 256 of 256 gradations.
One of each of VP256 and VN1 to VN256 is an output VPx1 from the ROM decoders 11P and 11N.
It is selected as VNx1 and supplied to the operational amplifiers 21 and 22. At this time, each ROM decoder 11P, 1
1N, digital data signals D8o, D7o, D8e,
Based on D7e, positive and negative gradation voltages VP6
4, VP128, VP192, VP256, VN64,
Only one of VN128, VN192, and VN256 is selected, and the low-impedance outputs VPx2 and VNx2 from the ROM decoders 11P and 11N are set only during a period in which the pulse of the latch signal STB is supplied.
It is directly supplied to the output side of the operational amplifiers 21 and 22. The output side voltage of the operational amplifier 21 is a positive drive voltage VPo which is biased to the odd-numbered data line via the second changeover switch 41 and each output terminal 30o in the direction in which the rising slope of the waveform is steep. The output voltage of the operational amplifier 22, which is supplied as the drive voltage VPo, is the negative drive voltage VN.
The second changeover switch 41 and each output terminal 3 as o
The negative drive voltage VNo is biased to the even-numbered data line via 0e in the direction in which the falling slope of the waveform is steep.

In the next one horizontal period, the horizontal driver I
When the latch signal STB is supplied to the latch of the preceding circuit in C100, the ROM decoders 11P and 11N to which the positive and negative gradation voltages VP1 to VP256 and VN1 to VN256 of 256 gradations of the output stage are supplied. , 8-bit digital data signals D8e, D7e, ..., D1e, D8o, D7o, ..., D respectively corresponding to the even-numbered and odd-numbered data lines via the first changeover switch 40.
In addition to being supplied with 1o, the latch signal STB is supplied. Digital data signals D8e, D7e, ..., D1e, D8o, D7 in the respective ROM decoders 11P, 11N.
o, ..., D1o, the gradation voltages VP1 to VP256 and VN1 to VN256 of 256 gradations of positive and negative polarities.
One of each is a ROM decoder 11P, 11N
Are selected as the outputs VPx1 and VNx1 and are supplied to the operational amplifiers 21 and 22. Also, at this time, each RO
Digital data signal D8 by M decoders 11P and 11N
e, D7e, D8o, D7o based on the positive and negative gradation voltages VP64, VP128, VP192, VP
256, VN64, VN128, VN192, VN25
Each one of 6 is selected, and the latch signal STB
Low-impedance output VPx from the ROM decoders 11P and 11N only while the pulse of
2, VNx2 is directly supplied to the output side of the operational amplifiers 21 and 22. The output voltage of the operational amplifier 21 is a positive drive voltage VPo that is biased in a direction in which the rising slope of the waveform is steep in the even-numbered data lines via the second changeover switch 41 and each output terminal 30e. The output voltage of the operational amplifier 22 is supplied as the drive voltage VPo, and the output voltage of the operational amplifier 22 is set as the negative drive voltage VNo.
The negative drive voltage VNo is biased to the odd-numbered data lines via 1 and each output terminal 30o in the direction in which the falling slope of the waveform is steep.

As described above, the drive voltage VPo,
As VNo, in addition to the output through the operational amplifiers 21 and 22, a voltage for energizing the rising and falling slopes in a steep direction at the rising and falling of the waveforms of the drive voltages VPo and VNo with a low impedance is RO.
By directly supplying from the M decoders 11P and 11N to the output side of the operational amplifiers 21 and 22 without passing through the operational amplifiers 21 and 22, even if the load increases due to the size increase of the liquid crystal panel, the bias of the operational amplifiers 21 and 22 is increased. The rising and falling slopes of the waveforms of the drive voltages VPo and VNo can be made steep without increasing the current as in the conventional case, and the horizontal driver IC is driven with low current consumption, as shown in the example of the rising waveform in FIG. be able to.

Next, referring to FIG. 7, the horizontal driver IC, which is the semiconductor integrated circuit device of the second embodiment for driving the liquid crystal panel according to the present invention, has the driving capability of 384 data lines of the liquid crystal panel. And explain. The same parts as those in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 7, the horizontal driver IC 200 has a data line 38.
Operational amplifier 20P and operational amplifier 2 corresponding to four
2 is connected to each of the operational amplifiers 23 (as operational amplifiers 20P) of 384 one-amplifier type operational amplifiers 23 of voltage follower connection arranged as both 0N and rising and falling. 192 PROM decoders 11P connected to each operational amplifier 2
3 (as the operational amplifier 20N) in the connection relationship shown in FIG. 3 with 192 NROM decoders 11N, odd-numbered 192 output terminals 30o connected to odd-numbered data lines, and even-numbered data 192 even-numbered output terminals 30e connected to the lines and an 8-bit digital data signal are alternately supplied to the ROM decoders 11P and 11N corresponding to the odd-numbered and even-numbered data lines. The first changeover switch 40 and the third switch 42 for alternately supplying the outputs VPx1 and VNx1 of the ROM decoders 11P and 11N to the input sides of the odd-numbered operational amplifiers 23 and the even-numbered operational amplifiers 23, respectively. And the outputs VPx2, VNx of the respective ROM decoders 11P, 11N
4 for alternately supplying 2 to the output side of each odd-numbered operational amplifier 23 and each even-numbered operational amplifier 23
A switch 43 and an output stage are provided, and an input of the first changeover switch 40 is connected to an output of a level shifter of a preceding stage circuit in which a shift register, a data register, a latch, and a level shifter (not shown) in the horizontal driver IC 100 are sequentially connected. . This driver IC 200 can be used in both the dot inversion driving method and the line inversion driving method. The operation when the horizontal driver IC 200 is connected to the liquid crystal panel conforms to that of the horizontal driver IC 100, and therefore its description is omitted.

As described above, the drive voltage VPo,
In addition to the output through the operational amplifier 23 as VNo,
The output of the operational amplifier 23 is output from the ROM decoders 11P and 11N at a low impedance without using the operational amplifier 23 to generate a voltage that biases the rising and falling slopes in a steep direction when the output waveform of the operational amplifier 23 rises and falls. By directly supplying the output waveform to the operational amplifier 23, the rising and falling slopes of the output waveform of the operational amplifier 23 can be made steep without increasing the bias current of the operational amplifier 23 as compared with the conventional case even if the load increases due to the size increase of the liquid crystal panel. The horizontal driver IC can be driven with low current consumption.

[0022]

According to the driving method and the driving device of the liquid crystal display device of the present invention, in addition to the output through the operational amplifier, the driving voltage rises and rises when the waveform of the driving voltage rises and falls. The voltage that biases the downward slope in a steep direction is R with low impedance.
By directly supplying from the OM decoder to the output of the operational amplifier without passing through the operational amplifier, it is possible to cope with an increase in size of the liquid crystal panel by driving with low current consumption.

[Brief description of drawings]

FIG. 1 is a connection diagram of a ROM decoder and an operational amplifier for explaining a driving method of a liquid crystal display device of the present invention.

FIG. 2 is a connection diagram of a PROM decoder and an operational amplifier for explaining a driving method using a positive driving voltage in FIG.

FIG. 3 is a connection diagram of an NROM decoder and an operational amplifier for explaining a driving method with a negative driving voltage in FIG.

FIG. 4 is a circuit diagram of a main part of the PROM decoder shown in FIG.

5 is a circuit diagram of a main part of the NROM decoder shown in FIG.

FIG. 6 is a horizontal driver IC according to the first embodiment of the present invention.
FIG.

FIG. 7 is a horizontal driver IC according to a second embodiment of the present invention.
FIG.

FIG. 8 is a connection diagram of a ROM decoder and an operational amplifier for explaining a driving method of a conventional liquid crystal display device.

9 is a connection diagram of a PROM decoder and an operational amplifier for explaining a driving method using a positive driving voltage in FIG.

FIG. 10 is a connection diagram of an NROM decoder and an operational amplifier for explaining a driving method with a negative driving voltage in FIG.

FIG. 11 is a circuit diagram of a main part of the PROM decoder shown in FIG. 9.

12 is a circuit diagram of a main part of the NROM decoder shown in FIG.

FIG. 13 is a rising waveform diagram of a driving voltage.

[Explanation of symbols]

1P P-type first transistor 1N N-type first transistor 2P P-type second transistor (always ON control) 2N N-type second transistor (always-on control) 3P, 3N transistor series circuit 4P, 4N Gate row pair 4Pa, 4Pb, 4Na, 4Nb Gate row 5P, 5N transistor series circuit 6P P-type third transistor 6N N-type third transistor 7P P type 4th transistor (always ON control) 7N N-type fourth transistor (always ON control) 8P P-type fifth transistor 8N N-type fifth transistor 11 ROM decoder 11P PROM decoder 11N NROM decoder 20, 21, 22, 23: Operational amplifier 30 output terminals 30o Odd number output terminal 30e Even number output terminal 40 First changeover switch 41 Second changeover switch 42 3rd changeover switch 43 4th changeover switch

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 575 G09G 3/20 611 G09G 3/20 623 G09G 3/20 641

Claims (8)

(57) [Claims] 1. A driving voltage for a data line of a liquid crystal panel to be driven, based on an n-bit digital data signal,
One of the grayscale voltages of 2 to the nth grayscale is RO
In a method of driving a liquid crystal display device, which is selected by an M decoder and whose driving capability is increased by a voltage follower-connected operational amplifier for output, a method of driving a liquid crystal display device according to the digital data signal at the time of rising and falling of the waveform of the driving voltage, Of the gradation voltages of the nth power gradation of, one of the gradation voltages that biases the rising and falling slopes in a steep direction is RO
A method of driving a liquid crystal display device, comprising selecting with low impedance by an M decoder and directly supplying to the output side of the operational amplifier. 2. The method of driving a liquid crystal display device according to claim 1, wherein the gradation voltage selected with the low impedance is selected based on upper m bits of data of the digital data signal. 3. A ROM decoder for selecting one gray scale voltage of gray scale voltages of 2 n gray scales based on an n-bit digital data signal, and a driving capability for the selected gray scale voltage. In a driving device of a liquid crystal display device comprising a voltage follower connection operational amplifier for outputting to a data line of a liquid crystal panel to be raised and driven, the ROM decoder, when the rising and falling edges of the driving voltage, Based on the signal, one gray scale voltage of the n-th power gray scale that urges the rising and falling slopes in a steep direction is selected with low impedance, and the output of the operational amplifier is selected. A driving device for a liquid crystal display device, which is directly supplied to the side. 4. The driving device of a liquid crystal display device according to claim 3, wherein the grayscale voltage selected with the low impedance is selected based on upper m bits of data of the digital data signal. 5. The ROM decoder has 2n columns and 2n rows of 2n columns each of which is composed of two pairs of a first transistor capable of on / off control and a second transistor which is always on.
Both transistors are arranged in a predetermined manner in a matrix of columns, and each row has a transistor series circuit in which both the transistors are connected by a source and a drain, and one gate of one transistor of each pair is commonly connected for each column. And a gate row pair consisting of the other gate row in which the gates of the other transistors are commonly connected in each row,
One end of each transistor series circuit is connected to each gradation voltage of the n-th gradation of 2, and the other end of each transistor series circuit is commonly connected to be connected to the input of the operational amplifier. 5. A liquid crystal display device driving apparatus according to claim 4, wherein the gate row of is connected to a positive phase of the digital data signal and the other row of gates is composed of a ROM decoder connected to a reverse phase of the digital data signal. apparatus. 6. The ROM decoder supplies to a gate column pair to which high-order m-bit data is supplied among the n pairs of gate column pairs, 2 (n−m) of the n-th row transistor series circuit. ) A pair of a third transistor capable of on / off control and a normally-on fourth transistor is provided for each ride, the third transistor is the first transistor, and the fourth transistor is a fourth transistor.
The transistors are arranged in the same gate row as the second transistors, and each transistor has a second transistor series circuit in which a source and a drain are connected to each other, and one end of each second transistor series circuit has the second (n -M) One of the grayscale voltages corresponding to each of the power lines is connected, and the other ends of the second transistor series circuits are commonly connected and connected to the output of the operational amplifier. The drive device of the liquid crystal display device according to claim 5. 7. The operational amplifier comprises a rising operational amplifier and a falling operational amplifier, and the ROM decoder connected to the rising operational amplifier is PRO.
4. The driving device for a liquid crystal display device according to claim 3, wherein the driving device is an M decoder, and the ROM decoder connected to the falling operational amplifier is an NROM decoder. 8. The operational amplifier, wherein the operational amplifier outputs both a rising waveform and a falling waveform, and the RO
4. The drive device for a liquid crystal display device according to claim 3, wherein a PROM decoder and an NROM decoder are alternately connected to the operational amplifier as the M decoder.