CN113205776B

CN113205776B - Data line driving unit, display system and gray scale related remote auxiliary driving method

Info

Publication number: CN113205776B
Application number: CN202110467001.7A
Authority: CN
Inventors: 林兴武; 张盛东; 焦海龙; 张敏
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2021-04-28
Filing date: 2021-04-28
Publication date: 2022-08-30
Anticipated expiration: 2041-04-28
Also published as: CN113205776A

Abstract

The invention provides a data line driving unit, a display system and a gray-scale related remote auxiliary driving method. The data line driving unit, the display system and the gray scale related far-end auxiliary driving method adopt the technical scheme that the near end and the far end of the data line start to drive simultaneously, the near end is driven by a traditional voltage buffer, the far end is driven by a fully-conducted high-voltage PMOS transistor or NMOS transistor, and the duration period is controlled by p _ pulse or n _ pulse.

Description

Data line driving unit, display system and gray scale related remote auxiliary driving method

Technical Field

The invention relates to the field of display technology application, in particular to a data line driving unit, a display system and a gray scale related remote auxiliary driving method.

Background

The display signal driver is one of the most important components in an AMOLED (Active Matrix Organic Light Emitting diode) display system. The display signal driver is used to accurately drive (charge or discharge) the data lines to a target display voltage according to input display data. The display voltage is programmed into the selected pixel cell to drive the OLED to emit light. The data lines all have resistive and capacitive parasitic loads, and the display signal driver takes a certain time to drive the data lines so that the data line voltages are close enough to the final target display voltage. With the development of display technology, the physical size of the AMOLED display panel is continuously increasing. Therefore, the parasitic load of the data line becomes larger and larger, and at the same time, the display resolution is also continuously improved to UHD (ultra high definition 3980RGB × 2160). Furthermore, for video game applications, the frame rate has been increased from 60Hz to 240Hz or even 360Hz for a better experience. The increase in display resolution and the increase in frame frequency greatly limit the allowable time for the display signal driver to drive the data lines to the target display voltage.

Disclosure of Invention

The invention provides a data line driving unit for driving a pixel unit, which comprises a voltage buffer (533), a data line (21), an NMOS transistor (603) and a PMOS transistor (703); the voltage buffer (533) is connected to the near end of the data line (21) and is used for receiving the display signal and outputting the display signal to the data line (21); the drain electrode of the NMOS transistor (603) and the drain electrode of the PMOS transistor (703) are connected to the far end of the data line (21); the source of the NMOS transistor 603 is connected to the VSS terminal; the source of the PMOS transistor (703) is connected to the VDDH terminal; the grid electrode of the NMOS transistor (603) is used for receiving a pulse signal corresponding to the value of the current first control signal; the grid electrode of the PMOS transistor (703) is used for receiving a pulse signal corresponding to the value of the current second control signal; the conduction time of the NMOS transistor (603)/the PMOS transistor (703) is related to the display signal difference between the current row display signal and the previous row display signal output by the voltage buffer (533), and different values of the first control signal/the second control signal respectively correspond to pulse signals with different duty ratios; the data line (21) is connected to the pixel unit.

The invention also provides a display system, which comprises a first driving unit (31), a display panel (20), a second driving unit (32) and a display controller (10), wherein the first driving unit (31) and the second driving unit (32) are arranged at two opposite sides of the display panel (20), and M rows of driving channels are formed among the first driving unit (31), the display panel (20) and the second driving unit (32); the first drive unit (31) comprises a voltage buffer module (53); the second driving unit (32) comprises a far-end auxiliary driving module (54), a pulse selection signal decoder (51) and a pulse signal generator (52); the far-end auxiliary driving module (54) comprises a first selection path and a second selection path, and the first selection path and the second selection path are both connected to the pulse selection signal decoder (51) and the pulse signal generator (52); the display panel (20) comprises M rows of data lines (21), and the data lines (21) are connected to the corresponding pixel units; the mth column driving channel is provided with a voltage buffer module (53) of a first driving unit (31), an mth column data line and a far-end auxiliary driving module (54) of a second driving unit (32) which are connected in sequence; the display controller (10) is connected with the voltage buffer module (53) and the pulse selection signal decoder (51) and is used for outputting display signals to be transmitted to the data line (21) through the voltage buffer module (53); the display controller (10) is further used for outputting a pulse selection signal to a pulse selection signal decoder (51), and the pulse selection signal decoder (51) is used for decoding the pulse selection signal into a first control signal and a second control signal and correspondingly transmitting the first control signal and the second control signal to a first selection path and a second selection path respectively; the pulse signal generator (52) is used for generating pulse signals with different duty ratios; different values of the first control signal/the second control signal respectively correspond to pulse signals with different duty ratios; the first selection path is used for receiving the pulse signal of the pulse signal generator (52) and outputting the pulse signal corresponding to the value of the current first control signal, and the second selection path is used for receiving the pulse signal of the pulse signal generator (52) and outputting the pulse signal corresponding to the value of the current second control signal; wherein M is an integer greater than 1, and M is an integer greater than or equal to 1 and less than M.

The invention also provides a gray-scale correlation remote auxiliary driving method, which is applied to the display system and comprises the following processes:

receiving an externally input display signal;

converting the digital display signal into an analog display signal to be transmitted to the data line (21);

subtracting the display signal of the previous line from the display signal of the current line to calculate a current pulse selection signal;

decoding the pulse selection signal into a first control signal and a second control signal; different values of the first control signal/the second control signal respectively correspond to pulse signals with different duty ratios;

and outputting a pulse signal corresponding to the value of the current first control signal and outputting a pulse signal corresponding to the value of the current second control signal.

The data line driving unit, the display system and the data line driving method combine the advantages of voltage pre-emphasis, gray scale correlation and two-end driving methods, and have better performance.

Drawings

Fig. 1 is a schematic circuit diagram of a data line driving unit according to a first embodiment;

fig. 2 is a schematic circuit diagram of a data line driving unit according to a second embodiment;

FIG. 3 is a schematic structural diagram of a display system according to a third embodiment;

FIG. 4 is a schematic circuit diagram of a driving channel in a display system according to a third embodiment;

FIG. 5 is a waveform diagram of a data line driving circuit according to a third embodiment;

FIG. 6 is a schematic diagram of a fourth embodiment of a display system;

FIG. 7 is a schematic diagram of a display system according to a fifth embodiment;

FIG. 8 is a flowchart illustrating a gray scale dependent remote auxiliary driving method according to a sixth embodiment;

FIG. 9 is a diagram of simulation results of three data line driving methods and a display system;

FIG. 10 is a schematic diagram showing the performance comparison of three data line driving methods and a display system;

fig. 11 is a diagram illustrating a comparison result between the data line driving method of the present invention and the data line driving method using the data line load difference compensation.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present invention have not been shown or described in the specification in order to avoid obscuring the present invention from the excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they can be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" as used herein includes both direct and indirect connections (couplings), unless otherwise specified.

M is an integer greater than 1, and M is an integer greater than or equal to 1 and less than M.

In the invention, one end of the data line connected with the voltage buffer module (or the voltage buffer) is the near end of the data line, and one end connected with the far-end auxiliary driving module (or the NMOS transistor/PMOS transistor) is the far end of the data line.

The first embodiment is as follows:

as shown in fig. 1, the circuit structure of the data line driving unit of the present embodiment includes a voltage buffer 533, a data line 21, an NMOS transistor 603, and a PMOS transistor 703.

The voltage buffer 533 is connected to the near end of the data line 21, and is used for receiving the display signal and outputting the display signal to the data line 21. Four resistors R used in this embodiment _L A/4 and three capacitors C _L The 3T wire model of data line 21(3T wire model of data line) represented by/3 is well suited for the driving method of the present invention for analyzing the gray scale-dependent remote auxiliary fast data line driving for driving the data line from both ends of the data line. V _D (t) is the target display voltage from the DAC output; v _O (t) is the voltage at the output of the voltage buffer; r _L And C _L Respectively, the parasitic resistance and capacitance of the data line.

The source of NMOS transistor 603 is connected to VSS, which is 0V or a negative voltage. The source of the PMOS transistor 703 is connected to the VDDH terminal, which is a high voltage. The drain of the NMOS transistor 603 and the drain of the PMOS transistor 703 are connected to the distal end of the data line 21.

The gate of the NMOS transistor 603 is configured to receive a pulse signal corresponding to a value of the current first control signal n _ sel [3:0 ]; the gate of the PMOS transistor 703 is used for receiving a pulse signal corresponding to the value of the current second control signal p _ sel [3:0 ].

In this embodiment, the on-time of the NMOS transistor 603 and the PMOS transistor 703 is positively correlated with the display signal difference (or the driving voltage difference) between the current row display signal outputted from the voltage buffer 533 and the previous row display signal, and further correlated with the gray scale difference, specifically, the larger the gray scale difference between the current row and the previous row (or the larger the display signal difference between the current row display signal and the previous row), the longer the on-time of the NMOS transistor 603 and the PMOS transistor 703 is; the smaller the difference between the gray scales of the current row and the previous row is (or the smaller the difference between the display signal of the current row and the display signal of the previous row is), the shorter the on-time of the NMOS transistor 603 and the PMOS transistor 703 is accordingly; by such a design, the data line voltage can be assisted to reach the vicinity of the target voltage more quickly, and the voltage buffer 533 at the near end of the data line accurately pushes the data line to reach the target voltage, thereby shortening the setup time of the data line. The different values of the first control signal/the second control signal respectively correspond to a Pulse0 Pulse signal, a Pulse1 Pulse signal, a Pulse2 Pulse signal and a Pulse3 Pulse signal.

In the present embodiment, the data line 21 is connected to the pixel unit; alternatively, the data line driving unit of the present embodiment further includes a pixel unit connected to the data line 21, i.e., the pixel unit is an integral part of the data line driving unit.

Example two:

fig. 2 shows a circuit structure of the data line driving unit of the present embodiment, which includes a voltage buffer module 53, a data line 21, and a far-end auxiliary driving module 54.

The voltage buffer module 53 includes a third level shifter 531, a digital-to-analog converter 532 and a voltage buffer 533 connected in sequence, the voltage buffer module 53The buffer 533 is connected to the near end of the data line 21, and the third level shifter 531 is configured to receive the digital display signal, so that the digital display signal is boosted by the third level shifter 531, converted into an analog display signal by the digital-to-analog converter 532, and then outputted to the data line 21 through the voltage buffer 533. Four resistors R used in the present embodiment _L A/4 and three capacitors C _L The data line 21 of the 3T wire pattern indicated by/3 is well suited for the driving method of the present invention that analyzes the gray-scale-dependent remote-assist fast data line driving in which the data lines are driven from both ends of the data line. V _D (t) is the target display voltage from the DAC output; v _O (t) is the voltage at the output of the voltage buffer; r is _L And C _L Respectively, the parasitic resistance and capacitance of the data line.

The distal auxiliary drive module 54 includes a first selection path and a second selection path.

The first selection path comprises a first four-way selector 601, a first level shifter 602 and an NMOS transistor 603, wherein the output end of the first four-way selector 601, the first level shifter 602 and the gate of the NMOS transistor 603 are connected in sequence; the source of NMOS transistor 603 is connected to VSS, which is 0V or a negative voltage.

One input of the first four-way selector 601 is for receiving a first control signal n _ sel [3:0 ]; four input ends of the first four-way selector 601 are used for receiving a Pulse0 Pulse signal, a Pulse1 Pulse signal, a Pulse2 Pulse signal and a Pulse3 Pulse signal, one input end of the first four-way selector 601, which is used for receiving a Pulse0 Pulse signal, may also be connected to a VSS end, a Pulse0 Pulse signal represents a Pulse signal with a duty ratio of 0, and the VSS end represents 0 or a negative voltage; the duty ratio of a Pulse0 Pulse signal corresponding to the VSS end is 0, and the duty ratio of a Pulse signal corresponding to the VDDH end is 100%; the output end of the first four-way selector 601 is configured to output a pulse signal corresponding to the value of the current first control signal.

The second selection path comprises a second four-way selector 701, an inverter 704, a second level shifter 702 and a PMOS transistor 703, and the output end of the second four-way selector 701, the inverter 704, the second level shifter 702 and the gate of the PMOS transistor 703 are sequentially connected; the source of the PMOS transistor 703 is connected to the VDDH terminal, which is a high voltage.

One input of the second four-way selector 701 is for receiving a second control signal p _ sel [3:0 ]; four input ends of the second four-way selector 701 are used for receiving Pulse0 Pulse signals, Pulse1 Pulse signals, Pulse2 Pulse signals and Pulse3 Pulse signals, and one input end of the second four-way selector 701 used for receiving Pulse0 Pulse signals can also be connected to the VSS end; an output end of the second fourth selector 701 is configured to output a pulse signal corresponding to a value of the current second control signal.

The drain of NMOS transistor 603 for the first selection path and the drain of PMOS transistor 703 for the second selection path are connected to the far end of data line 21.

In this embodiment, different values of the first control signal/the second control signal respectively correspond to a Pulse0 Pulse signal, a Pulse1 Pulse signal, a Pulse2 Pulse signal, and a Pulse3 Pulse signal.

Example three:

fig. 3 shows an AMOLED Display system adopting a gray-scale-dependent remote auxiliary fast data line driving method according to this embodiment, which includes a first driving unit 31, a Display panel 20(Large AMOLED Display panel), a second driving unit 32 and a Display controller 10(Display controller), wherein the first driving unit 31 and the second driving unit 32 are disposed at two opposite sides of the Display panel 20, M rows of driving channels are formed among the first driving unit 31, the Display panel 20 and the second driving unit 32, and fig. 4 is a schematic circuit structure diagram of two adjacent rows of driving channels in the Display system. The display panel 20 includes M rows of data lines 21 corresponding to the M rows of driving channels, and the data lines 21 are connected to the corresponding pixel units. Specifically, in the present embodiment, the first driving unit 31 is a top driving unit, and is disposed on the top of the display panel; the second driving unit 32 is a bottom driving unit and is disposed at the bottom of the display panel. Alternatively, the first driving unit 31 may be defined as a bottom driving unit, and the second driving unit 32 may be defined as a top driving unit.

In this embodiment, the data line driving unit in the first embodiment or the second embodiment is used as a basic circuit structure thereof, and the specific implementation scheme is as follows.

The top driving unit and the bottom driving unit each include a plurality of Source driver chips 41(Source driver ICs) arranged along the display panel 20; referring to fig. 4, one source driver chip 41 is provided with a Pulse selection signal decoder 51(PN _ SEL signal decoder) and a Pulse signal generator 52(Pulse generator), and at least one pair of a Near-end data line driver 53 and a Far-end auxiliary driver 54(Far-end auxiliary driver) are further provided, so that the voltage buffer 53 and the Far-end auxiliary driver 54 are arranged in the top driver unit/the bottom driver unit at intervals. For example, the top source driver chip 41 may be designed to be responsible for driving the data lines 21 of the even columns from the Near end (Near-end) and auxiliary driving the data lines 21 of the odd columns from the Far end (Far-end); the bottom source driver chip 41 is responsible for driving the data lines 21 of the even columns from the far end and driving the data lines 21 of the odd columns from the near end. For a certain row of data lines 21, the near end is driven by the voltage buffer 533 of the top source driver chip 41, the far end is driven by the far-end auxiliary driver module 54 of the bottom source driver chip 41, and the near end of the data line 21 of the adjacent row is driven by the voltage buffer 533 of the bottom source driver chip 41, and the far end is driven by the far-end auxiliary driver module 54 of the top source driver chip 41.

The display controller 10 includes a display signal terminal 11, and further includes an access memory 12 and a Subtractor 13 (subcoctor) connected to each other. The output line of the display signal terminal 11 is connected to the access memory 12 and the voltage buffer module 53, and the input line of the display signal terminal 11 is used for transmitting the externally input display signal to the access memory 12 and the voltage buffer module 53. The Access Memory 12 is used to store display signals (DISP _ OLD [7:0]), including the display signals of the previous column, and the Access Memory 12 can be a dual-port Static Random Access Memory 12 (SRAM). The subtractor 13 is also connected to the pulse selection signal decoder 51 for subtracting the display signal of the previous line from the display signal of the current line to calculate a current pulse selection signal, i.e., a selection signal (PN _ SEL [2:0]) for calculating the remote auxiliary driving pulse signals (p _ pulse and n _ pulse), and outputting to the pulse selection signal decoder 51. For the mth column driving channel, the subtractor 13 outputs a pulse selection signal to the pulse selection signal decoder 51 of the column, and the pulse selection signal decoder 51 decodes the pulse selection signal into the first control signal n _ sel [3:0] and the second control signal p _ sel [3:0] and correspondingly delivers to the first selection path and the second selection path, respectively.

In the present embodiment, the external 8-bit display signal is taken as an example for explanation, and the specific generation method of the pulse selection signal (PN _ SEL [2:0]) is as follows: the display signal terminal 11 receives an externally newly input 8-bit display signal (DISP [7:0]), the access memory 12 stores an 8-bit display signal (DISP _ OLD [7:0]) of a previous line, the subtracter 13 subtracts the 8-bit display signal of the previous line from the 8-bit display signal of the current line, and retains a result of the highest 3 bits as a selection signal (PN _ SEL [2:0]) of the period of the current pulse signals (p _ pulse and n _ pulse). Where PN _ SEL [2] is the sign bit, which is used to determine whether to turn on PMOS transistor 703 or NMOS transistor 603 and to pump charge into or out of data line 21; PN _ SEL [ 1: 0] is used to select one of the pulse signals (p _ pulse and n _ pulse) of different duty ratios as the length of the remote auxiliary driving period. Setting the pulse selection signal PN _ SEL to 3 bits is only an example, and the number of bits of the pulse selection signal PN _ SEL may be increased if the design allows more pulse signals p _ pulse and n _ pulse to be selected. The more the pulse signal is designed, the closer the voltage of the data line 21 is to the target display voltage at the end of the remote auxiliary driving, which helps to shorten the setup time of the data line 21.

In the M-column driving channels, the voltage buffer module 53 of the top driving unit, the M-column data line 21, and the far-end auxiliary driving module 54 of the bottom driving unit are connected in sequence. The (m + 1) th column of driving channels has a far-end auxiliary driving module 54 of the top driving unit, an (m + 1) th column of data lines 21, and a voltage buffering module 53 of the bottom driving unit connected in sequence. The m-th row of driving channels can be used as a single-number row, and the m + 1-th row of driving channels is a double-number row; the m-th row of driving channels can also be a even-numbered row, and then the m + 1-th row of driving channels is a single-numbered row.

In the mth column driving channel, the voltage buffer module 53 includes a third level Converter 531, a Digital-to-Analog Converter 532 (DAC), and a voltage buffer 533 connected in sequence. The display signal output by the display signal terminal 11 is transmitted to the third level shifter 531, that is, when the technician designs the display signal terminal 11, the third level shifter 531 is directly connected to the display signal terminal 11; or, a part of intermediate modules are further connected between the third level shifter 531 and the display signal terminal 11, and the display signal is transmitted from the display signal terminal 11 to the third level shifter 531 through the intermediate modules. The Voltage buffer 533 is connected to the data line 21, so that the digital display signal (DISP [7:0]) output from the display signal terminal 11 to the mth row driving channel is boosted by the third level shifter 531, converted into an analog display signal by the digital-to-analog converter 532, and then output to the data line 21 through the Voltage buffer 533(Voltage buffer).

In the mth column of driving channels, the remote auxiliary driving module 54 includes a first selection path and a second selection path, both of which are connected to the pulse selection signal decoder 51 and the pulse signal generator 52. In this embodiment, the first control signal is an NMOS transistor control signal, and the first selection path is an NMOS transistor selection path; the second control signal is a PMOS transistor control signal, and the second selection path is a PMOS transistor selection path.

The Pulse signal generator 52 is used for generating Pulse0 Pulse signals, Pulse1 Pulse signals and Pulse2 Pulse signals … PulseN Pulse signals with different duty ratios; the different values of the first control signal/the second control signal respectively correspond to a Pulse0 Pulse signal, a Pulse1 Pulse signal and a Pulse2 Pulse … PulseN Pulse signal. The first selection path receives the pulse signal generated by the pulse signal generator 52 and outputs a pulse signal corresponding to the value of the current first control signal to turn on the NMOS transistor, and the second selection path receives the pulse signal generated by the pulse signal generator 52 and outputs a pulse signal corresponding to the value of the current second control signal to turn on the PMOS transistor.

In the present embodiment, the Pulse signal generator 52 generates the Pulse0 Pulse signal, the Pulse1 Pulse signal, the Pulse2 Pulse signal, and the Pulse3 Pulse signal with different duty ratios as an example.

In fig. 4, the left channel is an odd-numbered column channel, the right channel is an even-numbered column channel, and the circuit structures of the two channels are the same. The middle portion of fig. 4 is the display panel 20, and the upper and lower portions are the source driving chips 41. The display panel 20 is shown with data lines 21 of a 3T wire pattern of only two rows of channels, using four resistors R _L /4 and three capacitors C _L The 3T wire model represented by/3 is well suited for analyzing the driving method of gray-scale-dependent remote-assisted fast data line driving that drives data lines from both ends of the data lines. V _D (t) is the target display voltage from the DAC output; v _O (t) is the voltage at the output of the voltage buffer; r _L And C _L Respectively, the parasitic resistance and capacitance of the data line. The far end of the right channel data line 21 is driven by the far end auxiliary driving module 54 of the upper source driving chip 41, and the near end is driven by the voltage buffer 533 of the lower source driving chip 41. A first selection path of the far-end auxiliary driving module 54 includes a first four-way selector 601(MUX), a first Level shifter 602(Level shifter), and an NMOS transistor 603, where an output end of the first four-way selector 601, and gates of the first Level shifter 602 and the NMOS transistor 603 are sequentially connected; the source of NMOS transistor 603 is connected to the VSS terminal. One input end of the first four-way selector 601 is connected to the pulse selection signal decoder 51, and is configured to receive the first control signal output by the pulse selection signal decoder 51; four input ends of the first four-way selector 601 are connected to the Pulse signal generator 52, and are configured to receive the Pulse0 Pulse signal, the Pulse1 Pulse signal, the Pulse2 Pulse signal, and the Pulse3 Pulse signal generated by the Pulse signal generator 52, and one input end of the first four-way selector 601, which is configured to receive the Pulse0 Pulse signal, may also be connected to the VSS end; the output terminal of the first four-way selector 601 is used for outputting the current first control signalAnd taking the value of the corresponding pulse signal.

The second selection path of the far-end auxiliary driving module 54 includes a second four-way selector 701(MUX), an inverter 704, a second Level shifter 702(Level shifter) and a PMOS transistor 703, and the output end of the second four-way selector 701, the inverter 704, the second Level shifter 702 and the gate of the PMOS transistor 703 are sequentially connected; the source of the PMOS transistor 703 is connected to the VDDH terminal. One input end of the second four-way selector 701 in the second selection path is connected to the pulse selection signal decoder 51, and is used for receiving the second control signal output by the pulse selection signal decoder 51; four input ends of the second four-way selector 701 are connected to the Pulse signal generator 52, and are used for receiving the Pulse0 Pulse signal, the Pulse1 Pulse signal, the Pulse2 Pulse signal and the Pulse3 Pulse signal of the Pulse signal generator 52, and one input end of the second four-way selector 701, which is used for receiving the Pulse0 Pulse signal, may also be connected to the VSS terminal; the output end of the second four-way selector 701 is configured to output a pulse signal corresponding to the value of the current second control signal.

In the remote auxiliary driving module 54, the drain of the NMOS transistor 603 of the first selection path and the drain of the PMOS transistor 703 of the second selection path are connected to the data line 21.

As shown in Table 1, in the present embodiment, the subtracter 13 in the first left column of the table subtracts the display signal of the previous row from the display signal of the current row to obtain the difference (Gray level difference) of 182 to 255, 128 to 181, 64 to 127, 0 to 63, -63 to 0, -127 to-64, -181 to-128, and-255 to-182, and the corresponding pulse selection signals (PN _ SEL [2: 0)]) 011, 010, 001, 000, 111, 110, 101, 100; further respectively corresponding first control signals (n _ sel [3:0]]) 0001, 0010, 0100, 1000, respectively, corresponding to the second control signal (p _ sel [3: 0)]) Is 1000, 0100, 0010, 0001. The values of 0001, 0010, 0100 and 1000 of the first control signal/the second control signal respectively correspond to a Pulse0 Pulse signal, a Pulse1 Pulse signal, a Pulse2 Pulse signal and a Pulse3 Pulse signal. It can be seen that if the new and old display signals differ

Meanwhile, the PMOS transistor 703 and the NMOS transistor 603 of the remote auxiliary driving module 54 are both turned off and turned on; other cases select Pulse0, Pulse1, Pulse2 or Pulse3 to turn on either PMOS transistor 703 or NMOS transistor 603 according to the difference in magnitude and polarity.

Table 1 shows a corresponding relationship table of signal difference, control signal and pulse signal

Gray level difference	PN_SEL[2:0]	p_sel[3:0]	n_sel[3:0]
				182～255	011	1000	0001
128～181	010	0100	0001
				64～127	001	0010	0001
0～63	000	0001	0001
				-63～0	111	0001	0001
-127～-64	110	0001	0010
				-181～-128	101	0001	0100
-255～-182	100	0001	1000

For example, if n _ sel [3:0] is equal to 0001, the first four-way selector 601 will select Pulse0 Pulse signal with 0 duty cycle, i.e., ground (VSS); if n _ sel [3:0] equals 0010, Pulse1 is selected; if n _ sel [3:0] equals 0100, Pulse2 is selected; if n _ sel [3:0] equals 1000, Pulse3 is selected. Similarly, if p _ sel [3:0] is equal to 0001, the second four-way selector 701 will select Pulse0 Pulse signal with 0 duty cycle, i.e., ground (VSS); if p _ sel [3:0] equals 0010, Pulse1 is selected; if p _ sel [3:0] equals 0100, Pulse2 is selected; if p _ sel [3:0] equals 1000, Pulse3 is selected.

The voltage buffer 533, the data line 21, the NMOS transistor 603 and the PMOS transistor 703 form the basic structure of the fast data line driving circuit, as shown in FIG. 5The waveform diagram of the circuit is from the input terminal of the voltage buffer 533 (the voltage waveform V at the output terminal of the DAC) _D (t)), the data line 21 has V arranged from the proximal end to the distal end ₁ (t)、V ₂ (t) and V ₃ (t) three nodes, a remote node (V) ₃ (t)) the voltage ramp is fastest, which greatly shortens the time for the data line 21 to settle. In the figure, near 0 μ s, the curve is from top to bottom, and the waveform signals are respectively V ₃ (t)、V ₁ (t)、V ₂ (t); near 5 mus, the curve is from top to bottom, the signals are respectively V ₂ (t)、V ₁ (t)、V ₃ (t)。

Example four:

fig. 6 shows an AMOLED display system using a gray-scale-dependent remote-assisted fast data line driving method according to this embodiment, which includes a first driving unit 31, a display panel 20, a second driving unit 32, and a display controller 10, wherein the first driving unit 31 and the second driving unit 32 are disposed on two opposite sides of the display panel 20, and M rows of driving channels are formed among the first driving unit 31, the display panel 20, and the second driving unit 32. The display panel 20 includes M rows of data lines 21 corresponding to the M rows of driving channels, and the data lines 21 are connected to their corresponding pixel units. Specifically, in the present embodiment, the first driving unit 31 is a top driving unit, and is disposed on the top of the display panel; the second driving unit 32 is a bottom driving unit and is disposed at the bottom of the display panel. Alternatively, the first driving unit 31 may be defined as a bottom driving unit, and the second driving unit 32 may be defined as a top driving unit.

The top driving unit and the bottom driving unit each include a plurality of source driving chips 41 arranged along the display panel 20; the source driver chip 41 is provided with a pulse selection signal decoder and a pulse signal generator, and is further provided with at least one pair of a voltage buffer module 53 and a far-end auxiliary driver module 54, such that the voltage buffer module 53 and the far-end auxiliary driver module 54 are arranged at intervals in the top driver unit/the bottom driver unit. The difference between the present embodiment and the third embodiment is that in the present embodiment, the top source driver chip 41 only utilizes the voltage buffer module 53, and the bottom source driver chip 41 only utilizes the pulse selection signal decoder, the pulse signal generator and the far-end auxiliary driver module 54. That is, the top source driver chip 41 is responsible for driving the data lines 21 from the near end, and the bottom source driver chip 41 is responsible for driving the data lines 21 from the far end in an auxiliary manner.

Alternatively, it should be understood by those skilled in the art that in the present embodiment, it may be simply replaced that the bottom source driver chip 41 only utilizes the voltage buffer module 53, and the top source driver chip 41 only utilizes the pulse selection signal decoder, the pulse signal generator and the far-end auxiliary driver module 54. That is, the bottom source driver chip 41 is responsible for driving the data lines 21 from the near end, and the top source driver chip 41 is responsible for driving the data lines 21 from the far end.

The display controller 10 includes a display signal terminal 11, and further includes an access memory 12 and a subtractor 13 connected to each other. The output line of the display signal terminal 11 is connected to the access memory 12 and further connected to the voltage buffer module 53, and the input line of the display signal terminal 11 is used for transmitting the externally input display signal to the access memory 12 and the voltage buffer module 53. The access memory 12 is used for storing display signals, including the display signals of the previous row, and the access memory 12 can adopt a dual port SRAM 12. The subtractor 13 is further connected to the pulse selection signal decoder for subtracting the display signal of the previous line from the display signal of the current line to calculate the current pulse selection signal, i.e. the selection signal of the remote auxiliary driving pulse signal, and outputting the current pulse selection signal to the pulse selection signal decoder. For the m-th column driving channel, the subtracter 13 outputs a pulse selection signal to the pulse selection signal decoder of the column, and the pulse selection signal decoder decodes the pulse selection signal into a first control signal and a second control signal and correspondingly transmits the first control signal and the second control signal to the first selection path and the second selection path respectively.

Other technical features of this embodiment are the same as those of the third embodiment, and thus are not described again.

Example five:

fig. 7 shows an AMOLED display system using a gray-scale-dependent remote-assisted fast data line driving method according to this embodiment, which includes a first driving unit 31, a display panel 20, a second driving unit 32, and a display controller 10, wherein the first driving unit 31 and the second driving unit 32 are disposed on two opposite sides of the display panel 20, and M rows of driving channels are formed among the first driving unit 31, the display panel 20, and the second driving unit 32. The display panel 20 includes M rows of data lines 21 corresponding to the M rows of driving channels, and the data lines 21 are connected to their corresponding pixel units. Specifically, in the present embodiment, the first driving unit 31 is a top driving unit, and is disposed on the top of the display panel; the second driving unit 32 is a bottom driving unit and is disposed at the bottom of the display panel. Alternatively, the first driving unit 31 may be defined as a bottom driving unit, and the second driving unit 32 may be defined as a top driving unit.

The first driving unit 31 includes a plurality of voltage buffer modules 53 arranged along the display panel 20 but does not include the remote auxiliary driving module 54, and specifically, the top driving unit includes a plurality of source driving chips 41 arranged along the display panel 20, and at least one voltage buffer module 53 but not the remote auxiliary driving module 54 is disposed on the source driving chip 41 of the top driving unit. The second driving unit 32 includes a pulse selection signal decoder, a pulse signal generator, and further includes a plurality of remote auxiliary driving modules 54 arranged along the display panel 20 but does not include the voltage buffer module 53, specifically, the bottom driving unit includes a plurality of source driving chips 41 arranged along the display panel 20, and the source driving chips 41 of the bottom driving unit are provided with the pulse selection signal decoder, the pulse signal generator, and at least one remote auxiliary driving module 54 but are not provided with the voltage buffer module 53.

The difference between this embodiment and the third embodiment is that in this embodiment, the top source driver chip 41 only utilizes the voltage buffer module 53, and the bottom source driver chip 41 only utilizes the pulse selection signal decoder, the pulse signal generator and the far-end auxiliary driver module 54. That is, the top source driver chip 41 is responsible for driving the data lines 21 from the near end, and the bottom source driver chip 41 is responsible for driving the data lines 21 from the far end in an auxiliary manner.

Alternatively, it should be understood by those skilled in the art that, in this embodiment, the bottom source driver chip 41 may also be replaced with a simple one, which includes a pulse selection signal decoder, a pulse signal generator, and a plurality of remote auxiliary driver modules 54 arranged along the display panel 20 but does not include the voltage buffer module 53, and the top source driver chip 41 includes a plurality of voltage buffer modules 53 arranged along the display panel 20 but does not include the remote auxiliary driver module 54. That is, the bottom source driver chip 41 is responsible for driving the data lines 21 from the near end, and the top source driver chip 41 is responsible for driving the data lines 21 from the far end in an auxiliary manner.

The display controller 10 includes a display signal terminal 11, and further includes an access memory 12 and a subtractor 13 connected to each other. The output line of the display signal terminal 11 is connected to the access memory 12 and the voltage buffer module 53, and the input line of the display signal terminal 11 is used for transmitting the externally input display signal to the access memory 12 and the voltage buffer module 53. The access memory 12 is used for storing display signals, including the display signals of the previous row, and the access memory 12 can adopt a dual port SRAM 12. The subtractor 13 is further connected to the pulse selection signal decoder, and is configured to calculate a current pulse selection signal by subtracting the display signal of the previous line from the display signal of the current line, that is, calculate a selection signal of the remote auxiliary driving pulse signal, and output the selection signal to the pulse selection signal decoder. For the m-th column driving channel, the subtracter 13 outputs a pulse selection signal to the pulse selection signal decoder of the column, and the pulse selection signal decoder decodes the pulse selection signal into a first control signal and a second control signal and correspondingly transmits the first control signal and the second control signal to the first selection path and the second selection path respectively.

Example six:

the gray-scale-dependent remote-assisted fast data line driving method (or large-size screen fast data line driving method) of the present embodiment is applied to the display systems of the third embodiment, the fourth embodiment and the fifth embodiment and is applied to driving the data lines of other large AMOLED display panels, as shown in fig. 8, and includes the following processes:

st1, the display signal terminal 11 receives an externally input digital display signal.

St2, the digital display signal outputted from the display signal terminal 11 to the driving channel is boosted by the third level shifter 531, converted into an analog display signal by the digital-to-analog converter 532, and outputted to the data line 21 through the voltage buffer 533.

St3, the current pulse selection signal is calculated by subtracting the display signal of the previous line from the display signal of the current line.

Taking the example of receiving the externally newly inputted 8-bit display signal, the access memory 12 stores the previous row of 8-bit display signals, and the subtractor 13 subtracts the previous row of 8-bit display signals from the current row of 8-bit display signals, and retains the result of the highest 3 bits as the selection signal (PN _ SEL [2:0]) of the current period of pulse signals (p _ pulse and n _ pulse). Where PN _ SEL [2] is the sign bit, which is used to determine whether to turn on PMOS transistor 703 or NMOS transistor 603 and to pump charge into or out of data line 21; PN _ SEL [ 1: 0] is used to select one of the 4 pulse signals (p _ pulse and n _ pulse) with different duty ratios as the length of the remote auxiliary driving period.

St4, the pulse selection signal decoder 51 decodes the pulse selection signal into a first control signal and a second control signal and transmits them to the first selection path and the second selection path, respectively. The different values of the first control signal/the second control signal respectively correspond to a Pulse0 Pulse signal, a Pulse1 Pulse signal and a Pulse2 Pulse … PulseN Pulse signal.

St5, outputting a pulse signal corresponding to the value of the current first control signal and outputting a pulse signal corresponding to the value of the current second control signal.

In the present embodiment, the Pulse signal generator 52 generates the Pulse0 Pulse signal, the Pulse1 Pulse signal, the Pulse2 Pulse signal, and the Pulse3 Pulse signal with different duty ratios.

In the first selection path of the far-end auxiliary driving module 54, one input end of the first four-way selector 601 receives the first control signal output by the pulse selection signal decoder 51; four input ends of the first four-way selector 601 receive the Pulse0 Pulse signal, the Pulse1 Pulse signal, the Pulse2 Pulse signal and the Pulse3 Pulse signal of the Pulse signal generator 52, and one input end of the first four-way selector 601, which is used for receiving the Pulse0 Pulse signal, may also be connected to the VSS end; the output end of the first four-way selector 601 outputs a pulse signal corresponding to the value of the current first control signal.

In the second selection path of the far-end auxiliary driving module 54, one input end of the second four-way selector 701 receives the second control signal output by the pulse selection signal decoder 51; four input ends of the second four-way selector 701 receive Pulse0 Pulse signals, Pulse1 Pulse signals, Pulse2 Pulse signals and Pulse3 Pulse signals of the Pulse signal generator 52, and one input end of the second four-way selector 701 for receiving the Pulse0 Pulse signals can also be connected to the VSS terminal; the output end of the second four-way selector 701 outputs a pulse signal corresponding to the value of the current second control signal.

As shown in Table 1, in the present embodiment, the subtracter 13 in the first column on the left in the table subtracts the display signals of the previous row from the display signals of the current row by the differences of 182 to 255, 128 to 181, 64 to 127, 0 to 63, -63 to 0, -127 to-64, -181 to-128, and-255 to-182, and the corresponding pulse selection signals are 011, 010, 001, 000, 111, 110, 101, and 100, respectively; further, the first control signals respectively correspond to 0001, 0010, 0100, and 1000, and the second control signals respectively correspond to 1000, 0100, 0010, 0001, and 0001. 0001, 0010, 0100 and 1000 values of the first control signal/the second control signal respectively correspond to a Pulse0 Pulse signal, a Pulse1 Pulse signal, a Pulse2 Pulse signal and a Pulse3 Pulse signal. It can be seen that if the difference between the old and new display signals is

Meanwhile, the PMOS transistor 703 and the NMOS transistor 603 of the remote auxiliary driving module 54 are both turned off and turned on; otherwise, the Pulse0, Pulse1, Pulse2 or Pulse3 are selected to turn on the PMOS transistor 703 or the NMOS transistor 603 according to the difference in magnitude and polarity.

For example, if n _ sel [3:0] is equal to 0001, the first four-way selector 601 will select 0 duty cycle Pulse0 Pulse signal, i.e., ground (VSS); if n _ sel [3:0] equals 0010, Pulse1 is selected; if n _ sel [3:0] equals 0100, Pulse2 is selected; if n _ sel [3:0] equals 1000, Pulse3 is selected. Similarly, if p _ sel [3:0] is equal to 0001, the second four-way selector 701 will select Pulse0 Pulse signal with 0 duty cycle, i.e., ground (VSS); if p _ sel [3:0] equals 0010, Pulse1 is selected; if p _ sel [3:0] equals 0100, Pulse2 is selected; if p _ sel [3:0] equals 1000, Pulse3 is selected.

FIG. 9 is a diagram showing simulation results of three data line driving methods and a display system. Fig. 9(a) shows a data line driving method and a display system without pre-emphasis (pre-emphasis), i.e., directly using a voltage buffer; fig. 9(b) illustrates a data line driving method and a display system using pre-emphasis (pre-emphasis) voltage and data line load difference compensation; fig. 9(c) corresponds to the gray-level related remote assisted fast data line driving method and the display system of the present invention. Adopting the parasitic load of the data line 21 as R in simulation _L ＝4kΩ，C _L 150pF, the voltage of the data line 21 is from V _L 4V up to V _H When three nodes reach V, 14V _H Within ± 0.7%, the setup time of the data line 21 is measured. The operational amplifier of the voltage buffer 533(Volage buffer) for the near-end driving is an ideal operational amplifier, the high-voltage device adopts a 0.18 μm technology, and the high-voltage PMOS transistor and the NMOS transistor have a predetermined width-to-length ratio.

In FIG. 9(a), the data line 21 setup delay is 1.54 μ s. In fig. 9(b), the pre-emphasis parameter K used for the simulation is 0.25 and the data line 21 set-up delay is 1.27 μ s. In FIG. 9(c), the auxiliary drive pulse square wave period is 0.47 μ s and the data line 21 set-up delay is 0.52 μ s, 59% faster than the method of FIG. 9 (b).

"pre-emphasis" (or voltage pre-emphasis) refers to temporarily boosting the drive voltage above the target voltage for a short period of time at an early stage of driving the data lines.

FIG. 10 is a schematic diagram showing the performance comparison of three data line driving methods and the display system. Fig. 10 is a simulation result when a ± 20% difference occurs in the load of the data line 21. In simulation R _L 1k Ω constant,/4, C _L The/3 changes from 40pF to 60pF, stepping to 5 pF. The curve connecting the top dots in fig. 7 is the simulation result of the data line driving method and the display system without pre-emphasis, and the delay of the data line 21 is proportional to the load variation. The curve connected by the middle diamonds in fig. 10 is the simulation result of the data line driving method and the display system with pre-emphasis and data line load difference compensation, each load re-correcting the value of the pre-emphasis parameter K. The simulation results show that at ± 20% of the load difference of the data line 21, the curve is "flat" compared to the other two driving methods. The curve formed by connecting the bottom triangles in fig. 10 is the simulation result of the fast data line driving method and the display system of the present invention. Although not compensated for by data line load variation, the data line 21 setup time of the present invention is shorter than the first two methods within a range of ± 20% variation. The optimum data line 21 setup time occurs at C _L At 50 pF/3, either too low or too high of the load increases the data line 21 settling time.

FIG. 11 is a schematic diagram showing the comparison results between the gray scale-related remote assisted fast data line driving method and display system of the present invention and the data line driving method and display system using pre-emphasis and data line load difference compensation, it can be seen by comparison that in the case of + -20% difference in load, the data line 21 setup time is reduced by the method and system of the present invention

The above simulation results show that the driving method of the present invention has better performance than other methods of the prior art even without compensating for the data line parasitic load difference. If the hardware cost is not considered, the data line parasitic load compensation scheme can be designed into the quick driving method of the invention by adjusting the duration time of the far-end auxiliary driving, so that the performance of the gray-scale-related far-end auxiliary quick data line driving method is further improved.

The data line driving unit, the display system and the gray scale related remote auxiliary driving method combine the advantages of voltage pre-emphasis, gray scale related and two-end driving methods, and have better performance. The technical solution of starting driving at the near end and the far end of the data line 21 at the same time is adopted, the near end is driven by a conventional voltage buffer, and the far end is driven by a fully-conductive high-voltage PMOS transistor or NMOS transistor, and the duration period is controlled by p _ pulse or n _ pulse. In circuit theory, the shortest "distance" between two nodes is the "distance" of a fully turned on transistor, the duration of p _ pulse and n _ pulse depends on the gray scale difference, i.e. the difference between the current and the previous display data (gray scale), and the present invention accelerates the setup time of the data line by charging or discharging the data line with the fully turned on transistor for a short time at the far end of the data line according to the difference between the current and the previous display data.

The gray-scale related far-end auxiliary fast data line driving method provided by the invention is different from the traditional pre-emphasis driving method in that the traditional design divides the driving time interval into a pre-emphasis time interval and a normal driving time interval, the data line is firstly driven by the pre-emphasis voltage in the pre-emphasis time interval and then driven by the target voltage in the normal driving time interval; although the method of the present invention is divided into two periods, the two periods start at the same time, that is, the data lines start to be driven at the same time from both ends of the data lines, and after the far-end auxiliary driving period (p _ pulse or n _ pulse) ends, the near-end voltage buffer driving continues to drive the data lines with the target voltage. In the method, the data line is charged at the maximum speed in the period of the far-end auxiliary driving, so that the time for driving the data line by the near-end voltage buffer can be greatly shortened; in addition, although the far-end auxiliary driving only instantaneously pulls up the far-end voltage of the data line, the driving of the near-end voltage buffer is not affected because the far-end auxiliary driving is at the far end of the data line.

In the prior art, a data line driving method with voltage Pre-emphasis and data line parasitic load difference compensation (or load sensing) has a disadvantage in that an additional high-voltage device module needs to be designed for each channel, and a chip layout of a high-voltage device is usually large, for example, a switch (sw), a Pre-emphasis voltage generator (Pre-emphasis voltage generator), and a K-calibrator (K-calibrator); after the pre-emphasis parameter K value is calibrated, the additional high-voltage device module is not used, but still occupies the layout. The hardware cost of the display system and the fast data line driving method of the invention is lower than that of the prior art system or method. Other modules such as a pulse selection signal decoder and a pulse signal generator only need to be arranged on each source driving chip, and the layout area of related chips can be ignored. The remote auxiliary driving module needs high-voltage devices to implement, the needed additional high-voltage devices are only designed to be one PMOS transistor, one NMOS transistor and two level shifters, the high-voltage devices needed by all channels are about ten or more, the specific number depends on the actual requirement of the level shifter, and the design can be very flexibly performed by a person skilled in the art.

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. Numerous simple deductions, modifications or substitutions may also be made by those skilled in the art in light of the present teachings.

Claims

1. A data line driving unit for driving a pixel unit,

the data line driving unit includes a voltage buffer (533), a data line (21), an NMOS transistor (603), and a PMOS transistor (703);

the data line (21) is connected to the pixel unit, and the data line (21) comprises a near end and a far end which respectively extend to two sides of the display panel;

the voltage buffer (533) is connected to the near end of the data line (21) for receiving the display signal and outputting the display signal to the data line (21);

the drain of the NMOS transistor (603) and the drain of the PMOS transistor (703) are connected to the far end of a data line (21);

the source of the NMOS transistor 603 is connected to the VSS terminal; the source of the PMOS transistor (703) is connected to the VDDH terminal;

the grid electrode of the NMOS transistor (603) is used for receiving a pulse signal corresponding to the value of the current first control signal;

the grid electrode of the PMOS transistor (703) is used for receiving a pulse signal corresponding to the value of the current second control signal;

the first control signal and the second control signal are respectively generated according to the display signal difference between the current row display signal and the previous row display signal, different values of the first control signal and the second control signal respectively correspond to pulse signals with different duty ratios, the pulse signals with different duty ratios control the NMOS transistor (603) and the PMOS transistor (703) to have different conduction times, the far end of the data line (21) is connected to the VSS end in the conduction period of the NMOS transistor (603), and the far end of the data line (21) is connected to the VDDH end in the conduction period of the PMOS transistor (703), so that the voltage buffer (533) drives the data line from the near end of the data line (21) and drives the data line from the far end of the data line (21).

2. The data line drive unit according to claim 1,

the circuit also comprises a first four-way selector (601), a first level shifter (602), a second four-way selector (701), an inverter (704) and a second level shifter (702);

the output end of the first four-way selector (601), the first level shifter (602) and the grid electrode of the NMOS transistor (603) are connected in sequence;

an input terminal of the first four-way selector (601) is used for receiving a first control signal; three input ends of the first four-way selector (601) are used for receiving Pulse1 Pulse signals, Pulse2 Pulse signals and Pulse3 Pulse signals, and one input end of the first four-way selector is used for receiving Pulse0 Pulse signals or is connected to a VSS end; the output end of the first four-way selector (601) is used for outputting a pulse signal corresponding to the value of the current first control signal;

the output end of the second four-way selector (701), the inverter (704), the second level shifter (702) and the grid electrode of the PMOS transistor (703) are sequentially connected;

one input end of the second four-way selector (701) is used for receiving a second control signal; three input ends of the second four-way selector (701) are used for receiving Pulse1 Pulse signals, Pulse2 Pulse signals and Pulse3 Pulse signals, and one input end of the second four-way selector is used for receiving Pulse0 Pulse signals or connected to a VSS end; the output end of the second four-way selector (701) is used for outputting a pulse signal corresponding to the value of the current second control signal.

3. The data line drive unit according to claim 1 or 2,

a third level shifter (531) and a digital-to-analog converter (532) are also included;

the third level converter (531), the digital-to-analog converter (532) and the voltage buffer (533) are connected in sequence;

the third level shifter (531) is configured to receive a digital display signal, such that the digital display signal is boosted by the third level shifter (531), converted into an analog display signal by the digital-to-analog converter (532), and output to the data line (21) by the voltage buffer (533);

the data line driving unit further includes a pixel unit connected to the data line (21).

4. A display system, characterized in that,

the display panel comprises a first driving unit (31), a display panel (20), a second driving unit (32) and a display controller (10), wherein the first driving unit (31) and the second driving unit (32) are arranged on two opposite sides of the display panel (20), and M rows of driving channels are formed among the first driving unit (31), the display panel (20) and the second driving unit (32);

the first drive unit (31) comprises a voltage buffer module (53);

the second drive unit (32) comprises a remote auxiliary drive module (54), a pulse selection signal decoder (51) and a pulse signal generator (52); the far-end auxiliary driving module (54) comprises a first selection path and a second selection path, and the first selection path and the second selection path are both connected to the pulse selection signal decoder (51) and the pulse signal generator (52);

the display panel (20) comprises M rows of data lines (21), the data lines (21) are connected to corresponding pixel units, and the data lines (21) comprise near ends and far ends which respectively extend to two sides of the display panel; the voltage buffer module (53) is connected to the near end of the data line (21) and is used for driving the data line from the near end of the data line (21), and the first selection path and the second selection path are respectively connected to the far end of the data line (21) and are used for simultaneously driving the data line from the far end of the data line (21); the mth column driving channel is provided with a voltage buffer module (53) of a first driving unit (31), an mth column data line and a far-end auxiliary driving module (54) of a second driving unit (32) which are connected in sequence;

the display controller (10) is connected with the voltage buffer module (53) and is used for outputting display signals to the voltage buffer module (53) and transmitting the display signals to the near end of the data line (21) through the voltage buffer module (53);

the display controller (10) is further connected with a pulse selection signal decoder (51) and used for outputting a pulse selection signal to the pulse selection signal decoder (51), and the pulse selection signal decoder (51) is used for decoding the pulse selection signal into a first control signal and a second control signal and correspondingly transmitting the first control signal and the second control signal to a first selection path and a second selection path respectively; the pulse signal generator (52) is used for generating pulse signals with different duty ratios; different values of the first control signal and the second control signal respectively correspond to pulse signals with different duty ratios; the first selection path is used for receiving the pulse signal of the pulse signal generator (52) and determining the drive time of the far end of the data line (21) according to the duty ratio of the pulse signal corresponding to the value of the current first control signal, and the second selection path is used for receiving the pulse signal of the pulse signal generator (52) and determining the drive time of the far end of the data line (21) according to the duty ratio of the pulse signal corresponding to the value of the current second control signal;

wherein M is an integer greater than 1, and M is an integer greater than or equal to 1 and less than M.

5. The display system of claim 4,

the first drive unit (31) further comprises a remote auxiliary drive module (54), a pulse selection signal decoder (51) and a pulse signal generator (52);

the second drive unit (32) further comprises a voltage buffer module (53);

in the first driving unit (31) and the second driving unit (32), the voltage buffer module (53) and the far-end auxiliary driving module (54) are arranged at intervals;

the m +1 th column of driving channels are provided with a far-end auxiliary driving module (54) of a first driving unit (31), an m +1 th column of data lines and a voltage buffering module (53) of a second driving unit (32) which are connected in sequence.

6. The display system of claim 5,

the first driving unit (31) and the second driving unit (32) each include at least one source driving chip (41) arranged along the display panel (20);

the pulse selection signal decoder (51) and the pulse signal generator (52) are arranged on the source driving chip (41), and at least one pair of a voltage buffer module (53) and a far-end auxiliary driving module (54) is further arranged on the source driving chip (41), so that the voltage buffer module (53) and the far-end auxiliary driving module (54) are arranged in the first driving unit (31) and the second driving unit (32) at intervals.

7. The display system according to any one of claims 4 to 6,

the voltage buffer module (53) comprises a third level converter (531), a digital-to-analog converter (532) and a voltage buffer (533) which are connected in sequence;

the third level shifter (531) is connected to the display controller (10), and the voltage buffer (533) is connected to the near end of the data line (21), so that the digital display signal output by the display controller (10) is boosted by the third level shifter (531), converted into an analog display signal by the digital-to-analog converter (532), and output to the data line (21) through the voltage buffer (533).

8. The display system according to any one of claims 4 to 6,

the first selection path of the far-end auxiliary driving module (54) comprises a first four-way selector (601), a first level shifter (602) and an NMOS transistor (603), and the output end of the first four-way selector (601), the first level shifter (602) and the grid electrode of the NMOS transistor (603) are sequentially connected; the source of the NMOS transistor 603 is connected to the VSS terminal;

one input end of the first four-way selector (601) is connected to the pulse selection signal decoder (51) and is used for receiving the first control signal output by the pulse selection signal decoder (51); the four input ends of the first four-way selector (601) are connected to the Pulse signal generator (52) and used for receiving Pulse0 Pulse signals, Pulse1 Pulse signals, Pulse2 Pulse signals and Pulse3 Pulse signals of the Pulse signal generator (52); the output end of the first four-way selector (601) is used for outputting a pulse signal corresponding to the value of the current first control signal;

the second selection path of the far-end auxiliary driving module (54) comprises a second four-way selector (701), an inverter (704), a second level shifter (702) and a PMOS transistor (703), and the output end of the second four-way selector (701), the inverter (704), the second level shifter (702) and the grid electrode of the PMOS transistor (703) are sequentially connected; the source of the PMOS transistor (703) is connected to the VDDH terminal;

one input end of the second four-way selector (701) is connected to the pulse selection signal decoder (51) and is used for receiving a second control signal output by the pulse selection signal decoder (51); the four input ends of the second four-way selector (701) are connected to the Pulse signal generator (52) and used for receiving Pulse0 Pulse signals, Pulse1 Pulse signals, Pulse2 Pulse signals and Pulse3 Pulse signals of the Pulse signal generator (52); the output end of the second four-way selector (701) is used for outputting a pulse signal corresponding to the value of the current second control signal;

the drain of the NMOS transistor (603) of the first selection path and the drain of the PMOS transistor (703) of the second selection path are connected to the far end of the data line (21).

9. The display system according to any one of claims 4 to 6,

the display controller (10) comprises a display signal end (11), an access memory (12) and a subtracter (13) which are connected with each other;

the output circuit of the display signal terminal (11) is connected to the access memory (12) and is also connected to a voltage buffer module (53) for transmitting the display signal input from the outside to the access memory (12) and the voltage buffer module (53);

the access memory (12) is used for storing the display signals of the previous row;

the subtracter (13) is also connected to the pulse selection signal decoder (51) and is used for subtracting the display signal of the previous line from the display signal of the current line so as to calculate the current pulse selection signal, and the current pulse selection signal is output to the pulse selection signal decoder (51).

10. The display system of claim 9,

the display signal terminal (11) is used for receiving an externally input 8-bit display signal;

the access memory (12) is used for storing 8-bit display signals of a previous row;

the subtracter (13) is used for subtracting the 8-bit display signal of the previous line from the 8-bit display signal of the current line and keeping the result of the highest 3 bits as the current pulse selection signal;

the access memory (12) is a dual port static random access memory.

11. The display system of claim 10,

the subtracter (13) subtracts the display signal of the previous line from the display signal of the current line to obtain the difference of 182-255, 128-181, 64-127, 0-63, -63-0, -127 to-64, -181 to-128 and-255 to-182, and the corresponding pulse selection signals are 011, 010, 001, 000, 111, 110, 101 and 100 respectively.

12. The display system of claim 11,

the pulse selection signals 011, 010, 001, 000, 111, 110, 101 and 100 respectively correspond to the first control signals 0001, 0010, 0100 and 1000, and the second control signals 1000, 0100, 0010, 0001 and 0001;

the values of 0001, 0010, 0100 and 1000 of the first control signal and the second control signal respectively correspond to a Pulse0 Pulse signal, a Pulse1 Pulse signal, a Pulse2 Pulse signal and a Pulse3 Pulse signal.

13. A gray scale dependent remote auxiliary driving method applied to the display system according to any one of claims 4 to 12, comprising:

receiving an externally input display signal;

converting the digital display signal into an analog display signal to be transmitted to a near end of the data line (21), driving the data line from the near end of the data line;

decoding the pulse selection signal into a first control signal and a second control signal; different values of the first control signal and the second control signal respectively correspond to pulse signals with different duty ratios;

outputting a pulse signal corresponding to the value of the current first control signal and outputting a pulse signal corresponding to the value of the current second control signal;

and connecting the far end of the data line (21) to the VSS end according to the duty ratio of the pulse signal corresponding to the value of the first control signal, connecting the far end of the data line (21) to the VDDH end according to the duty ratio of the pulse signal corresponding to the value of the second control signal, and driving the data line from the far end of the data line.

14. The gray-scale dependent remote auxiliary driving method according to claim 13,

subtracting the display signals of the previous line from the display signals of the current line by using the differences of 182-255, 128-181, 64-127, 0-63, -63-0, -127-64, -181-128, -255-182, wherein the corresponding pulse selection signals are 011, 010, 001, 000, 111, 110, 101 and 100 respectively, the corresponding first control signals are 0001, 0010, 0100 and 1000 respectively, and the corresponding second control signals are 1000, 0100, 0010, 0001 and 0001;