JP3382647B2 - Time vernier equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to electronic devices that require accurate and stable placement of signal edges. More specifically, the present invention is directed to a computer- aided test device for testing integrated circuits that adds a time delay to an input signal. The resulting signal is stable to power and temperature variations (ie, has low skew).

[0002]

2. Description of the Prior Art Manufacturers of test equipment for integrated circuits have traditionally utilized bipolar technology to provide timing control. However, high power solutions, such as those implemented in bipolar technology, have functional limitations compared to low power technologies such as CMOS (Complementary Metal Oxide Semiconductor). Moreover, high power solutions often require the addition of water cooling to maintain a workable environment.
Those skilled in the art understand that solutions utilizing CMOS technology rather than bipolar technology can significantly reduce device power requirements and thus avoid water cooling. CMOS technology offers greater functionality with less power.

One aspect of test equipment development is the design of vector formatters. Vector formatters generate the coarse timing edges used to test integrated circuits. The inventor has previously designed a vector formatter that exhibits high performance specifications such as low skew specifications and low jitter specifications in the critical path of an integrated circuit device. However, the coarse timing edges generated by vector formatters generally require some fine tuning. A problem associated with conventional designs is that the output signal of the vector formatter is a BT605 time vernier.
er) (Brook, San Diego, CA)
This is shown by an example in which the fine adjustment is performed by putting it in the ree Corporation). BT60
5 provides precise time adjustment for skew (relative timing between edges) of the input waveform. Since the BT605 is implemented in bipolar technology, the power requirements of the device are large compared to those in CMOS.

In addition, the bipolar solution using BT605 is bandwidth limited by the ramp-comparator method. The ramp-comparator method involves charging a capacitor with a constant current that produces a voltage ramp, which is then compared to a reference voltage using a comparator. Bandwidth is limited due to the need to discharge capacitors between edges. Furthermore, BT
To implement at 605, N BT605 circuits are needed. Where N is the number of functional test pins times the number of data format types per edge. The power and space requirements of this bipolar device are therefore N times higher.

These power and space requirements can be significantly reduced by eliminating the bipolar time vernier and incorporating the functions of the vector formatter and time vernier made in CMOS technology into a single silicon die. The challenge in designing such a device is to design a time vernier utilizing CMOS technology that at least meets the performance of conventional bipolar circuits. This task is a challenge as bipolar technology is usually considered to have higher bandwidth performance than CMOS technology.

Although there are several CMOS time vernier mechanisms that make fine temporal adjustments to coarse timing edges, their skew and jitter performance is inadequate. (Branson and other papers "Integrat
ed PIN Electronics for a
VLSI Test System ", IEEE In
international Test Conferen
ce, 1988, pp. See 23-27. 2.) These existing CMOS devices use multiple delay elements that tap or multiplex to obtain the required delay. Redundant hardware elements and large lookup tables are needed for calibration. These CMOS devices were only used in low performance devices because the skew and linearity performance of such CMOS implementations in the delay line was inadequate with respect to market requirements. Therefore, high power precision bipolar tuning requires high power consuming bipolar subsystems.

As current technology indicates, there is a strong need in the test equipment manufacturing industry for ways to incorporate low cost, high performance, low power time vernier on the same chip with a vector formatter. Its purpose is to eliminate the need for high power and high potential water cooling of the bipolar portion without significantly compromising performance or function. CM
Incorporation of a vector formatter and time vernier using low power technologies such as OS could enable more functionality with a chip that has significantly reduced power and space requirements.

[0008]

SUMMARY OF THE INVENTION The present invention provides an apparatus which is not affected by fluctuations in power supply and temperature, consumes less power, and is capable of imparting a stable and highly accurate time delay to an input signal. The purpose is to provide.

[0009]

The present invention implements a device that utilizes CMOS or equivalent technology to incorporate the required time vernier on the same chip as the vector formatter. The present invention significantly reduces the power requirements of the device, avoids the need for water cooling, and maintains and exceeds the performance of bipolar time vernier. Devices using CMOS technology are very different from devices using bipolar technology,
The inventor could not use the same type of circuit implemented in bipolar technology. As a result, the present invention aimed at new designs that utilize CMOS. Generally speaking, the apparatus and method of the present invention provides a means for incorporating a time vernier on the same chip utilizing a technology such as CMOS rather than bipolar technology so that it can perform more functions at significantly reduced power. It provides the structure of.

The apparatus and method of the present invention is much more rigorous in reducing the possible temporal changes in the logic elements of an integrated circuit due to process, temperature, and power supply variations that occur during chip manufacture and operation. functions to provide a method for obtaining a control. In particular, the skew is reduced in the logic element realized by the CMOS using the pseudo NMOS (n-channel MOS). Pseudo-NMOS circuits have been named because they perform proportional logic, as circuits implemented using NMOS technology do. Second, the pseudo NMOS is an NMO
Depletion load in the S circuit
It is realized using a PMOSFET (p-channel MOS field effect transistor) with a control voltage similar to d). As described herein, a pseudo-NMOS circuit functionally emulates an NMOS circuit even though the pseudo-NMOS circuit is technically not implemented in NMOS.

The present invention can be applied to an electronic device in which the timing of edge placement is delicate. One embodiment relates to a computer-aided test equipment used to test integrated circuits. Pseudo-NMOS devices are used to delay the negative timing edge. Yet another embodiment of the present invention comprises a pseudo-PMOS circuit to control and delay the positive timing edge. Yet another embodiment of the present invention is a pseudo-NMOS / PMO for controlling and delaying both negative and positive edges.
It has an S circuit.

According to the invention, the device comprises a current mirror digital-to-analog converter (DAC) which supplies a control voltage to at least one time vernier subsystem on the integrated circuit chip. Since the DAC is configured as a current mirror, the control voltage from the DAC automatically compensates for temperature and power supply variations that occur on the chip. The time vernier subsystem includes support storage and decoding circuitry for the delay line subsystem. The delay line subsystem comprises delay elements coupled together in a wired OR multiplexer. All critical timing elements have been implemented using the pseudo-NMOS technology described above. As a result, the present invention uses devices for power supply and temperature compensation, and with significantly reduced power requirements and increased functionality as compared to conventional methods, to coarsely adjust the rough edges in time. Control the delay of the timing edge,
An apparatus and method are provided.

Features and Advantages of the Present Invention The present invention overcomes the above-mentioned drawbacks of the prior art and has the following advantages. One advantage of utilizing a pseudo-NMOS device is that a control voltage can be used to set the speed of the device. In essence, changing the reference current allows the user to compensate for process variations, for example. In addition, the pseudo NMOS circuit has a smaller skew due to power and temperature compensation than the standard CMOS circuit, and is therefore a high performance VLSI by itself. Another advantage of the present invention is based on the use of CMOS technology. Since CMOS circuitry Ru can provide more abundant functionality significantly reduces the power requirements as compared to a similar device according to other technologies that require further more power, the device uses a CMOS rather than bipolar technology It is easy to incorporate in other devices that have been realized. Furthermore, C
The use of MOS technology eliminates the need for water cooling required for some applications that utilize bipolar technology.

The present invention is based on a fabrication process between integrated circuit chips .
Automatically calibrate variation and the variation due to the photolithography that. The calibration process is controlled by a calibration logger that can average the data to statistically improve the accuracy of the calibration. In addition, the calibration logger and delay line are configured to allow the circuit to indirectly measure its own delay to the precise timing edge and monitor its own operation during production testing. The present invention comprises a plurality of time verniers incorporated into one analog-to-digital converter to provide the ability to reference several delay lines per integrated chip to provide precision delays for one or more input signals. be able to. The present invention makes these precise delay adjustments by digitally programming the capacitance of the buffer. Finally, the inventive arrangements allow for increased bandwidth (throughput) compared to known devices.

[0015]

In DETAILED DESCRIPTION OF THE INVENTION wide definition, the apparatus and method of the present invention, a more number of functions in greatly reduced power
For demonstration purposes, it will show how to incorporate time vernier on the same chip using CMOS-like technology rather than bipolar technology. The apparatus and method of the present invention comprises:
Operates to provide a programmable delay to one or more input signals having coarse timing edges. The programmable delay provided is first of all stable against power and temperature fluctuations. This stability is necessary to separate the behavior of the circuit under test from that of the test equipment (tester) itself. In particular, pseudo NMOS (n channel MO
S) Skew is reduced for logic devices implemented by CMOS using field effect transistor circuits.

The present invention can be used in electronic devices in which the temporal position of the rising or falling edge of a signal is important. One of the embodiments is in a computer-aided test equipment used to test integrated circuits. The pseudo NMOS circuit is used to delay the negative timing edge. Yet another embodiment of the present invention is a pseudo-PMOS circuit that controls and delays the positive timing edge. In yet another embodiment of the present invention, a pseudo-NMOS for controlling and delaying both positive and negative edges.
/ There is a PMOS circuit. This particular delay is a pseudo PMOS
Can be accomplished by constructing such comprising both PMOS and NMOS control voltage or by an element using the elements and pseudo NMOS device alternately. Pseudo NMOS (also called PNMOS) circuit is NMO
It is so named because it performs proportional logic as circuits implemented using S-technology do. The PNMOS is implemented using a p-channel MOSFET with a control voltage similar to a depletion type NMOSFET.
Pseudo P realized by using n-channel MOSFET
MOS devices can also be considered.

The threshold voltage of conventional depletion-type MOSFETs is negative, which means that the channel of the FET conducts with O volts applied to its gate electrode. In the case of pseudo-NMOS, the control voltage is applied to the gate electrode of the PMOSFET of a standard CMOS device, so that the PMOSFET remains conductive at all times. As an example, the pseudo NMOS inverter is formed by driving the gate of the PMOSFET of the CMOS inverter with a control voltage. Therefore, the PMOSFET remains on. As a result, the CMOS inverter behaves like an NMOS inverter whose load FET, which is coupled to the power supply voltage, is always on and whose input signal is used to control the gate of the NMOSFET of the CMOS inverter. Therefore, the pseudo-NMOS device has a pure N
A PMOSFET and N that emulate a MOS inverter, even if it is not technically an NMOS device.
Formed from standard CMOS using MOSFETs.

The present invention will now be described with reference to the block diagrams shown in FIGS. Referring to FIG. 1, a block diagram shows the high-level structure of a time vernier device 101, which is designed to scale from a variable number (n) of input signals 103 with coarse timing edges. Adjusted timing edge (fine adjustment
It is used to generate a variable number (n) of well controlled output signals 102 with edges . The device 101 comprises two basic blocks, a current mirror digital-to-analog converter (DAC) 104 and a TV1, TV respectively.
2, and one or more time vernier blocks 106, 108, and 110, referred to as TVn. Each time the vernier 106-110 is the input signal 10
3 can be used to generate a time delayed output signal 102. The n input signals 103 are provided to one of the time verniers 106, 108, or 110, for example, to adjust a coarse timing edge to produce an output signal 102 having a finely adjusted timing edge .

The current mirror DAC 104 includes a control voltage signal (PCNTRL) 1 that automatically compensates for temperature and power supply variations, as described in detail below in connection with FIG.
12 is generated. Current mirror DAC 104 is a delay system
It can be programmed to be able to adjust the PCNTRL signal 112 in order to perform the control. This control can also be used to adjust for process variations. The PCNTRL signal 112 is the time vernier device 10
Time vernier 106, 10 installed on one chip
8 and 110 respectively.

FIG. 2 shows a block diagram of one of the time vernier subsystem 106 and its supporting circuitry. As shown in FIG. 2, the time vernier subsystem 106 is a PCNT.
It receives the RL signal 112 and the data input signal 203 and produces a data output signal 204 by the function of the time vernier and support circuitry. In particular, the support circuit of the time vernier 106 comprises a delay line 206. Delay line 206 comprises one or more delay element blocks 210, 212, and 214 as well as a block 208 consisting of a wired-OR multiplexer (MUX) 215. Wired ORMUX
215 is electrically connected to delay elements 210-214 via connection 216. Delay elements 210 and 212
To 214 and the characteristics of the delay line 206 are described below.
And will be described in detail with reference to FIGS. 5 and 6 and FIGS. 7 and 8 , respectively.

FIG. 3 shows a block diagram of one of the delay elements 210 included in block 208. Delay element 210
Acts to add a finite amount of capacitance to precisely delay the input signal 203 by digital control. Delay element 210 also receives control bus input 306 in addition to PCNTRL signal 112 and input signal 203. P
The CNTRL signal 112 is input as a voltage to the pseudo NMOS inverter 307, and the inverter 307 inputs the input signal 2
Invert 03 and buffer. A set of capacitor rows 30
8 is connected to the internal node 310. Capacitor bank 308 provides a programmable capacitance for internal node 310. Therefore, a finite amount of capacitance can be added to internal node 310 by digital control. In particular, the capacitor bank 308 is the control bus input 3
Binary Thermometer Decoding Logic Unit 312 Powered by 06
Is turned on via. Decoding logic 312 may include capacitor array 30 according to a particular input depending on the particular application.
Add binary control to 8. Decoding logic 312 also performs thermometer decoding to further control the capacitor train to reduce device non-linearity.

Node 310 receives a specified amount of capacitance from capacitor bank 308, but with P as the control voltage.
It is used to control the second pseudo-NMOS inverter 314 which also receives the CNTRL signal 112. Node 31
The signal present at 0 is inverted again by inverter 314 to produce a delayed, finely tuned output signal 316 having the same logic state as input signal 203. DAC1
04 because are based on the stable constant current source as described in detail below, PCNTRL signal 112 automatically adjusts for variations in temperature and power supply. In other words,
From a theoretical point of view, a "constant" delay occurs regardless of power and temperature variations, thus giving the device a unique way of compensating for temperature and power.

A representative logic diagram of the DAC 104 of the present invention will now be described with reference to FIG. The DAC 104 is shown connected to a pseudo-NMOS (PNMOS) programmable capacitor delay element 210 via a control voltage or PCNTRL signal 112 which is tapped off at node 408. The DAC 104 has a PMOSFET 410 whose gate and drain are connected to the analog power supply 412.
Is equipped with. These connections create a node 408 that automatically adjusts to reflect (mirror) the same amount of current (IREF) provided by current source 412. Multiple PMOSFET rows 414, 416, 418, 42
0, 422, and 430 allow node 408 of DAC 104 to make small voltage adjustments to node 408.
It is switchably connected to. In the preferred embodiment, row 4
14 has one FET, column 416 has two FETs, column 418 has four FETs, column 420 has eight FETs, column 422.
.About.430 each have 16 FETs.

The voltage regulation is controlled via a digital input 432 which specifies the required regulation in digital fashion.
As illustrated by decoder 434, digital input 432 is decoded to switchably connect a given FET string to node 408. This allows a predetermined amount of FET width from columns 414-430 to be added to the width of PMOSFET 410. The output line from decoder 434 corresponding to column 414 represents the least significant bit (LSB) and the line corresponding to column 430 is the most significant bit (MSB).
Is represented. The current reflected in the PNMOS delay element 210 is specified by the width-to-length ratio of the total number of predetermined PMOSFETs in the DAC 104 and the width-to-length ratio of the PMOS delay element 210. This relationship is shown below in the form of an equation.

[0025]

[Equation 1]

The width of the FET of the current mirror DAC 104 is variable as expressed by the following equation. WDAC = Wo + NWi where Wo = the initial equivalent channel width of the device, N = the value of the digital input 432, Wi = the channel width of the LSBFET and therefore the reflected current is:

[0027]

[Equation 2]

Although these equations assume that the respective FETs are all saturated, this is not always true. Nevertheless, these equations serve to illustrate the operation of the DAC device. Since the output voltage (PCNTRL 112) is controlled by the current mirror, DAC 104 compensates for temperature and power supply variations such that IREF is reflected as shown in the above equation. Two different forms of decoding are utilized by decoder 434. In the preferred embodiment, a plurality of PMOSFETs
The column is connected to the DAC 104 at node 408. P
MOSFET rows 420-430 provide the MSB (most significant bit) to the current mirror. These bits are decoded using a thermometer decoding method that decodes in increments without binary weighting. Table 1 shows an example of thermometer decoding for values from 0 to 3.

[0029]

[Table 1]

In contrast, PMOSFET rows 414-41
8 supplies the LSB (least significant bit) to the current mirror. These columns are selected using a binary decoding method that decodes according to standard binary weighting. The split point between binary decoding and thermometer decoding depends on the particular application.
In the preferred embodiment, an FE consisting of 16 PMOSFETs.
The split points in column T give a 16: 1 MSB to LSB ratio. This ratio is 64: 1 MSB to LSB if exact binary decoding is used throughout the group of FET strings.
It is different from the ratio. The net effect is that the processing mismatch of the device shrinks to a 16: 1 MSB to LSB ratio.

The transfer function for voltage at node 408 is non-linear and inversely proportional to N. Here, N is the value of the digital input 432. P generated at node 408
The CNTRL signal 112 is the variable capacitance delay element 2
A delay element 210 connected to 10 allows a specific delay to be applied to the input signal 203 having coarse timing edges. The delay element 210 produces a finely tuned output signal 316, as described below (see FIG. 3). Digital input 432 and PCNT
As a function of the RL signal 112 (the reflected current at node 408) is inversely proportional to N as follows:

[0032]

[Equation 3]

Here, VGS is equivalent to PCNTRL signal 112 related to positive supply voltage 411, and VT is PM.
OSFET 410 and PMOSFET array 414-43
The threshold voltage is 0. However, although the voltage and current from the DAC 104 are both inversely proportional to N, the delay element 2
The delay reflected in 10 is proportional to digital input 432. This feature of the invention is best illustrated by considering the amount of time required to charge the capacitor C with a constant current I = C (dV / dt) or approximately ΔT = CΔV / I. it can. Substituting I for the current reflected from DAC 104 into the above equation yields:

[0034]

[Equation 4]

Therefore, the linear delay for the above situation is the true delay.

[0036]

[Equation 5]

Individual delay amount

[0038]

[Equation 6]

It is obtained by adding the digital programming from the digital input 432 to the addition of. Figure 5
Next, the delay element 210 of the present invention shown in FIG. The basic structure of the delay element 210 is composed of a pseudo-NMOS buffer or a pseudo-PMOS buffer, which is assembled from two pseudo-NMOS or pseudo-PMOS inverters 307 and 314, and the inverter 307.
And 314 with a programmable capacitance 308 added to an internal node 310. The pseudo NMOS circuit shown in FIG. 5 provides fine adjustment of the negative timing edge of the input signal 203. The pseudo PMOS circuit is shown in FIG. 6 and provides fine adjustment of the positive timing edge of the input signal 203. Similar reference numbers in these figures indicate identical or functionally similar elements.

The PMOSFETs 502 and 504 of the embodiment of the pseudo NMOS inverter shown in FIG. 5 and the NMOS of the embodiment of the pseudo NMOS inverter shown in FIG.
The gates of FETs 602 and 604 are driven by the PCNTPL signal 112 generated by DAC 104. As explained above, the independent variable N represents the digital input 432 to the DAC and the transfer function between the output signal of the current mirror and the digital input is inversely proportional to N. Since the DAC is associated with a stable constant current source,
The PCNTRL signal 112 automatically adjusts for temperature and power supply variations. Therefore, temperature and power compensation is pseudo N
This is done for MOS or pseudo-PMOS inverters.

The PCNTRL signal 112 is used to regulate the charging current into the variable capacitance 308 (reflected from the DAC) and the delay of the buffer 210. In the present invention, the PCNTRL signal 112 is also used to cancel out process variations, and thus to obtain a normal time delay. By changing the mirror ratio of the DAC, the charging current changes. The time to charge the internal node is inversely proportional to the charging current. However, the charging current is DACF
Inversely proportional to ET width. Therefore, the net result is that the delay increases proportionally to the width of the DACFET, as described above.

Variable capacitance 30 relevant to the present invention
8 is obtained by modulating the gate-source voltage (VGSS) of one or more NMOSFETs. Each NMO
The gate of the SFET is connected to the internal node of the buffer 210. The source and drain electrodes are connected together. The gate capacitance can be effectively switched in and out of the circuit by bringing the source-drain node to a negative or positive supply voltage, respectively.
Therefore, a small amount of precisely controlled capacitance can be added to internal node 310 by digital control. As will be apparent to those skilled in the art, capacitor F
The size of ET is chosen to correspond to the precise timing resolution required for the application of this invention. The number of capacitors attached to the internal node depends on the required dynamic range. Since the delay of the device is directly proportional to the capacitance of the internal node, this approach makes the relationship between the programmed value of the capacitor and the delay of the circuit linear. In the case of the present invention, the higher order capacitors are configured as a capacitor array to reduce non-linearity.

The pseudo NMOS device of FIG. 5 is used to delay the negative timing edge. Another embodiment of the present invention comprises a pseudo-PMOS circuit that delays positive timing edges with good controllability (see FIG. 6). Yet another embodiment of the present invention comprises a pseudo-NMOS / PMOS circuit which controlslably delays both negative and positive edges. This particular delay can be achieved by alternating the use of pseudo-PMOS (PPMOS) and pseudo-NMOS (PNMOS) devices, or by configuring the device with both PMOS and NMOS control voltages.

Referring again to FIG. 5, the PNMOS delay element 210 includes an inverter 307 and an inverter 31.
4 and various capacitor rows 518, 524, 528,
534, 538, and 544, which are generally designated by 308, are shown in FIG.
12 and is connected in parallel to the internal node 310. The inverter 307 includes a PMOSFET 502, the gate electrode of which is the PCNTRL signal 112.
It is connected to the. PMOSFET 502 remains on all the time, but its conductance can be adjusted by changing the voltage on PCNTRL signal 112. Adjusting this voltage modulates changes in the capacitance of internal node 310. The inverter 307 is an NMO
It also comprises an SFET 506, which receives the input signal 203 connected to its gate electrode. PMOSF
The ET 502 and NMOSFET 506 work together to invert the input signal 203. The inverted output signal from inverter 307 is delayed at node 310 by the previously described capacitor string 308 that is switchably connected to the node.

The lower order capacitor series (FET series consisting of less than 8 FETs) are activated by control signals G1-G3 (see lines 520, 522, and 526, respectively). Once activated, i.e. conductive,
The FET operates like a capacitor, absorbs the electric charge from the node 310, and turns the inverter 307 to the inverter 3
The signal transmitted to 14 is delayed. The control signals G1-G3 are Boolean coded to provide another capacitance at node 31.
Add to 0 linearly. The higher order bits (FET string consisting of 8 or more FETs) are activated by control signals G4 and G5 (see lines 530 and 532, respectively). The control signals G4 and G5 are thermometer coded to minimize device mismatch due to process tolerances. Line 52
0, 522, 526, 530, and 532 comprise the control bus 306 described above in connection with FIG.

The first capacitor bank 518 has a single NMOSFET whose gate is connected in parallel to node 310, similar to a shorted source-drain node controlled by the gate control input signal G1 on line 520. I have it. G1 is logically inverted and buffered by the inverter 521. The input signal G1 is the least significant bit (LSB) of the control word consisting of the input signals G1 to G5. Line 52
The two gate control input signal G2 is inverted and buffered by the inverter 523 to control the shorted source-drain node of the pair of parallel connected FETs forming the capacitor bank 524. Capacitor string 524 is connected to node 310 to control the next significant bit of the node. The gate control input signal G3 on line 526, which is inverted by inverter 527, controls a group of four FETs forming a capacitor bank 528. Capacitor bank 528 is connected in parallel to node 310 through the gate of capacitor bank 528 to control the next significant bit of the node.

A logical NOR gate 529 of gate control input signal G4 on line 530 and gate control input signal G5 on line 532 controls the source-drain node of capacitor string 534. Column 534 consists of eight NMOSFETs that provide the next significant bit of delay to node 310. The inverter 535 has a gate control input signal G4.
Generates an inverted output signal 536 of The output signal 536 is
Controls the source-drain node of a capacitor bank 538 of eight NMOSFETs that provides the capacitance delay for the next significant bit at node 310. Gate control input signals G4 and G5 are applied to respective inputs of logical NAND gate 540. Logical NAN
The output signal of D540 controls the source-drain node of capacitor string 544. Capacitor bank 544 is composed of eight NMOSFETs that provide the MSB (most significant bit) capacitance delay to node 310.

The FETs of the first four-capacitor string are arranged in binary (1, 2, 4, 8) to achieve the programmed capacitance capability as indicated by the binary decoding supplied to inputs G1 to G3. Note that it is done. The two MSBs, G4 and G5, are the capacitor bank 3
08 is eight NMOSF instead of the next 16 binary equivalents
Thermometrically decoded to consist of ET. Thermometer decoding is a capacitor array 53 consisting of three 8 FETs
4, 538, and 544 are such that they turn on monotonically as input signal G4 and input signal G5 increase from binary 0 (002) to binary 3 (112). Node 310 provided by capacitor string 308
Is the input signal to the gate of the NMOSFET of the inverter 314. The inverter 314 is an NMOSF
The ET 508 and the PMOSFET 504 are provided, and the PCNTRL signal 112 is PM so that its conductivity can be adjusted.
It is connected to the gate of OSFET 504. Node 3
10 delayed data signal is inverted and logically input signal 2
Data output signal 316 (O
UT) is generated.

Referring again to FIG. 6, the pseudo PMOS delay element is the p-channel FET 6 of the first inverter 307.
02 has an input 203 connected to the gate. The output of the first inverter 307 is connected to the gate of the p-channel FET 604 of the second inverter 314, and the PCNTRL signal 112 is the p-channel FET 60.
Connected to the gates of 6 and 608. By inverting the control signal and the input signal, the positive timing edge can be delayed with good controllability. The delay line 2 of the present invention
06 will be described below. The delay line is a structural combination of a delay element 210 electrically coupled to a PNMOS Wired-OR Multiplexer (MUX) 215 (see FIG. 2). In particular, a group of delay elements are arranged in series so that the data output from one delay element is connected to the data input of the next delay element. One part of this group of stacked delay elements is used to add a fine increment of delay to the input timing edge, and the other part of this group of stacked delay elements is used to add a coarse increment of delay. . A further part of this family can be used for calibration.

Referring now to FIG. 7, the delay line 2 of the present invention.
A logic diagram of a high level structure comprised of ten preferred embodiments is illustrated. Delay line 210 includes delay elements 706-726 and a PNMOS wired ORM connected in series.
It is equipped with UX215. Delay elements 706, 708, and 714 are precision delay elements F1, F2 ,. ． ． , Fn, and delay elements 716, 718, and 726 are coarse delay elements C1, C2 ,. ． ． , Cn. The input signal 203 with the coarse timing edge is applied to the input of element 706.

The number of delay elements depends on the required use of delay line 206. Precision delay elements (F1, F2, ..., F
In the number n), the combination range of the precision delay elements includes one coarse delay, but does not exceed the maximum true delay specification. True delay = precision true delay + delay of MUX total delay = true delay + precision program delay + coarse program Selected to be delayed.

Each precision delay element comprises a control bus 306 of FIG. 3 and control inputs GF1-n [1: 5] corresponding to lines G1-G5 of FIGS. 5 and 6. Control input GF1-
n [1: 5] specifies the amount of delay to be added by the corresponding precision delay element. Similarly, each coarse delay element has a control input GC1-n [1: 5] that specifies the amount of delay to be added by the corresponding coarse delay element. Final fine delay element Fi and all coarse delay elements 716-72
6 are their respective outputs D [1], D [2] ,. ． ． D
It branches along the PNMOS wired ORMUX 215 at [N]. The nominal coarse delay is set by controlling a respective capacitor bank for each coarse delay element.
Therefore, the PNMOS wired ORMUX 215 operates to add the nominal coarse delay integer S [1: N] to the incident edge and then branch the incident edge, as specified by the predetermined bus 748.

Select bus 748 is a PNMOS wired OR
Each tap output signal D received by the MUX 215
Individual digital control is performed for [1] to D [N].
The bit size of select bus 748 depends on the particular application. In addition, the PNMOS wired ORMUX 215 receives the PCNTRL signal 112 which operates to control the PMOS gate of its pseudo-NMOS device. Delay line 206
Are delay elements F1 ,. ． ． , Fn produced by the coarse delay elements C1 ,. ． ． , Cn, and the coarse delay generated by Cn. Therefore, the fine edge (FE) output signal 204 is obtained from the coarse edge (CE) input 203 after the appropriate amount of fine and coarse delay has been added. FE output signal 204 is also precision delay and PNMOS
It has a constant intrinsic delay component added by the wired ORMUX 215.

FIG. 8 shows a level diagram of a field effect transistor (FET) of the multiplexer embodiment of the PNMOS wired ORMUX 215 of FIG. 7 of the present invention. PNMO
The S-wired ORMUX 215 is implemented using pseudo-NMOS technology. The bus 216 is a delayed input signal D
[1], D [2] ,. ． ． Supply the required inputs to the MUX 215 from some number (N) of D [N]. PNMOS wired ORMUX 215 receives PCNTRL signal 112 and controls the PNMOS gate of the pseudo-NMOS device of PNMOS wired ORMUX 215. N inputs (S
[1: N]) select bus 748 performs digital control and provides N delayed input signals D [1], D [2] ,. ． ． D
Select one from [N]. Multiple NMOSFETs
802a, 802b ,. ． ． , 802n corresponds to P
MOSFETs 822a, 822b ,. ． ． , 822n and inverting output nodes 842a, 842
b ,. ． ． , 842n are formed. Each delayed input signal D [1] to D [N] corresponds to the corresponding NMOSFET 8
02 is connected to the gate. PNMOS wired O
In this PNMOS configuration of RMUX 215, each P
The MOSFET 822 is controlled by the PCNTRL signal 112, which results in the same pseudo-NMOS power and temperature compensation characteristics. Each inverting output node 842 may be selected with the signal S [1: N] via the select bus 748, but N connected in parallel to the respective node 842.
MOSFET 862a, 862b ,. ． ． , 862n. The individual lines of select bus 748 are negative true,
Only one select line (S [i], L = 1 to n) can be active at one time.

Finally, the digitally selected node 842 carries inverting delay inputs D [1] -D [N], respectively, but the corresponding NMOSFETs 882a, 882.
b ,. ． ． , 882n. These NMO
Each of the SFETs 882 is connected in parallel to the PMOSFET 897 to invert predetermined inversion delay inputs D [1] to D [N] at the respective nodes 842 to select the delay inputs D [1] to D [D] selected by the selection bus 748. It forms a second inverter that produces an output signal 204 that is logically consistent with [N].

In summary, the PNMOS wired ORMU
The X215 comprises a PNMOSOR circuit, each with an open drain output. All open drain outputs have one PMOS pull-up FET 897 whose gate is driven by PCNTRL signal 112.
It is connected to the. One output of each PNMOSOR is driven by a delay line tap. The other input of each PNMOSOR is driven by a select input that operates to enable or disable a particular tap. In one embodiment of the invention, only one tap may be available at a time. When the incident edge is on the available tap, the signal is PNMO
The signal is transmitted through the SOR circuit, pulls down the common PMOS pull-up FET, and transmits the branched signal to the output of the MUX. A common pull-up FET "wires" (electrically connects) all open drain nodes to it.
In this state, it operates as an OR gate (wired OR),
Causes the active tap to be transmitted to the output.

Since the present invention can be applied in an integrated circuit (IC) test environment that requires the ability to compensate for temperature, power supply, and process variations, it separates the behavior of the circuit under test from the behavior of the test equipment. It is necessary to be able to.
Therefore, this configuration is a pseudo NMOS (called PNMOS)
A method of calibration using a fine / coarse wired-OR tap delay line and support circuitry is provided. The support circuit comprises: 1) a data register for receiving a digital value representing the required time delay to be added to the input signal with a coarse timing edge; 2) a RAM, which serves as a calibration memory for the fine delay portion of the programmed digital delay. ) A register train serving as a calibration storage device for the coarse delay portion of the programmed digital delay,
4) a decode circuit for each fine and coarse portion of the programmed digital delay input to the PNMOS wired-OR tapped delay line to obtain the required precision (FE) output signal, and 5) a calibration circuit to support various calibration procedures. It consists of

FIG. 9 shows a block diagram of the time vernier 106. The time vernier 106 is used to generate a well-controlled fine timing edge output from a coarse timing edge input. The data bus 904 supplies the input data signal 906 to the alpha register 908. Input data signal 906 specifies the required program digital delay stored in alpha register 908. Most significant bit of value stored in alpha register 908 (MS
B) is received by coarse decode 910 via bus 911. The least significant bit (LSB) of the value in alpha register 908 defines the precise delay to be provided by time vernier 106, but via bus 918 RAM 91.
Received as an address to 2.

The coarse decoder 910 is an alpha register 90.
Decode the MSB of the value stored in 8 and select input 91
4 is supplied to the delay line 206 with a PNMOS wired OR tap. PNMOS wired OR delay line with tap 2
06 selects one tap to the delay line and operates to combine the coarse delays specified by the input data signal 906. Register bank 918 is accessible from data bus 904 via bus 919 and to PNMOS wired-OR tapped delay line 206 via bus 920. It serves as a storage device for the calibration data required by the coarse delay elements that internally comprise the PNMOS wired-OR tapped delay line 206.

The RAM 912 serves as a storage device for the precision delay calibration data designated by the least significant bit (LSB) of the value stored in the alpha register 908.
The bus 912 accesses the RAM 912 from the data bus 904. The bus 922 provides access to the precision delay decoder 924 from the RAM 912, but the decoder 924
Serves to decode the binary data in RAM 912 into a combination of binary decoding and thermometer decoding. This combinatorial decoding improves linearity. The thermometer decoding is used between a plurality of delay elements (inter-delay elements) forming the delay line 206 with the PNMOS wired OR tap. Binary decoding is PNMO
The S-wired OR delay line 206 is used inside each delay element (intra-delay element). Bus 926 is from precision delay decoder 924 to PNMOS wired-OR delay line 20.
Access to 6.

Still referring to FIG. 9, an input signal 203 with coarse timing edges or to be added with a time delay is input to the final flip-flop-1 (LFF1) 930 along with the device clock signal CLK932. . The output stage of the (LFF1) 930 is composed of a PNMOS for compensating the power supply and temperature. The input signal 203 is timed to generate a CE (coarse edge) signal 934 to be input to the PNMOS wired-OR tapped delay line 206 of the time vernier 106. P
Delay line 206 with NMOS wired OR tap is also PNM
It receives the PCCTRL signal 112 as a control voltage for the OS device. A well-controlled delay edge corresponding to the program delay received via the input data signal 906 is a precision edge (F
E) It is output as the output signal 204.

In addition, the CE signal 934 is input to the D input of the LFF2 (final flip-flop 2) 940, which is also timed by the device clock signal CLK932. The delay characteristic of the (LFF2) 940 is (LFF2).
Since it should match the characteristics of (F1) 930, it is actually the same as (LFF1) 930. In the next device clock signal CLK932 after receiving the CE signal 934, (L
The FF2) 940 supplies the reference edge signal PCLK942 to the phase detector 944. The phase detector 944 also receives the FE signal 204. The phase detector 944 compares the delay of the delay line period i.e. device clock period of the device clock signal <br/> No. CLK932 determined by FE signal 204. PHDOUT
Output signal 946 specifies a logic "1" if the delay of the delay line indicated by FE signal 204 is less than one clock period of signal PCLK942. In other cases, PH
The DOUT output signal specifies a logic "0".

Calibration is necessary for several reasons. The need for calibration includes process variations from different lots of the same chip or equipment mismatch on the same chip. The arrangement of the present invention supports three preferred calibration procedures. 1) PCNT
RL calibration. This compensates for process variations. 2) Precision delay calibration. This compensates for device mismatch within the precision delay element.
3) Coarse delay calibration. This compensates for device mismatch within the coarse delay element. Depending on the specific equipment requirements, some or all of the above calibration procedures may or may not be required.

Each of the above calibration procedures requires a precise time base. This time reference appears in the form of the precisely controlled conventional clock period signal CLK932 of FIG.
The method of calibration is controlled by a digital control circuit (calibration logger), which allows averaging of the data to statistically improve the calibration. One of ordinary skill in the art will readily recognize a number of conventional techniques for storing and counting calibration loggers. The characteristics of the calibration logger are not necessary for those skilled in the art to practice the present invention. The calibration logger can consist of several counters and registers, and digital logic or the like. The purpose of the logger circuit is to monitor and store the total counts of the output results of several phase detectors and to compare them with a threshold preprogrammed in the calibration logger. By this comparison, it is possible to determine whether the timing edge in question by the calibration logger has the required timing. The calibration logger is also a means by which the circuit indirectly makes sensitive timing measurements and thus tests itself during production testing.

The calibration procedure is the device clock signal CLK of FIG.
This can be explained by reference to two consecutive rising edges of 932. First edge is CE delay line 206
To the second flip-flop (LFF2) 94
Assemble 0. (LFF2) 940 is timed by CLK932 and produces output PCLK942,
This then becomes the second clock which drives the phase detector. Therefore, if the device clock period, which is the time between two consecutive rising edges of the device clock signal CLK932, is programmed to be the delay required by the delay line 206, the output FE 204 will output a second clock, PCLK9.
42 becomes high level at the same time as its rising edge.
If the signal edge of FE output 204 and the signal edge of PCLK942 are not as described above, FE output 204
Is out of calibration. In this case, the set value of the delay line 206 is set to the signal edge of the FE output 204 and PCLK942.
Adjust until the signal edges of are aligned as described above. The results of this calibration process can be used for precision calibration, coarse calibration, or PCNTR.
Depending on which of each of the L signals 112 is being calibrated, it is either stored in RAM 912, register 918 or used to adjust the DAC setpoint. Essentially P
HDOUT946 is a phase locked loop function emulates, to be able to calibrate the present invention to meet the constant Di <br/> digital desired delay that by the delay line 206 through adjustment of the period of the clock Drive the feedback section.

FIGS. 10, 11 and 12 show a flow chart of the calibration method utilized with the preferred embodiment of the present invention shown in FIG. Figure 10 shows PCNT that compensates for process variations.
6 is a flow chart of a method of RL calibration. Referring to FIG.
The calibration procedure for the PCNTRL signal 112 programs all delay elements inside the PNMOS wired-OR tapped delay line 206 to the nominal capacitor settings. PC
The NTRL calibration procedure begins at block 1001 and sets the time reference ( device clock signal CLK932) to the required frequency. In this example, which aids in explaining this method,
If the delay to be calibrated is 8 ns, the time reference CLK93
2 should be set to a period of 8 ns. This set value means that the time between one rising edge and the following rising edge is 8 ns. It is noted that if the nominal delay of each delay element in delay line 206 is 2 ns in this example, then four delay elements are required for delay line 206 to generate the required delay of 8 ns. The DAC 104 generates the PCNTRL signal 112 to be calibrated, but the minimum PCNT
To generate the RL signal 112, it is set to its minimum setting, as shown in block 1002. In the present embodiment , this minimum setting for the PCNTRL signal 112 allows the delay line 206 to generate a delay less than the required delay of 8 ns to approach the required delay of 8 ns by slowly increasing the PCNTPL signal 112. Note that you must be able to.

Next, block 1004 indicates that the timing edge is an input to the time vernier 106 by the input signal 203. Block 1006 PCL the delayed edge, FE output 204, with phase detector 944.
K942 (this is generated from the time base CLK932,
It has the same clock period). As mentioned in the description of FIG. 9, the PHDOUT output signal 946 specifies a logic "1" if the delay of the FE signal 204 from the delay line 206 is shorter than the device clock period of the PCLK signal 942, and otherwise, PHDOUT
Output signal 946 specifies a logic "0". Next, the external calibration logger will use PHDOUT as indicated by block 1008.
The output signal 946 is recorded, which counts the number of times the output is high.

Decision block 1009 indicates that the process repeats from block 1004 N times. However, N
Is the digital number programmed into the calibration logger. The repetition of this cycle from blocks 1004 to 1009 is performed so that the delay of the delay line 206 is the time reference CLK93.
Necessary when approaching 2 cycles. This is because, at this point, the phase detector 944 enters an unstable mode in which the output becomes uncertain, and therefore the output must be determined by probability. Therefore, as N increases, the probability that the correct output will be correctly determined increases.

Decision block 1010 is stored as a calibration logger value representing the total number of times the phase detector 944 returned a "1" result in that the correct output was reasonably determined by N consecutive iterations. Determine if the count value is greater than or equal to an independent programmable threshold. If so, as indicated by block 1012, each delay element is equal to the nominal delay, which means that the delay of delay line 206 is approximately calibrated to the delay specified by the period of time reference CLK 932. To do. Therefore, PCNTRL signal 1
12 is now calibrated for manufacturing process variations. Otherwise, the DAC controlling the PCNTRL signal 112, as indicated by the "No" branch from block 1010.
The set value of 104 is increased by 1 LSB to increase the PCNTRL signal 112 and thereby the delay provided by each delay line that comprises delay line 206. The decision block 1010 is block 101.
Repeat from block 1004 until the "Yes" branch to 2 is followed.

FIG. 11 is a flow chart of a method of precision delay calibration that compensates for device mismatch of the precision delay element. In essence, the precision delay element is calibrated for on-chip photolithography variations. The precision delay calibration procedure is based on the time base (CLK
932) to block 1 by setting the required frequency
Starts with 101. A real book to help explain this method
In facilities example, the required delay to be calibrated if 8 ns, should set the time reference CLK932 to the period of 8 ns.
This set value means that the time between one rising edge and the following rising edge is 8 ns. Next, block 1102 compares the setting value of the capacitor for the precision delay element included in the delay line with the PNMOS wired-OR tap to the minimum setting value (the minimum setting value of the delay of the precision delay element).
To respond. ) Is set. In the case of this example, this corresponds to a fine delay of less than 8 ns.

Next, block 1104 shows that the timing edge is input to the time vernier 106 via the input signal 203. Block 1106 provides the delayed edge, FE output 204, to the PC by phase detector 944.
LK942 (which is generated from the time reference CLK 932 and has the same device clock period). As described in the description of FIG. 9, PHDO
The UT output signal 946 is the delay line 206 of the FE signal 204.
If the delay from is less than one clock period of the signal PCLK942, specify logic "1", otherwise P
HDOUT output signal 946 specifies a logic "0". The external calibration logger is then set to P 1 as indicated by block 1108.
The HDOUT output signal 946 is recorded, which counts the number of times the output is high.

Decision block 1109 indicates repeating the process from block 1104 N times. Where N
Is the digital number programmed into the calibration logger. This cycle of blocks 1104 to 1109 is repeated so that the delay of the delay line 206 is the time reference CLK93.
Necessary when approaching 2 cycles. This is because at this point the phase detector 944 enters an unstable mode where the output is uncertain and therefore the output must be determined by probability. Therefore, as N increases,
The probability that the output is correctly determined increases. At decision block 1110, the system determines if the count value stored as a calibration logger value representing the total number of times the phase detector 944 returned a logic "1" result is greater than or equal to an external independently programmable threshold. To do. If it is not above the threshold, then the capacitor of the precision delay element is increased by one setpoint, as indicated by block 1191, and the process 1104
Repeat from. If the determination at block 1110 is “yes”, then block 1112 calibrates the first fine delay setpoint to the required fine delay, this time for variations in on-chip photolithography, and stores the result in RAM 912.

Since the method includes multiple fine delay settings, decision block 1114 checks if all the fine delay settings have been calibrated. If not,
The precision delay element capacitors are switched to a minimum setpoint, as indicated by block 1115. Next, time reference CLK
932 is increased by one delay element resolution, as indicated by block 1116. The process then repeats from block 1104 for this next fine delay setting. The calibration method for the precision delay element is complete when all the precision delay settings have been calibrated, as indicated by block 1117.

FIG. 12 is a flow chart of a preferred method of coarse delay calibration that compensates for the device mismatch of the coarse delay element. In essence, the coarse delay element is calibrated for on-chip photolithographic variations and variations due to tapped delay lines. The coarse delay calibration procedure begins at block 1201 and sets the time reference (CLK932) to the required frequency. Next, block 1202 depicts programming the first coarse delay element capacitor setting inside the PNMOS wired-OR tapped delay line 206 to its minimum setting. Note that this minimum setting corresponds to a total delay less than the "Delay Required". Block 1204-1
The coarse delay calibration procedure shown at 211 is exactly the same as the procedure, blocks 1104-1111, described above in connection with FIG. Therefore, detailed description of the blocks 1204 to 1211 will be omitted. However, if the determination at block 1210 is “yes”, then the first coarse delay element is calibrated to the required coarse delay for changes in on-chip photolithography and the result is stored in register 918, as shown at block 1212. Store.

Since the method of FIG . 12 may include multiple coarse delay elements, decision block 1214 checks to see if all the coarse delay elements have been calibrated. If not calibrated, replace the precision delay element capacitor
As shown in step 1215, the resolution is switched to the required resolution. In this case, the time reference CLK 932 is set in the block 121.
As shown at 6, it increases by one delay element resolution, but in fact this includes the next coarse delay element in the calibration. The process then repeats from block 1204 for this next coarse delay element. The coarse delay element calibration is complete when all the coarse delay elements have been calibrated, as indicated by block 1217. While various embodiments of the invention have been described above, it should be understood that they have been presented by way of example and not limitation.

[0076]

As described above, by using the present invention, the power delay, the temperature, the process, etc. are not affected, the power consumption is small, and the stable and highly accurate time delay with respect to the input signal is achieved. It is possible to realize a device capable of giving.

[Brief description of drawings]

FIG. 1 is a high level block diagram of the time vernier system of the present invention.

2 is a high level block diagram of the temporal vernier subsystem shown in FIG. 1 of the present invention. FIG.

FIG. 3 is a block diagram of one of the delay elements of FIG. 2 of the present invention.

FIG. 4 is a block diagram of a digital-to-analog converter system of the present invention.

FIG. 5 is a representative logic diagram of a pseudo-NMOS delay element of the present invention.

FIG. 6 is a representative logic diagram of a pseudo PMOS delay element of the present invention.

FIG. 7 is a representative logic diagram of the delay line of the present invention.

FIG. 8 is a representative logic diagram of the wired OR multiplexer of the present invention.

FIG. 9 is a block diagram of the time vernier of the present invention.

FIG. 10 is a PCNTRL used in an embodiment of the present invention.
It is a flowchart of a signal calibration method.

FIG. 11 is a flowchart of a fine delay calibration method used in an embodiment of the present invention.

FIG. 12 is a flowchart of a coarse delay calibration method used in an embodiment of the present invention.

[Explanation of symbols]

206: PNMOS wired OR delay line with tap 908: Alpha register 910: Coarse decoding 912: RAM 918: Register 924: Precision delay decoder 944: Phase detector

Continuation of the front page (31) Priority claim number 786,695 (32) Priority date November 1, 1991 (1999.11.1) (33) Priority claim country United States (US) (31) Priority claim No. 786,459 (32) Priority date November 1, 1991 (1999.11.1) (33) Priority claiming country United States (US) (72) Inventor Christopher Kena Longmont Boulder, Colorado, United States・ Hills Drive 5699 (72) Inventor Masaharu Goto 691-19 Nakato Shimogo, Hanno City, Saitama Prefecture, Japan (72) Inventor James Oliver Burns Fort Corins Alexander Court 7761 (56) Colorado, USA 7761 (56) Reference References JP-A-3-130678 (JP, A) JP-A-63-146613 (JP, A) JP-A-57-174928 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 5/13

Claims (3)

(57) [Claims] 1. A time vernier for precisely controlling an input signal having a coarse timing edge, the desired time delay being added to the input coarse timing edge, the fine delay and the coarse adjustment delay. Receiving means for receiving a value representing the time delay, and a first delay circuit for decoding the fine delay and generating a fine delay control signal.
Decoding means and a second means for decoding the coarse delay and generating a coarse delay control signal
A decoding means, said input signal and said fine delay control signal, said coarse delay <br/> control signal, an input for receiving a control voltage that automatically adjusts to temperature and power supply variation, the control Depending on voltage
Due to temperature and power fluctuation, the rough timing edge
The fine delay is compensated for while compensating the fluctuation of the added time delay.
A delay line for supplying an output signal having a precise timing edges by combining the control signal and the coarse adjustment delay control signal
And the control voltage does not depend on the output signal.
That time vernier system. 2. A method for calibrating a control voltage signal to a time vernier device for precisely controlling an input signal having a coarse timing edge, the step of setting a time reference according to a desired delay.
(1) , a step of setting the control voltage signal to a first level
(2) receiving an input signal having the coarse timing edges by the time vernier system with precise timing edge
Generating an output signal (3) Comparing a delay of the output signal and a device clock period according to the time reference with a phase detector to generate a phase detector output signal
(4) where the counting means has generated in step (4)
Count the total number of occurrences of the phase detector signal of constant logic value
Step of recording Te (5), wherein the step (3), wherein in (4) (5) is repeated a predetermined number of times step (6), and step (5)
When the total number of occurrences over a predetermined number of times is less than a threshold value, the control voltage signal is generated in step (2)
(7) incrementing the level setting in accordance with the predetermined logical value and repeating the steps from step (3) to step (7) . 3. A method for calibrating a time Bagni Ya apparatus for precisely controlling the coarse timing edge that is input, and sets the time base in accordance with the desired delay step
(1) , a step of setting the delay of the first delay element of the time vernier device to a minimum setting value (2) , in order to generate an output signal having a precise timing edge, an input signal having a coarse timing edge the step of the device clock cycle corresponding to step (3) the delay and the time before SL output signal reference input to the vernier device compared with the phase detector for generating a phase detector output signal
(4) where the counting means has generated in step (4)
Count the total number of occurrences of the phase detector signal of constant logic value
Step of recording Te (5), wherein the step (3), (4), (5) a predetermined number of times repeating steps (6), when the total number of occurrences in the previous SL Step (5) is less than the threshold value Sets the delay setting value of the first delay element in the step (2) according to the predetermined logical value.
Increments Te, step (3) repeating the steps from the step (7), and wherein storing the setting of the delay element means for storing data step (1)
Incrementing the time reference according to the predetermined logical value, and repeating the steps from step (3) when the total number of occurrences is less than the threshold value in step ( 5 ). A calibration method comprising: step (8) .