JP3378816B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP3378816B2
JP3378816B2 JP36250498A JP36250498A JP3378816B2 JP 3378816 B2 JP3378816 B2 JP 3378816B2 JP 36250498 A JP36250498 A JP 36250498A JP 36250498 A JP36250498 A JP 36250498A JP 3378816 B2 JP3378816 B2 JP 3378816B2
Authority
JP
Japan
Prior art keywords
semiconductor element
lead
resin
island
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP36250498A
Other languages
Japanese (ja)
Other versions
JP2000183241A (en
Inventor
秀雄 国井
清 高田
浩 井野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP36250498A priority Critical patent/JP3378816B2/en
Publication of JP2000183241A publication Critical patent/JP2000183241A/en
Application granted granted Critical
Publication of JP3378816B2 publication Critical patent/JP3378816B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、複数の半導体素子
がアイランドに平面的に配列された半導体装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of semiconductor elements arranged in a plane in an island.

【0002】[0002]

【従来の技術】近年、モールド型半導体素子が高機能に
成っており、複数の半導体素子を1パッケージ化するも
のが開発されている。
2. Description of the Related Art In recent years, mold type semiconductor elements have become highly functional, and a package of a plurality of semiconductor elements has been developed.

【0003】この技術として例えば、特開平5−121
645号公報の従来例がある。これは、図8に示すよう
に、第1の半導体素子1および第2の半導体素子2が一
つのアイランド3に固着されている。第1および第2の
半導体素子1,2のボンディングパッド4、5とリード
6の先端が金属細線7により実現され、全体が樹脂で封
止されている。そして第1の半導体素子1と第2の半導
体素子2との間の接続は、ボンディングパッド7、8の
間を金属細線9により接続されている。
As this technique, for example, Japanese Patent Laid-Open No. 5-121
There is a conventional example of Japanese Patent No. 645. In this, as shown in FIG. 8, the first semiconductor element 1 and the second semiconductor element 2 are fixed to one island 3. The tips of the bonding pads 4 and 5 and the leads 6 of the first and second semiconductor elements 1 and 2 are realized by thin metal wires 7, and the whole is sealed with resin. The connection between the first semiconductor element 1 and the second semiconductor element 2 is made by connecting the bonding pads 7 and 8 with a thin metal wire 9.

【0004】[0004]

【発明が解決しようとする課題】しかし前記第1の半導
体素子と第2の半導体素子に於いて、前記第2の半導体
素子が、例えば発光ダイオードや半導体レーザ等の発光
素子、ホトダイオードや光IC、磁気センサ、表面弾性
波素子または光書き込み型のメモリ素子等で構成される
場合、実際には同一材料でモールドすることが困難であ
り、個別にモールドしていた。
However, in the first semiconductor element and the second semiconductor element, the second semiconductor element is, for example, a light emitting element such as a light emitting diode or a semiconductor laser, a photodiode or an optical IC, In the case of being composed of a magnetic sensor, a surface acoustic wave device, an optical writing type memory device, or the like, it is actually difficult to mold them with the same material, and they are individually molded.

【0005】またICカード、タグ、光を使った送受信
モジュール等は、複数の半導体素子やチップ抵抗等の受
動素子を使用するが、実際は樹脂の応力、光素子の場合
は光透過性樹脂で覆わなければ成らず、プリント基板上
にはモールドされたディスクリートを実装しているのが
現実であった。
Further, IC cards, tags, transmitting / receiving modules using light use a plurality of semiconductor elements and passive elements such as chip resistors, but in reality, resin stress, and in the case of optical elements, they are covered with a light-transmissive resin. In reality, it was necessary to mount a molded discrete on the printed circuit board.

【0006】従って、安価なモジュールを提供できない
問題があった。
Therefore, there is a problem that an inexpensive module cannot be provided.

【0007】[0007]

【課題を解決するための手段】本発明は、前述の課題に
鑑みてなされ、絶縁性基板を採用するものに於いては、
第2の半導体素子下層に配置されたアイランドと第1の
リードは、前記第2の半導体素子を封止する第2の樹脂
封止部材が硬化前にその間に配置できる間隔を有し、前
記第2の樹脂封止部は、金属細線もカバーする事で解決
するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in the case of using an insulating substrate,
The island and the first lead arranged in the lower layer of the second semiconductor element have a space such that the second resin sealing member for sealing the second semiconductor element can be arranged before curing, and The second resin sealing portion is to solve the problem by also covering the thin metal wire.

【0008】第2の半導体素子と前記第1のリードを接
続する金属細線の一部が第1の樹脂で覆われると、この
二つの樹脂封止部材の熱膨張係数の違いにより断線を発
生させる。しかしアイランドとリードとのクリアランス
が調整されていれば、第2の半導体素子およびこれとリ
ードを接続する金属細線全体も封止できる。
When a part of the thin metal wire connecting the second semiconductor element and the first lead is covered with the first resin, a disconnection occurs due to a difference in thermal expansion coefficient between the two resin sealing members. . However, if the clearance between the island and the lead is adjusted, the second semiconductor element and the entire metal thin wire connecting the lead and the second semiconductor element can be sealed.

【0009】またアイランドに、第2の半導体素子に向
かって凹み部を設け、この凹み部に第1のリードを延在
させる事で解決するものである。
Further, the problem is solved by providing the island with a recess toward the second semiconductor element and extending the first lead in the recess.

【0010】アイランドに凹み部を設け、ここに第1の
リードを挿入すれば、第2の樹脂封止部は、第1のリー
ドと凹み部に相当するアイランド上にのみ載置できる。
従って隣接する他のリードと第1のリードとのクリアラ
ンスを同等にする必要が無く、広げることができるため
他のリードとの耐電圧特性に影響を与えることがない。
If a recess is provided in the island and the first lead is inserted therein, the second resin sealing part can be placed only on the island corresponding to the first lead and the recess.
Therefore, it is not necessary to make the clearance between the other lead and the first lead adjacent to each other equal, and the lead can be widened, so that the withstand voltage characteristic of the other lead is not affected.

【0011】また第2の樹脂封止部を、前記第1の樹脂
封止部から露出させ、その露出面と前記第1の樹脂封止
部を同一面とすることで解決するものである。
Further, the second resin encapsulation part is exposed from the first resin encapsulation part, and the exposed surface and the first resin encapsulation part are made to be the same surface.

【0012】一般の樹脂封止部材は、樹脂の応力緩和を
目的としてフィラーを混入している。しかしこのフィラ
ーは、光素子にとっては不要なものである。ところが、
フィラーの混入率を少なくしたもの、全くなくしたもの
で封止すると、今度は、樹脂応力が発生し、特性の変動
やチップ自身が欠けたりする。しかし本発明は、部分的
にポッティングし、このポッティング樹脂を金型に当接
させてフィラー入りの封止部材でモールドするので、光
素子は、効率の良い受発光が可能に、また他の素子は、
前記フィラー入りの樹脂封止部材で素子の特性変化、欠
けを防止することができる。しかも後述する金型で形成
すれば、第1の樹脂封止部、第2の樹脂封止部ともに同
一面で構成できるので、光素子を第2の半導体素子とし
て採用した場合、光の入射・射出が精度高くできる。ま
た磁気センサを採用した場合、被検出体との離間距離も
精度よく維持できるので、検出精度を維持できるメリッ
トを有する。
In a general resin sealing member, a filler is mixed for the purpose of stress relaxation of the resin. However, this filler is unnecessary for the optical element. However,
If sealing is performed with a filler with a low mixing rate or without a filler, resin stress will be generated this time, resulting in fluctuations in characteristics and chipping. However, according to the present invention, the potting resin is partially potted, and the potting resin is brought into contact with the mold and is molded with the sealing member containing the filler. Therefore, the optical element can efficiently receive and emit light, and other elements Is
With the resin-sealing member containing the filler, it is possible to prevent characteristic changes and chipping of the element. In addition, since the first resin encapsulation portion and the second resin encapsulation portion can be formed on the same surface if they are formed by a mold described later, when the optical element is adopted as the second semiconductor element, High precision injection. Further, when the magnetic sensor is adopted, the distance from the object to be detected can also be maintained with high accuracy, which has the advantage of maintaining the detection accuracy.

【0013】またリードフレームのみを採用した場合に
於いて、第2の半導体素子下層に配置されたアイランド
と第1のリードには、前記第2の半導体素子を封止する
第2の樹脂封止部の材料が硬化前にその間に配置できる
間隔を設け、第2の樹脂封止部は、金属細線もカバーさ
せる事で解決するものである。
In the case where only the lead frame is adopted, the island and the first lead arranged in the lower layer of the second semiconductor element are sealed with the second resin for sealing the second semiconductor element. The problem is solved by providing a space that allows the material of the parts to be arranged between them before curing, and by covering the thin metal wire in the second resin sealing part.

【0014】第2の半導体素子と前記第1のリードを接
続する金属細線の一部が第1の樹脂で覆われると、この
二つの樹脂封止部材の熱膨張係数の違いにより断線を発
生させる。しかしアイランドとリードとのクリアランス
が調整されていれば、第2の半導体素子およびこれとリ
ードを接続する金属細線全体も封止できる。
When a part of the thin metal wire connecting the second semiconductor element and the first lead is covered with the first resin, a disconnection occurs due to a difference in thermal expansion coefficient between the two resin sealing members. . However, if the clearance between the island and the lead is adjusted, the second semiconductor element and the entire metal thin wire connecting the lead and the second semiconductor element can be sealed.

【0015】またリード間にチップ状の受動素子を固着
することで解決するものである。
Another solution is to fix a chip-shaped passive element between the leads.

【0016】絶縁性基板を用いない代わりにリード間に
受動素子を取り付けることで簡単な回路も含めて一体で
構成できる。
Instead of using an insulating substrate, a passive element is attached between the leads so that a simple circuit can be integrally formed.

【0017】またアイランドは、前記第2の半導体素子
に向かって凹み部を有し、この凹み部に前記第1のリー
ドを延在させる事で解決するものである。
Further, the island has a recessed portion toward the second semiconductor element, and is solved by extending the first lead in the recessed portion.

【0018】アイランドに凹み部を設け、ここに第1の
リードを挿入すれば、第2の樹脂封止部は、第1のリー
ドと凹み部に相当するアイランド上にのみ載置できる。
従って隣接する他のリードと第1のリードとのクリアラ
ンスを同等にする必要が無く、広げることができるため
他のリードとの耐電圧特性に影響を与えることがない。
If the island is provided with a recess and the first lead is inserted therein, the second resin sealing part can be placed only on the island corresponding to the first lead and the recess.
Therefore, it is not necessary to make the clearance between the other lead and the first lead adjacent to each other equal, and the lead can be widened, so that the withstand voltage characteristic of the other lead is not affected.

【0019】更には前もって第1のリードとアイランド
とのクリアランスが所定の間隔に成って用意されていれ
ば、第2の樹脂封止部材が滴下せず、第2の樹脂封止部
の高さ、露出面積を一定に保てる。また金型内にこの第
2の樹脂封止部材が落下する事もない。従って完成品の
表面に落下した樹脂封止部が固まりとなって形成される
こともない。
Furthermore, if the clearance between the first lead and the island is prepared in advance with a predetermined interval, the second resin sealing member does not drip and the height of the second resin sealing portion is high. , The exposed area can be kept constant. In addition, the second resin sealing member does not fall into the mold. Therefore, the resin sealing portion that has fallen onto the surface of the finished product will not be formed as a lump.

【0020】[0020]

【発明の実施の形態】以下に本発明の第1の実施の形態
を図1を参照しながら詳細に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described in detail below with reference to FIG.

【0021】まず絶縁性基板10があり、この上には接
着剤等によりCu箔パターンが形成されている。このパ
ターンは、半導体素子が実装されるランド11、回路を
構成するための配線、この配線の端部に形成されるボン
ディング用パッド12、チップコンデンサ等をロウ材で
固着するための電極13等で成る。
First, there is an insulating substrate 10, on which a Cu foil pattern is formed with an adhesive or the like. This pattern is composed of a land 11 on which a semiconductor element is mounted, a wiring for forming a circuit, a bonding pad 12 formed at an end of this wiring, an electrode 13 for fixing a chip capacitor or the like with a brazing material, and the like. Become.

【0022】また前述した絶縁性基板10は、ここでは
プリント基板を採用したが、フレキシブルシート、ガラ
ス基板、セラミック基板等でも良い。
Although a printed circuit board is used as the insulating substrate 10 described above, a flexible sheet, a glass substrate, a ceramic substrate or the like may be used.

【0023】このパターンには、第1の半導体素子1
4、第2の半導体素子15、チップコンデンサ、チップ
抵抗等の受動素子RCが固着され、ロウ材や金属細線W
で電気的に接続されている。
In this pattern, the first semiconductor element 1
4, the second semiconductor element 15, the passive element RC such as the chip capacitor and the chip resistor is fixed, and the brazing material or the thin metal wire W
It is electrically connected with.

【0024】またCuを主材料とするリードフレームが
用意され、このリードフレームの構成要素であるアイラ
ンド16に前記絶縁性基板10が固着される。そして、
第1のリード18と第2の半導体素子15が金属細線1
9を介して接続されている。
A lead frame mainly made of Cu is prepared, and the insulating substrate 10 is fixed to the island 16 which is a constituent element of the lead frame. And
The first lead 18 and the second semiconductor element 15 are the thin metal wires 1
It is connected through 9.

【0025】また第2のリード20と例えばパッド12
が金属細線21で接続されている。
The second lead 20 and the pad 12, for example,
Are connected by a thin metal wire 21.

【0026】更には、第2の半導体素子15は、透明な
エポキシ樹脂、シリコーン樹脂等の第2の樹脂封止部材
22でポッティングされ、全体が第1の樹脂封止部材2
3で封止されている。
Further, the second semiconductor element 15 is potted with a second resin sealing member 22 such as a transparent epoxy resin or silicone resin, so that the entire first resin sealing member 2 is formed.
It is sealed with 3.

【0027】本発明の特徴は、第1の樹脂封止部23で
実質全体を封止すると共に、第2の半導体素子15を第
2の樹脂封止部22で封止したことにある。
A feature of the present invention is that the first resin encapsulation portion 23 substantially encapsulates the entire structure and the second semiconductor element 15 is encapsulated by the second resin encapsulation portion 22.

【0028】前記第1の半導体素子15が光素子である
場合は、第2の樹脂封止部は、透明なエポキシ樹脂等で
なり、後述する金型で封止されるため第1の樹脂封止部
23と一緒につらいちに形成されている。第2の樹脂封
止部材のフィラー混入率は、第1の樹脂封止部材よりも
少ないか、全く入っていないため、樹脂に発生する応力
が大きくなるが、実質第1の半導体素子のみ封止してい
るので、他の素子への影響は抑制される。
When the first semiconductor element 15 is an optical element, the second resin sealing portion is made of a transparent epoxy resin or the like, and is sealed with a mold described later, so that the first resin sealing portion is used. It is formed together with the stop 23. Since the filler mixing ratio of the second resin sealing member is smaller than that of the first resin sealing member or does not exist at all, the stress generated in the resin is large, but substantially only the first semiconductor element is sealed. Therefore, the influence on other elements is suppressed.

【0029】また第1の半導体素子が磁気センサ等の場
合、応力が少ないシリコーン樹脂で覆われ、やはりつら
いちで形成される。
When the first semiconductor element is a magnetic sensor or the like, the first semiconductor element is covered with a silicone resin having a low stress, and is also formed with a flat surface.

【0030】従って製品としての表面形状、光素子や磁
気センサに必要なその表面のフラット性が維持でき、光
素子では、光の発光受光が良好にでき、磁気センサで
は、その検出媒体との間隔を一定に保つことができる。
Therefore, the surface shape as a product and the flatness of the surface required for the optical element and the magnetic sensor can be maintained, the optical element can satisfactorily emit and receive light, and the magnetic sensor can be spaced from the detection medium. Can be kept constant.

【0031】また第2の樹脂封止部は、第2半導体素子
のみ覆うのではなく、第1の金属細線19も完全に覆う
必要がある。例えば第2の半導体素子15側の金属細線
19は、第2の樹脂封止部で、第1のリード18側の金
属細線19が第1の樹脂封止部23で覆われると、熱膨
張係数の違いにより断線が発生する。
Further, the second resin encapsulation portion needs to completely cover not only the second semiconductor element but also the first thin metal wire 19. For example, the metal thin wire 19 on the second semiconductor element 15 side is a second resin sealing portion, and when the metal thin wire 19 on the first lead 18 side is covered with the first resin sealing portion 23, the coefficient of thermal expansion is increased. Disconnection occurs due to the difference in

【0032】従って第2の樹脂封止部22は、第1のリ
ード18の接続部も含めて金属細線19全体を覆わなけ
ればならない。図1に於いて、第2の半導体素子15の
右側にある金属細線19は、絶縁性基板10上であるの
でカバーすることは簡単であるが、左側の金属細線は、
アイランドとリードとの間に隙間を有するため問題とな
る。
Therefore, the second resin sealing portion 22 must cover the entire thin metal wire 19 including the connecting portion of the first lead 18. In FIG. 1, the thin metal wire 19 on the right side of the second semiconductor element 15 is on the insulating substrate 10 and is therefore easy to cover, but the thin metal wire on the left side is
There is a gap between the island and the lead, which causes a problem.

【0033】本発明は、この隙間を前もって計算し、第
2の樹脂封止部材が落下しないように設定されているこ
とにある。第2の樹脂封止部材は、後述する製造方法か
らも明らかなように、ある粘度を持ち、ディスペンサ等
でポッテングされる。従って硬化前までは、できるだけ
流動しなく、またリードの下方に垂れたり落下すること
もしない様にしなければならない。
According to the present invention, the gap is calculated in advance and the second resin sealing member is set so as not to drop. The second resin sealing member has a certain viscosity and is potted with a dispenser or the like, as is clear from the manufacturing method described later. Therefore, before curing, it should be as fluid as possible and should not drip or fall below the lead.

【0034】本発明は、少なくとも第1のリード18と
アイランド16との隙間が狭く形成され、樹脂はその粘
性と表面張力によりこの隙間から流れ出ないので、完全
に金属細線19をカバーする事ができる。
In the present invention, at least the gap between the first lead 18 and the island 16 is formed narrow, and the resin does not flow out of this gap due to its viscosity and surface tension, so that the fine metal wire 19 can be completely covered. .

【0035】尚符号24は、アイランドのつりリードで
あり、25は、リード18の隣に配置されたリードであ
る。第2の樹脂封止部の塗布量によっては、これらのク
リアランスも狭くする必要がある。
Reference numeral 24 is a fishing lead of the island, and 25 is a lead arranged next to the lead 18. These clearances also need to be narrowed depending on the application amount of the second resin sealing portion.

【0036】例えばアイランドの厚みが0.125mm
であると、プレスで打ち抜けるクリアランスは、0.1
mm程度である。従って好ましくは、隙間0.2〜0.
1mm程度でも滴下のない粘度に樹脂封止部材を調整す
る必要がある。
For example, the thickness of the island is 0.125 mm
Then, the clearance that can be punched by the press is 0.1
It is about mm. Therefore, preferably, the gap is 0.2 to 0.
It is necessary to adjust the resin sealing member to a viscosity that does not drop even about 1 mm.

【0037】続いて第2の実施の形態について図2を参
照して説明する。
Next, a second embodiment will be described with reference to FIG.

【0038】一番上の図は、図1に凹み部HBを設けた
ものである。真ん中の図面は、第1のリードに沿った断
面図であり、下の図面は、リード25に沿った断面図で
ある。
The uppermost drawing is the one in which the recessed portion HB is provided in FIG. The middle drawing is a cross-sectional view along the first lead, and the lower drawing is a cross-sectional view along the lead 25.

【0039】また構造は前記凹み部HBのみ異なるた
め、ここの説明だけにとどめる。つまり第1のリード1
8、ここでは金属細線19が接続されている第1のリー
ド18の部分がアイランドの中に入り込むように、アイ
ランド16、絶縁性基板10に凹み部HBを設ける。そ
して、この部分とアイランド16との隙間は、第2の樹
脂封止部材が硬化前に落下しないような間隔に設定され
る事に特徴を有する。
Since the structure is different only in the recess HB, only the description will be given here. That is, the first lead 1
8. Here, the recessed portion HB is provided in the island 16 and the insulating substrate 10 so that the portion of the first lead 18 to which the thin metal wire 19 is connected enters into the island. The gap between this portion and the island 16 is characterized in that the gap is set such that the second resin sealing member does not drop before curing.

【0040】つまり図1では、第1のリードや他の隣接
しているリードにもそのクリアランスが必要であるが、
本実施の形態では、第1のリード18とアイランド16
のみのクリアランスを狭めるだけですむ。つまり他のリ
ードは、回路の都合からくる電圧の高いものと接続が可
能となる。
That is, in FIG. 1, the clearance is also required for the first lead and other adjacent leads.
In the present embodiment, the first lead 18 and the island 16
Only need to narrow the clearance. In other words, other leads can be connected to ones having a high voltage due to the convenience of the circuit.

【0041】また樹脂で成るダム30を黒い太丸の様に
囲むと、第2の樹脂封止部材をポッテングした際、流れ
が抑制され、金型との完全な当接が可能となり、また当
接して第1の樹脂封止部から露出する露出面積もそのバ
ラツキを抑制することができる。
Further, if the dam 30 made of resin is surrounded by a thick black circle, when the second resin sealing member is potted, the flow is restrained, and it becomes possible to make complete contact with the mold, and It is possible to suppress the variation in the exposed area which comes into contact and is exposed from the first resin sealing portion.

【0042】続いて第3の実施の形態を図3を用いて説
明する。本実施の形態は、図3の構造において、前記絶
縁性基板10を省略したものである。本発明は、絶縁性
基板10上のCuパターンの代わりにリードを活用して
受動素子RCを接続したものである。
Next, a third embodiment will be described with reference to FIG. In this embodiment, the insulating substrate 10 is omitted in the structure of FIG. In the present invention, the passive element RC is connected by utilizing the lead instead of the Cu pattern on the insulating substrate 10.

【0043】前記絶縁性基板10は、厚みが有るため、
パッケージ後の半導体装置としてはその厚みが大きくな
るが、リードに受動素子RCが接続されているので、そ
の厚みを小さくできる特徴を有する。
Since the insulating substrate 10 has a thickness,
Although the thickness of the packaged semiconductor device is large, the passive element RC is connected to the leads, so that the thickness can be reduced.

【0044】では簡単に説明する。アイランド16に
は、第1の半導体素子14と第2の半導体素子15が実
装されている。この第2の半導体素子15の周りには、
ライン状の樹脂(ダム)30で樹脂のストッパーが形成
され、ここに第2の樹脂封止部材22が塗布されてい
る。またリード間には受動素子RCであるチップコンデ
ンサ、チップ抵抗等がロウ材で電気的に接続固着されて
いる。そして例えば封止部材の中で所定の回路機能を構
成している。また封止部材から導出するリードに外付け
部品を取り付けることで、所定の回路機能を実現しても
良い。
A brief description will be given below. The first semiconductor element 14 and the second semiconductor element 15 are mounted on the island 16. Around this second semiconductor element 15,
A line-shaped resin (dam) 30 forms a resin stopper, and the second resin sealing member 22 is applied thereto. A chip capacitor, a chip resistor, etc., which is a passive element RC, is electrically connected and fixed between the leads with a brazing material. Then, for example, a predetermined circuit function is configured in the sealing member. Further, a predetermined circuit function may be realized by attaching an external component to the lead led out from the sealing member.

【0045】更に第1および第2の実施の形態と同様
に、第1の樹脂封止部23、第2の樹脂封止部22が形
成される。
Further, similar to the first and second embodiments, the first resin sealing portion 23 and the second resin sealing portion 22 are formed.

【0046】全実施例において、例えば光ICモジュー
ル、IrDA等の応用すれば、これらは受動素子が少な
いため、これらも一緒に一体ができ、コストを低下でき
ると共に、これを用いたセットも組立等の作業を簡略に
できる。
In all of the embodiments, if an optical IC module, IrDA, etc. are applied, since these have few passive elements, they can be integrated together, the cost can be reduced, and a set using this can be assembled. Can be simplified.

【0047】またタグ等に採用した場合、コイルだけを
外部に導出したリードに外付けするだけで製品化が可能
となる。
When it is adopted as a tag or the like, it can be commercialized only by externally attaching only the coil to the lead led out to the outside.

【0048】また図3は、図2の構造と同様に凹み部H
Bが設けられており、前述同様に第1のリード18とア
イランド16の隙間のみ考慮するだけで第2の樹脂封止
部材を落下させることなくポッティングすることができ
る。
Further, FIG. 3 shows the recess H as in the structure of FIG.
B is provided, and potting can be performed without dropping the second resin sealing member by only considering the gap between the first lead 18 and the island 16 as described above.

【0049】ここでリード間には、他に2端子構造の半
導体素子(例えばダイオード)等も接続可能である。
In addition, a semiconductor element (for example, a diode) having a two-terminal structure can be connected between the leads.

【0050】続いて第4の実施の形態について図4、図
5を参照して説明する。
Next, a fourth embodiment will be described with reference to FIGS.

【0051】これは図3の構造において、アイランド1
6の表裏にそれぞれ半導体素子14、15を実装したも
のである。例えば少なくとも一方が輻射ノイズを嫌った
り、またIC基板を同一電位にすることを嫌ったりする
場合に有効である。
This corresponds to the island 1 in the structure of FIG.
The semiconductor elements 14 and 15 are mounted on the front and back sides of 6, respectively. For example, it is effective when at least one dislikes radiation noise or dislikes making the IC substrate have the same potential.

【0052】後者の場合、どちらか一方の半導体素子
は、絶縁シート、絶縁接着剤等で絶縁処理される。
In the latter case, either one of the semiconductor elements is insulated with an insulating sheet, an insulating adhesive or the like.

【0053】ここでタブ30は、一方のアイランド面と
第1のリード18間に設けられ、この中に第2の樹脂封
止部が設けられる。この場合、両面実装であるため、図
3に比べさらにそのサイズは小さくなる。
Here, the tab 30 is provided between one island surface and the first lead 18, and the second resin sealing portion is provided therein. In this case, since it is double-sided mounting, its size is smaller than that in FIG.

【0054】続いて、第2の樹脂封止部22と第1の樹
脂封止部23とのつらいちの仕方について簡単に説明す
る。ここでは図1の第1の実施の形態を使って説明す
る。また第2および第3の実施の形態については、実質
同じ方法で形成されるので、省略する。
Next, a brief description will be given of how the second resin encapsulation portion 22 and the first resin encapsulation portion 23 are attached. Here, description will be given using the first embodiment of FIG. Also, the second and third embodiments are omitted because they are formed by substantially the same method.

【0055】まず図6のように、半導体素子14、1
5、受動素子RCが実装された絶縁性基板10を用意
し、金属細線を接続した後、前記絶縁性基板をリードフ
レームのアイランド16に固着し、第2の樹脂封止部材
をポッティングする。この樹脂は、周りに流れ出なく、
金型K1またはK2に当接できるある高さを維持できる
粘性を有している。
First, as shown in FIG. 6, semiconductor elements 14 and 1
5. Prepare the insulating substrate 10 on which the passive element RC is mounted, connect the thin metal wires, fix the insulating substrate to the island 16 of the lead frame, and pot the second resin sealing member. This resin does not flow out,
It has a viscosity that can maintain a certain height at which it can contact the mold K1 or K2.

【0056】続いて、前記リードフレームを金型K1、
K2に組み込み、第1の樹脂封止部材を流し込む。当然
図4、図5の構造では、第2の樹脂封止部が設けられる
側が上になって金型に配置される。また前記第2の樹脂
封止部材22は、金型に組み込んでからポッティングし
ても良い。
Subsequently, the lead frame is attached to the mold K1,
It is assembled in K2 and the first resin sealing member is poured. As a matter of course, in the structures shown in FIGS. 4 and 5, the side on which the second resin sealing portion is provided faces upward and is arranged in the mold. Further, the second resin sealing member 22 may be potted after being incorporated in a mold.

【0057】ここでは第2の樹脂封止部材が上金型K1
に当接するため、第1の樹脂封止部23と同一面を構成
できる。
Here, the second resin sealing member is the upper mold K1.
Since it abuts against, it is possible to form the same surface as the first resin sealing portion 23.

【0058】ここで前記第2の樹脂封止部材は、第1の
樹脂封止部材23を注入する前に、前記金型の熱で硬化
した方が良い。これは注入圧力で第2の樹脂封止部材が
変形する恐れがあるからである。また図1、図2のよう
に絶縁性基板を採用する比較的サイズの大きいもの、ま
たは絶縁基板を採用しなくてもアイランドが大きい場合
(図3の構造を金型に配置した場合)、金型に当接した
後、アイランド16裏面を支持する手段を設ける必要が
ある。これはアイランドの上下変動により、注入時の樹
脂圧力で樹脂漏れが発生したり、アイランド上の半導体
素子が欠けたりする問題があるからである。
Here, it is preferable that the second resin sealing member is cured by the heat of the mold before injecting the first resin sealing member 23. This is because the second resin sealing member may be deformed by the injection pressure. In addition, as shown in FIGS. 1 and 2, if the insulating substrate is used and the size is relatively large, or if the insulating substrate is not used and the island is large (when the structure of FIG. 3 is arranged in the mold), the It is necessary to provide a means for supporting the back surface of the island 16 after contacting the mold. This is because the up and down movement of the island may cause resin leakage due to the resin pressure at the time of injection or the semiconductor element on the island may be chipped.

【0059】また図3のようにダム30を用い、粘度と
突出量を制御すれば、前記第1の樹脂封止部から露出す
る第2の樹脂封止部の領域を制御できる。
If the viscosity and the amount of protrusion are controlled by using the dam 30 as shown in FIG. 3, the area of the second resin sealing portion exposed from the first resin sealing portion can be controlled.

【0060】つまり光素子では、第2の樹脂封止部22
で一定面積の透過性の窓を実現できるメリットも有す
る。
That is, in the optical element, the second resin sealing portion 22
It also has the advantage that a transparent window with a certain area can be realized.

【0061】[0061]

【発明の効果】以上に説明した通り、本発明によれば、
通常の半導体素子と特殊な半導体素子(例えば光素子、
磁気センサ等)を一体モールドできる。特に金型でモー
ルドする際、第2の樹脂封止部材を金型に当接させた後
に第1の樹脂封止部材を注入するので、第2の樹脂封止
部の露出面を第1の樹脂封止部とつらいちにできる。
As described above, according to the present invention,
Ordinary semiconductor devices and special semiconductor devices (eg optical devices,
Magnetic sensor etc.) can be integrally molded. In particular, when molding with a mold, the first resin sealing member is injected after the second resin sealing member is brought into contact with the mold, so that the exposed surface of the second resin sealing portion is formed into the first resin. It can be made as simple as a resin sealing part.

【0062】また第1のリードとアイランドのクリアラ
ンスを設定することで、硬化前の第2の樹脂封止部材が
隙間から流れ出ることを防止することができる。
By setting the clearance between the first lead and the island, it is possible to prevent the second resin sealing member before curing from flowing out from the gap.

【0063】更には、絶縁性基板を用いたフルモール
ド、受動素子をリードに固着したフルモールドが可能で
あるため、光モジュール、タグ、ICカード等の構成部
品として好適である。
Furthermore, since full molding using an insulating substrate and full molding in which passive elements are fixed to the leads are possible, it is suitable as a component of an optical module, tag, IC card, or the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態を説明する半導体装
置の平面図である。
FIG. 1 is a plan view of a semiconductor device illustrating a first embodiment of the present invention.

【図2】本発明の第2の実施の形態を説明する半導体装
置の図である。
FIG. 2 is a diagram of a semiconductor device illustrating a second embodiment of the present invention.

【図3】本発明の第3の実施の形態を説明する半導体装
置の平面図である。
FIG. 3 is a plan view of a semiconductor device illustrating a third embodiment of the present invention.

【図4】本発明の第4の実施の形態を説明する半導体装
置の平面図である。
FIG. 4 is a plan view of a semiconductor device illustrating a fourth embodiment of the present invention.

【図5】図4の裏面を説明する図である。FIG. 5 is a diagram illustrating the back surface of FIG.

【図6】本半導体装置の製造方法を説明する図である。FIG. 6 is a diagram illustrating the manufacturing method of the present semiconductor device.

【図7】本半導体装置の製造方法を説明する図である。FIG. 7 is a diagram illustrating the manufacturing method of the present semiconductor device.

【図8】従来例の半導体装置を説明するための平面図で
ある。
FIG. 8 is a plan view for explaining a conventional semiconductor device.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 実開 平4−107844(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 23/29 H01L 23/31 H01L 25/04 H01L 25/18 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Bibliography 4-107844 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/29 H01L 23/31 H01L 25 / 04 H01L 25/18

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 アイランドと、前記アイランドの少なく
とも一側辺の近傍から外に向かい配置された複数のリー
ドと、前記アイランドに固着された絶縁性基板と、前記
絶縁性基板に貼着された導電性パターンと、前記絶縁性
基板に固着され、前記導電パターンと電気的に接続され
た複数のベアチップ状の半導体素子と、前記絶縁性基板
に固着され、前記導電パターンと電気的に接続されたチ
ップ状の受動素子と、前記リード、前記導電パターン、
前記複数の半導体素子または前記受動素子を電気的に接
続する金属細線と、前記リード、前記複数の半導体素
子、前記受動素子および金属細線を封止する樹脂封止部
とを有する半導体装置に於いて、 前記半導体素子の中の第1の半導体素子は、実質全域を
封止する第1の樹脂封止部でカバーされ、前記半導体素子の中の第2の半導体素子は、前記第2の
半導体素子に向かって凹み部を有する前記アイランドに
固着され、この凹み部に延在され且つその近傍に配置さ
れた第1のリードと金属細線を介して接続され、 前記第2の半導体素子下層に配置された前記アイランド
と前記第1のリードは、前記第2の半導体素子を封止す
る第2の樹脂封止部の材料が硬化前にその間に配置でき
る間隔を有し、前記第2の樹脂封止部は、前記金属細線
もカバーする事を特徴とした半導体装置。
1. An island, a plurality of leads arranged outward from the vicinity of at least one side of the island, an insulating substrate fixed to the island, and a conductive material attached to the insulating substrate. Pattern, a plurality of bare chip-shaped semiconductor elements fixed to the insulating substrate and electrically connected to the conductive pattern, and a chip fixed to the insulating substrate and electrically connected to the conductive pattern -Shaped passive element, the lead, the conductive pattern,
In a semiconductor device having a thin metal wire for electrically connecting the plurality of semiconductor elements or the passive element, and a resin sealing portion for sealing the lead, the plurality of semiconductor elements, the passive element and the thin metal wire. The first semiconductor element in the semiconductor element is covered with a first resin sealing portion that seals substantially the entire area, and the second semiconductor element in the semiconductor element is the second semiconductor element.
In the island having a recess toward the semiconductor element
It is fixed and extended in this recess and placed near it.
The first lead connected to the first semiconductor lead via a thin metal wire, and the island and the first lead arranged in the lower layer of the second semiconductor element are the second resin for sealing the second semiconductor element. A semiconductor device, wherein the material of the encapsulating portion has a space that can be arranged before curing, and the second resin encapsulating portion also covers the thin metal wire.
【請求項2】 前記第2の樹脂封止部は、前記第1の樹2. The second resin sealing portion is the first resin.
脂封止部から露出し、その露出面と前記第1の樹脂封止Exposed from the oil sealing portion, the exposed surface and the first resin sealing
部は同一面を構成する請求項1に記載の半導体装置。The semiconductor device according to claim 1, wherein the parts form the same plane.
【請求項3】 アイランドと、前記アイランドの少なく
とも一側辺近傍から外に向かい配置された複数のリード
と、前記アイランドに固着された複数のベアチップ状の
半導体素子および前記リードを封止する樹脂封止部とを
有する半導体装置に於いて、 前記半導体素子および前記リードは、実質全域を封止す
る第1の樹脂封止部で封止され、前記半導体素子の中の第2の半導体素子は、前記第2の
半導体素子に向かって 凹み部を有する前記アイランドに
固着され、この凹み部に延在され且つその近傍に配置さ
れた第1のリードと金属細線を介して接続され、 前記第2の半導体素子下層に配置された前記アイランド
と前記第1のリードは、前記第2の半導体素子を封止す
る第2の封止樹脂部の材料が硬化前にその間に配置でき
る間隔を有し、前記第2の樹脂封止部は、前記金属細線
もカバーする事を特徴とした半導体装置。
3. An island, a plurality of leads arranged outward from the vicinity of at least one side of the island, a plurality of bare chip-shaped semiconductor elements fixed to the island, and a resin seal for sealing the leads. In a semiconductor device having a stopper, the semiconductor element and the lead are sealed with a first resin sealing section that seals substantially the entire area, and a second semiconductor element in the semiconductor element is The second
In the island having a recess toward the semiconductor element
It is fixed and extended in this recess and placed near it.
The first lead connected to the first semiconductor chip and the first lead, which are connected to each other through a thin metal wire, are disposed in the lower layer of the second semiconductor element, and the first lead seals the second semiconductor element. A semiconductor device characterized in that the material of the resin-stopping portion has an interval that can be arranged therebetween before curing, and the second resin sealing portion also covers the thin metal wire.
【請求項4】 前記第2の樹脂封止部は、前記第1の樹
脂封止部から露出し、その露出面と前記第1の樹脂封止
部は同一面を構成する請求項3に記載の半導体装置。
4. The second resin sealing portion is exposed from the first resin sealing portion, and the exposed surface and the first resin sealing portion form the same surface. Semiconductor device.
JP36250498A 1998-12-21 1998-12-21 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3378816B2 (en)

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