JP2000164803A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JP2000164803A
JP2000164803A JP10337852A JP33785298A JP2000164803A JP 2000164803 A JP2000164803 A JP 2000164803A JP 10337852 A JP10337852 A JP 10337852A JP 33785298 A JP33785298 A JP 33785298A JP 2000164803 A JP2000164803 A JP 2000164803A
Authority
JP
Japan
Prior art keywords
resin
resin sealing
semiconductor
sealing portion
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10337852A
Other languages
Japanese (ja)
Inventor
Hideo Kunii
秀雄 国井
Kiyoshi Takada
清 高田
Hiroshi Inoguchi
浩 井野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10337852A priority Critical patent/JP2000164803A/en
Publication of JP2000164803A publication Critical patent/JP2000164803A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent generation of stresses from resin sealing material in a package, which is formed in a state in which an element disliking stress and scattering of incident light is electrically connected with an ordinary semiconductor element. SOLUTION: On an island 16, an insulating substrate 10 is formed, on which a first semiconductor element 14 and a second semiconductor element 15 are fixed. A second resin sealing material 22 is spread on the second semiconductor element 15. In this state, the substrate is set in metallic molds K1, K2. A second resin sealing material is made to abut against the metal mold K1, and a first resin sealing material 23 is injected. As a result, two resin sealing parts are formed in the same plane.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、複数の半導体素子
がアイランドに平面的に配列された半導体装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor elements are arranged in an island in a plane.

【0002】[0002]

【従来の技術】近年、モールド型半導体素子が高機能に
成っており、複数の半導体素子を1パッケージ化するも
のが開発されている。
2. Description of the Related Art In recent years, a mold type semiconductor device has become highly functional, and a device in which a plurality of semiconductor devices are integrated into one package has been developed.

【0003】この技術として例えば、特開平5−121
645号公報の従来例がある。これは、図6に示すよう
に、第1の半導体素子1および第2の半導体素子2が一
つのアイランド3に固着されている。第1および第2の
半導体素子1,2のボンディングパッド4、5とリード
6の先端が金属細線7により実現され、全体が樹脂で封
止されている。そして第1の半導体素子1と第2の半導
体素子との間の接続は、ボンディングパッド7、8の間
を金属細線9により接続されている。
As this technique, for example, Japanese Patent Laid-Open No. 5-121 is disclosed.
There is a conventional example of JP-A-645-645. The first semiconductor element 1 and the second semiconductor element 2 are fixed to one island 3 as shown in FIG. The tips of the bonding pads 4 and 5 and the leads 6 of the first and second semiconductor elements 1 and 2 are realized by fine metal wires 7, and the whole is sealed with resin. In the connection between the first semiconductor element 1 and the second semiconductor element, the bonding pads 7 and 8 are connected by a thin metal wire 9.

【0004】[0004]

【発明が解決しようとする課題】しかし前記第1の半導
体素子と第2の半導体素子に於いて、前記第2の半導体
素子が、例えば発光ダイオードや半導体レーザ等の発光
素子、ホトダイオードや光IC、磁気センサ、表面弾性
波素子または光書き込み型のメモリ素子等で構成される
場合、実際には一緒にモールドすることが困難であり、
個別にモールドしていた。
However, in the first semiconductor element and the second semiconductor element, the second semiconductor element is a light emitting element such as a light emitting diode or a semiconductor laser, a photodiode or an optical IC, or the like. In the case of a magnetic sensor, a surface acoustic wave device or an optical writing type memory device, it is actually difficult to mold them together,
Molded individually.

【0005】またICカード、タグ、光を使った送受信
モジュール等は、複数の半導体素子やチップ抵抗等の受
動素子を使用するが、実際は樹脂の応力、光素子の場合
は光透過性樹脂で覆わなければ成らず、プリント基板上
にはモールドされたディスクリートを実装しているのが
現実であった。
[0005] IC cards, tags, transmitting / receiving modules using light, etc., use a plurality of semiconductor elements and passive elements such as chip resistors. However, in reality, the stress of resin is used. The reality was that molded discretes were mounted on the printed circuit board.

【0006】従って、安価なモジュールを提供できない
問題があった。
Therefore, there is a problem that an inexpensive module cannot be provided.

【0007】[0007]

【課題を解決するための手段】本発明は、前述の課題に
鑑みてなされ、絶縁性基板を採用するもの、リードフレ
ームを採用するものに於いて、複数の半導体素子の中の
第1の半導体素子を、実質全域を封止する第1の樹脂封
止部でカバーし、第2の半導体素子を、前記第1の樹脂
封止部と材質の異なる第2の樹脂封止部でカバーし、第
2の樹脂封止部を、第1の樹脂封止部から露出し、その
表面を第1の樹脂封止部と同一面で成すことで解決する
ものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-mentioned problems. The device is covered with a first resin sealing portion that seals substantially the entire area, and the second semiconductor element is covered with a second resin sealing portion having a different material from the first resin sealing portion. This problem is solved by exposing the second resin sealing portion from the first resin sealing portion and forming the surface of the second resin sealing portion on the same plane as the first resin sealing portion.

【0008】例えば一般の樹脂封止部材は、樹脂の応力
緩和を目的としてフィラーを混入している。しかしこの
フィラーは、光素子にとっては不要なものである。とこ
ろが、フィラーの混入率を少なくしたもの、全くなくし
たもので封止すると、今度は、樹脂応力が発生し、特性
の変動やチップ自身が欠けたりする。しかし本発明は、
部分的にポッティングし、このポッティング樹脂を金型
に当接させてフィラー入りの封止部材でモールドするの
で、光素子は、効率の良い受発光が可能に、また他の素
子は、前記フィラー入りの樹脂封止部材で素子の特性変
化、欠けを防止することができる。
For example, a general resin sealing member is mixed with a filler for the purpose of relaxing the stress of the resin. However, this filler is unnecessary for an optical element. However, when sealing is performed with a filler having a reduced or no filler mixing rate, resin stress is generated, which causes a change in characteristics and a chip itself. However, the present invention
Partial potting is performed, and this potting resin is brought into contact with a mold and molded with a sealing member containing a filler, so that an optical element can efficiently receive and emit light, and the other elements include the filler containing the filler. With the resin sealing member described above, it is possible to prevent the characteristic change and chipping of the element.

【0009】また第2の半導体素子を、アイランドの裏
面に固着する事で解決するものである。
Another object is to solve the problem by fixing the second semiconductor element to the back surface of the island.

【0010】裏面に実装することで、第1の樹脂封止部
材と第2の樹脂封止部材との熱膨張係数の違いから発生
する応力が、直接アイランド表面に加わることがない。
[0010] By mounting on the back surface, stress generated due to a difference in thermal expansion coefficient between the first resin sealing member and the second resin sealing member is not directly applied to the island surface.

【0011】また第2の樹脂封止部は、シリコーン樹脂
または透明樹脂から成ることで解決するものであり、前
者は応力に弱い磁気センサ、後者は光素子に好適であ
る。
The second resin sealing portion can be solved by using a silicone resin or a transparent resin. The former is suitable for a magnetic sensor which is weak against stress, and the latter is suitable for an optical element.

【0012】更には、第2の半導体素子、第2の金属細
線および第2の金属細線が接続された第2のリードを封
止する所定の粘度を持った封止樹脂を設け、リードフレ
ームを金型に配置し、封止樹脂を前記金型に接触させた
状態で、封止樹脂とは異なる樹脂で封止する事で解決す
るものである。
Further, a sealing resin having a predetermined viscosity for sealing the second semiconductor element, the second thin metal wire, and the second lead to which the second thin metal wire is connected is provided, and the lead frame is formed. This problem can be solved by disposing the sealing resin in a mold, and sealing with a resin different from the sealing resin in a state where the sealing resin is in contact with the mold.

【0013】発光素子、磁気センサ等は、これらを封止
する樹脂の表面に平坦性を要求し、ポッティングされた
流動性のある樹脂を金型に当接させ、この当接面で形成
される平坦面を維持しながら別の樹脂で封止すれば、両
方の樹脂表面は、フラットに形成できる。
A light emitting element, a magnetic sensor, and the like require flatness on the surface of a resin for sealing them, and a potted fluid resin is brought into contact with a mold, and is formed on the contact surface. By sealing with another resin while maintaining a flat surface, both resin surfaces can be formed flat.

【0014】[0014]

【発明の実施の形態】以下に本発明の第1の実施の形態
を図1を参照しながら詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below in detail with reference to FIG.

【0015】まず絶縁性基板10があり、この上には接
着剤等によりCu箔パターンが形成されている。このパ
ターンは、半導体素子が実装されるランド11、回路を
構成するための配線、この配線の端部に形成されるボン
ディング用パッド12、チップコンデンサ等をロウ材で
固着するための電極13等で成る。
First, there is an insulating substrate 10 on which a Cu foil pattern is formed by an adhesive or the like. This pattern includes lands 11 on which semiconductor elements are mounted, wiring for forming a circuit, bonding pads 12 formed at the ends of the wiring, electrodes 13 for fixing chip capacitors and the like with a brazing material, and the like. Become.

【0016】また前述した絶縁性基板10は、ここでは
プリント基板を採用したが、フレキシブルシート、ガラ
ス基板、セラミック基板等でも良い。
Although the above-described insulating substrate 10 employs a printed substrate here, it may be a flexible sheet, a glass substrate, a ceramic substrate, or the like.

【0017】このパターンには、第1の半導体素子1
4、第2の半導体素子15、チップコンデンサ、チップ
抵抗等の受動素子RCが固着され、ロウ材や金属細線W
で電気的に接続されている。
In this pattern, the first semiconductor element 1
4. The second semiconductor element 15, the passive element RC such as a chip capacitor and a chip resistor are fixed, and the brazing material or the thin metal wire W is fixed.
Are electrically connected.

【0018】またCuを主材料とするリードフレームが
用意され、このリードフレームの構成要素であるアイラ
ンド16に前記絶縁性基板10が固着される。そして、
第1のリード18と例えばパッド12が金属細線19
で、第2のリード20と第2の半導体素子15が金属細
線21で接続されている。
A lead frame mainly composed of Cu is prepared, and the insulating substrate 10 is fixed to an island 16 which is a component of the lead frame. And
The first lead 18 and, for example, the pad 12 are thin metal wires 19.
Thus, the second lead 20 and the second semiconductor element 15 are connected by a thin metal wire 21.

【0019】更には、第2の半導体素子15は、透明な
エポキシ樹脂、シリコーン樹脂等の第2の樹脂封止部材
22でポッティングされ、全体が第1の樹脂封止部材2
3で封止されている。
Further, the second semiconductor element 15 is potted with a second resin sealing member 22 made of a transparent epoxy resin, silicone resin, or the like, and the entire first semiconductor element 15 is potted.
3 is sealed.

【0020】本発明の特徴は、第1の樹脂封止部23で
実質全体を封止すると共に、第2の半導体素子15を第
2の樹脂封止部22で封止したことにある。
A feature of the present invention resides in that substantially the entirety is sealed by the first resin sealing portion 23 and that the second semiconductor element 15 is sealed by the second resin sealing portion 22.

【0021】前記第1の半導体素子15が光素子である
場合は、第2の樹脂封止部は、透明なエポキシ樹脂等で
なり、後述する金型で封止されるため第1の樹脂封止部
23と一緒につらいちに形成されている。第2の樹脂封
止部材のフィラー混入率は、第1の樹脂封止部材よりも
少ないか、全く入っていないため、樹脂に発生する応力
が大きくなるが、実質第1の半導体素子のみ封止してい
るので、他の素子への影響は抑制される。
In the case where the first semiconductor element 15 is an optical element, the second resin sealing portion is made of a transparent epoxy resin or the like, and is sealed with a mold described later. Together with the stop 23, it is formed stubbornly. Since the filler mixing ratio of the second resin sealing member is smaller than that of the first resin sealing member or does not enter at all, the stress generated in the resin increases, but substantially only the first semiconductor element is sealed. Therefore, the influence on other elements is suppressed.

【0022】また第1の半導体素子が磁気センサ等の場
合、応力が少ないシリコーン樹脂で覆われ、やはりつら
いちで形成される。
When the first semiconductor element is a magnetic sensor or the like, the first semiconductor element is covered with a low-stress silicone resin, and is also formed with ease.

【0023】従って製品としての表面形状、光素子や磁
気センサに必要なその表面のフラット性が維持でき、光
素子では、光の発光受光が良好にでき、磁気センサで
は、その検出媒体との間隔を一定に保つことができる。
Therefore, the surface shape as a product, the flatness of the surface required for an optical element or a magnetic sensor can be maintained, the optical element can emit and receive light satisfactorily, and the magnetic sensor has a good distance from its detection medium. Can be kept constant.

【0024】第2の実施の形態を図2に示す。これは、
第2の半導体素子15をアイランド16の表面から裏面
に移したもので、両者の間には、仮に絶縁が必要として
絶縁材が形成されている。ここでも第1の樹脂封止部2
3と第2の樹脂封止部22は、つらいちで形成されてい
る。
FIG. 2 shows a second embodiment. this is,
The second semiconductor element 15 is moved from the front surface of the island 16 to the back surface, and an insulating material is formed between the two because it is temporarily required to be insulated. Again, the first resin sealing portion 2
The third and second resin sealing portions 22 are formed in a smooth manner.

【0025】続いて第3の実施の形態を図3を用いて説
明する。本実施の形態は、前記絶縁性基板10を省略し
たものである。本発明は、絶縁性基板10上のCuパタ
ーンの代わりにリードを活用したものである。
Next, a third embodiment will be described with reference to FIG. In the present embodiment, the insulating substrate 10 is omitted. The present invention utilizes a lead instead of the Cu pattern on the insulating substrate 10.

【0026】前記絶縁性基板10は、厚みが有るため、
半導体装置としてはその厚みが大きくなるが、リードに
受動素子RCが接続されているので、その厚みを小さく
できる特徴を有する。
Since the insulating substrate 10 has a thickness,
Although the semiconductor device has a large thickness, it has a feature that the thickness can be reduced because the passive element RC is connected to the lead.

【0027】では簡単に説明する。アイランド16に
は、第1の半導体素子14と第2の半導体素子15が実
装されている。この第2の半導体素子15の周りには、
ライン状の樹脂30で樹脂のストッパー30が形成さ
れ、ここに第2の樹脂封止部材22が塗布されている。
またリード間には受動素子RCであるチップコンデン
サ、チップ抵抗等がロウ材で電気的に接続固着されてい
る。そして例えば封止部材の中で所定の回路機能を構成
している。また封止部材から導出するリードに外付け部
品を取り付けることで、所定の回路機能を実現しても良
い。
A brief description will now be given. A first semiconductor element 14 and a second semiconductor element 15 are mounted on the island 16. Around the second semiconductor element 15,
A resin stopper 30 is formed of the line-shaped resin 30, and the second resin sealing member 22 is applied here.
A chip capacitor, a chip resistor, and the like, which are passive elements RC, are electrically connected and fixed between the leads with a brazing material. For example, a predetermined circuit function is configured in the sealing member. A predetermined circuit function may be realized by attaching an external component to a lead derived from the sealing member.

【0028】更に第1および第2の実施の形態と同様
に、第1の樹脂封止部23、第2の樹脂封止部22が形
成される。
Further, similarly to the first and second embodiments, a first resin sealing portion 23 and a second resin sealing portion 22 are formed.

【0029】全実施例において、例えば光ICモジュー
ル、IrDA等の応用すれば、これらは受動素子が少な
いため、これらも一緒に一体ができ、コストを低下でき
ると共に、これを用いたセットも組立等の作業を簡略に
できる。
In all embodiments, for example, if an optical IC module, IrDA or the like is applied, since these have few passive elements, they can be integrated together to reduce the cost, and a set using this can be assembled. Work can be simplified.

【0030】またタグ等に採用した場合、コイルだけを
外部に導出したリードに外付けするだけで製品化が可能
となる。
When employed in a tag or the like, it is possible to commercialize the product simply by externally attaching only the coil to a lead led out.

【0031】続いて、第2の樹脂封止部22と第1の樹
脂封止部23とのつらいちの仕方について簡単に説明す
る。ここでは図1の第1の実施の形態を使って説明す
る。また第2および第3の実施の形態については、実質
同じ方法で形成されるので、省略する。が、別の実施例
のものも実質同じであるまず図4のように、半導体素子
14、15、受動素子RCが実装された絶縁性基板10
を用意し、金属細線を接続した後、前記絶縁性基板をリ
ードフレームのアイランド16に固着し、第2の樹脂封
止部材をポッティングする。この樹脂は、周りに流れ出
なく、金型K1またはK2に当接できるある高さを維持
できる粘性を有している。
Next, the manner in which the second resin sealing portion 22 and the first resin sealing portion 23 are connected will be briefly described. Here, a description will be given using the first embodiment of FIG. Further, the second and third embodiments are formed by substantially the same method, and thus the description is omitted. However, another embodiment is substantially the same. First, as shown in FIG. 4, the insulating substrate 10 on which the semiconductor elements 14, 15 and the passive element RC are mounted is mounted.
After connecting the fine metal wires, the insulating substrate is fixed to the island 16 of the lead frame, and the second resin sealing member is potted. This resin has a viscosity that does not flow around and maintains a certain height at which the resin can abut the mold K1 or K2.

【0032】続いて、前記リードフレームを金型K1、
K2に組み込み、第1の樹脂封止部材を流し込む。当然
図2の構造では、上下が反転されて金型に配置される。
また前記第2の樹脂封止部材22は、金型に組み込んで
からポッティングしても良い。
Subsequently, the lead frame is connected to a mold K1,
The first resin sealing member is poured into K2. As a matter of course, in the structure shown in FIG.
The second resin sealing member 22 may be potted after being incorporated in a mold.

【0033】ここでは第2の樹脂封止部材が上金型K1
に当接するため、第1の樹脂封止部23と同一面を構成
できる。
Here, the second resin sealing member is an upper mold K1.
Therefore, the same surface as the first resin sealing portion 23 can be formed.

【0034】ここで前記第2の樹脂封止部材は、第1の
樹脂封止部材23を注入する前に、前記金型の熱で硬化
した方が良い。これは注入圧力で第2の樹脂封止部材が
変形する恐れがあるからである。また図1、図2のよう
に絶縁性基板を採用する比較的サイズの大きいもの、ま
たは絶縁基板を採用しなくてもアイランドが大きい場合
(図3の構造を金型に配置した場合)、金型に当接した
後、アイランド16裏面を支持する手段を設ける必要が
ある。これはアイランドの上下変動により、注入時の樹
脂圧力で樹脂漏れが発生したり、アイランド上の半導体
素子が欠けたりする問題があるからである。
Here, it is preferable that the second resin sealing member is cured by the heat of the mold before injecting the first resin sealing member 23. This is because the second resin sealing member may be deformed by the injection pressure. In addition, as shown in FIGS. 1 and 2, a relatively large-sized substrate employing an insulating substrate, or a large island without employing an insulating substrate (when the structure shown in FIG. 3 is arranged in a mold) is used. After contacting the mold, it is necessary to provide a means for supporting the back surface of the island 16. This is because there is a problem that a resin leak occurs due to a resin pressure at the time of injection and a semiconductor element on the island is chipped due to the vertical fluctuation of the island.

【0035】また図3のようにダム30を用い、粘度と
突出量を制御すれば、前記第1の樹脂封止部から露出す
る第2の樹脂封止部の領域を制御できる。
If the viscosity and the amount of protrusion are controlled by using the dam 30 as shown in FIG. 3, the area of the second resin sealing portion exposed from the first resin sealing portion can be controlled.

【0036】つまり光素子では、第2の樹脂封止部22
で一定面積の透過性の窓を実現できるメリットも有す
る。
That is, in the optical element, the second resin sealing portion 22
Thus, there is an advantage that a transparent window having a fixed area can be realized.

【0037】また全実施の形態に言えることであるが、
第2の半導体素子とリード20を接続する金属細線21
も第2の樹脂封止部でカバーした方がよい。この場合、
アイランド16とリード20の隙間からポッティング樹
脂が流れないように、両者のクリアランスを調整するこ
とが好ましい。つまり例えば0.2〜0.1mm程度の
隙間とすれば、ポッティング樹脂は、この隙間から流れ
落ちないため、樹脂量を一定に保つことができ、露出面
積も精度良くコントロールできる。
As can be said in all the embodiments,
Fine metal wire 21 connecting second semiconductor element and lead 20
Should be covered with the second resin sealing portion. in this case,
It is preferable to adjust the clearance between the island 16 and the lead 20 so that the potting resin does not flow through the gap. That is, for example, if the gap is set to about 0.2 to 0.1 mm, the potting resin does not flow down from this gap, so that the resin amount can be kept constant and the exposed area can be accurately controlled.

【0038】[0038]

【発明の効果】以上に説明した通り、本発明によれば、
通常の半導体素子と特殊な半導体素子(例えば光素子、
磁気センサ等)を一体モールドできる。特に金型でモー
ルドする際、第2の樹脂封止部材を金型に当接させた後
に第1の樹脂封止部材を注入するので、第2の樹脂封止
部の露出面を第1の樹脂封止部とつらいちにできる。
As described above, according to the present invention,
Normal semiconductor devices and special semiconductor devices (such as optical devices,
Magnetic sensor etc.) can be integrally molded. In particular, when molding with a mold, since the first resin sealing member is injected after the second resin sealing member is brought into contact with the mold, the exposed surface of the second resin sealing portion is fixed to the first resin sealing member. It can be made with resin sealing part.

【0039】更には、絶縁性基板を用いたフルモール
ド、受動素子をリードに固着したフルモールドが可能で
あるため、光モジュール、タグ、ICカード等の構成部
品として好適である。
Further, since full molding using an insulating substrate and full molding in which passive elements are fixed to leads are possible, they are suitable as components of optical modules, tags, IC cards and the like.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態を説明する半導体装
置の断面図である。
FIG. 1 is a cross-sectional view of a semiconductor device illustrating a first embodiment of the present invention.

【図2】本発明の第2の実施の形態を説明する半導体装
置の断面図である。
FIG. 2 is a cross-sectional view of a semiconductor device illustrating a second embodiment of the present invention.

【図3】本発明の第3の実施の形態を説明する半導体装
置の断面図である。
FIG. 3 is a cross-sectional view of a semiconductor device illustrating a third embodiment of the present invention.

【図4】本半導体装置の製造方法を説明する図である。FIG. 4 is a diagram illustrating a method for manufacturing the semiconductor device.

【図5】本半導体装置の製造方法を説明する図である。FIG. 5 is a diagram illustrating a method for manufacturing the semiconductor device.

【図6】従来例の半導体装置を説明するための平面図で
ある。
FIG. 6 is a plan view illustrating a conventional semiconductor device.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 井野口 浩 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 Fターム(参考) 4M109 AA01 BA01 CA04 CA21 EC04 EC11 FA06 GA01 GA02  ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Hiroshi Inoguchi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 4M109 AA01 BA01 CA04 CA21 EC04 EC11 FA06 GA01 GA02

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 アイランドと、前記アイランドの少なく
とも一側辺から外に向かい配置された複数のリードと、
前記アイランドに固着された絶縁性基板と、前記絶縁性
基板に貼着された導電性パターンと、前記絶縁性基板に
固着され、前記導電パターンと電気的に接続された複数
のベアチップ状の半導体素子と、前記絶縁性基板に固着
され、前記導電パターンと電気的に接続されたチップ状
の受動素子と、前記リード、前記導電パターン、前記複
数の半導体素子および前記受動素子を封止する樹脂封止
部とを有する半導体装置に於いて、 前記複数の半導体素子の中の第1の半導体素子は、実質
全域を封止する第1の樹脂封止部でカバーされ、前記第
2の半導体素子は、前記第1の樹脂封止部と材質の異な
る第2の樹脂封止部でカバーされ、前記第2の樹脂封止
部は、前記第1の樹脂封止部から露出し、その表面は前
記第1の樹脂封止部と同一面で成る事を特徴とした半導
体装置。
An island; and a plurality of leads disposed outwardly from at least one side of the island;
An insulating substrate fixed to the island, a conductive pattern attached to the insulating substrate, and a plurality of bare chip semiconductor elements fixed to the insulating substrate and electrically connected to the conductive pattern; And a chip-shaped passive element fixed to the insulating substrate and electrically connected to the conductive pattern, and resin sealing for sealing the lead, the conductive pattern, the plurality of semiconductor elements, and the passive element. Wherein the first semiconductor element of the plurality of semiconductor elements is covered with a first resin sealing part that seals substantially the entire area, and the second semiconductor element is The first resin sealing portion is covered with a second resin sealing portion having a different material from that of the first resin sealing portion. The second resin sealing portion is exposed from the first resin sealing portion, and the surface thereof is the second resin sealing portion. Be made of the same surface as the resin sealing part A semiconductor device characterized by the following.
【請求項2】 アイランドと、前記アイランドの少なく
とも一側辺から外に向かい配置された複数のリードと、
前記アイランドに固着された複数のベアチップ状の半導
体素子と、前記リードに固着され、電気的に接続された
チップ状の受動素子と、前記リード、前記複数の半導体
素子および前記受動素子を封止する樹脂封止部とを有す
る半導体装置に於いて、 前記複数の半導体素子の中の第1の半導体素子は、実質
全域を封止する第1の樹脂封止部でカバーされ、前記第
2の半導体素子は、前記第1の樹脂封止部と材質の異な
る第2の樹脂封止部でカバーされ、前記第2の樹脂封止
部は、前記第1の樹脂封止部から露出し、その表面は前
記第1の樹脂封止部と同一面で成る事を特徴とした半導
体装置。
2. An island, and a plurality of leads disposed outward from at least one side of the island,
A plurality of bare chip-shaped semiconductor elements fixed to the island, a chip-shaped passive element fixed to the lead and electrically connected thereto, and the lead, the plurality of semiconductor elements and the passive element are sealed. A first semiconductor element among the plurality of semiconductor elements is covered with a first resin sealing part that seals substantially the entire area, and the second semiconductor element The element is covered with a second resin sealing portion made of a material different from that of the first resin sealing portion. The second resin sealing portion is exposed from the first resin sealing portion and has a surface. Is a semiconductor device comprising the same surface as the first resin sealing portion.
【請求項3】 前記第2の半導体素子は、前記アイラン
ドの裏面に固着される請求項1または請求項2記載の半
導体装置。
3. The semiconductor device according to claim 1, wherein said second semiconductor element is fixed to a back surface of said island.
【請求項4】 前記第2の樹脂封止部は、シリコーン樹
脂または透明樹脂から成る請求項1、請求項2または請
求項3記載の半導体装置。
4. The semiconductor device according to claim 1, wherein said second resin sealing portion is made of a silicone resin or a transparent resin.
【請求項5】 前記第2の半導体素子は、受光素子また
は発光素子から成る請求項4記載の半導体装置。
5. The semiconductor device according to claim 4, wherein said second semiconductor element comprises a light receiving element or a light emitting element.
【請求項6】 リードフレームを構成するアイランドま
たはこのアイランドに載置された絶縁性基板に複数の半
導体素子を実装し、 前記半導体素子の中の第1の半導体素子と前記リードフ
レームを構成する第1のリード、前記半導体素子の中の
第2の半導体素子と前記リードフレームを構成する第2
のリードを第1の金属細線および第2の金属細線で接続
し、 前記第2の半導体素子、前記第2の金属細線および前記
第2の金属細線が接続された前記第2のリードを封止す
る所定の粘度を持った封止樹脂を設け、 前記リードフレームを金型に配置し、前記封止樹脂を前
記金型に接触させた状態で、前記封止樹脂とは異なる樹
脂で封止する事を特徴とした半導体装置の製造方法。
6. A plurality of semiconductor elements are mounted on an island constituting a lead frame or an insulating substrate mounted on the island, and a first semiconductor element among the semiconductor elements and a first semiconductor constituting the lead frame. 1 lead, a second semiconductor element among the semiconductor elements, and a second
Are connected by a first thin metal wire and a second thin metal wire, and the second semiconductor element, the second thin metal wire, and the second lead to which the second thin metal wire is connected are sealed. A sealing resin having a predetermined viscosity is provided, the lead frame is arranged in a mold, and the sealing resin is sealed with a resin different from the sealing resin in a state where the sealing resin is in contact with the mold. A method for manufacturing a semiconductor device, comprising:
【請求項7】 前記封止樹脂は、前記リードフレームを
金型に配置した後に設ける請求項6記載の半導体装置の
製造方法。
7. The method according to claim 6, wherein the sealing resin is provided after the lead frame is arranged in a mold.
JP10337852A 1998-11-27 1998-11-27 Semiconductor device and its manufacture Pending JP2000164803A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10337852A JP2000164803A (en) 1998-11-27 1998-11-27 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10337852A JP2000164803A (en) 1998-11-27 1998-11-27 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JP2000164803A true JP2000164803A (en) 2000-06-16

Family

ID=18312595

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000164803A (en)

Cited By (5)

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Publication number Priority date Publication date Assignee Title
JP2004319530A (en) * 2003-02-28 2004-11-11 Sanyo Electric Co Ltd Optical semiconductor device and its manufacturing process
WO2011148441A1 (en) * 2010-05-25 2011-12-01 パナソニック株式会社 Method for manufacturing semiconductor device, and semiconductor device
JP2014060404A (en) * 2006-07-14 2014-04-03 Allegro Microsystems Llc Sensor
JP2015198098A (en) * 2014-03-31 2015-11-09 愛知時計電機株式会社 Transmitter-receiver
WO2022123981A1 (en) * 2020-12-07 2022-06-16 Nissha株式会社 Electronic component-equipped resin casing and method for producing same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319530A (en) * 2003-02-28 2004-11-11 Sanyo Electric Co Ltd Optical semiconductor device and its manufacturing process
JP2014060404A (en) * 2006-07-14 2014-04-03 Allegro Microsystems Llc Sensor
US9228860B2 (en) 2006-07-14 2016-01-05 Allegro Microsystems, Llc Sensor and method of providing a sensor
WO2011148441A1 (en) * 2010-05-25 2011-12-01 パナソニック株式会社 Method for manufacturing semiconductor device, and semiconductor device
JP2015198098A (en) * 2014-03-31 2015-11-09 愛知時計電機株式会社 Transmitter-receiver
WO2022123981A1 (en) * 2020-12-07 2022-06-16 Nissha株式会社 Electronic component-equipped resin casing and method for producing same
EP4201632A4 (en) * 2020-12-07 2024-03-27 Nissha Co Ltd Electronic component-equipped resin casing and method for producing same

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