JP3375742B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention disclosed in this specification relates to a structure of a thin film transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art A thin film transistor (generally called a TFT) using a thin film semiconductor formed on a substrate having an insulating surface such as a glass substrate is known. This thin film transistor is used in various integrated circuits. In particular, an example is known in which the active matrix type liquid crystal display device is arranged in each pixel portion and used for switching pixels.

Amorphous silicon films and crystalline silicon films are known as types of thin film semiconductors. The amorphous silicon film has a characteristic that it is excellent in productivity because of its ease of film formation, but it has a problem that its electrical characteristics are low and the characteristics of the obtained thin film transistor are low. On the other hand, the crystalline silicon film has a feature that a thin film transistor having high characteristics can be obtained. However, under the present circumstances, a single crystal silicon film cannot be obtained, so that the obtained film has a polycrystalline structure or a microcrystalline structure (these are collectively referred to as a crystalline silicon film).

FIG. 2A shows an example of a typical thin film transistor. FIG. 2 shows that the N-type source region 2 is formed on the surface of the glass substrate 201 on which the silicon oxide film 202 is formed.
03, substantially genuine (I-type) channel forming region 20
4. The gate insulating film 205, the gate electrode 207, the interlayer insulating film 208, the source electrode 209, and the drain electrode 21.
Has 0.

In a thin film transistor using such a crystalline silicon film, the presence of an OFF current (also referred to as a leakage current) becomes a big problem. The OFF current means, for example, a channel formation region 204 and a drain region 205 when a negative potential is applied to the gate electrode 207 when the N-channel thin film transistor is OFF as shown in FIG.
A phenomenon in which an electric current flows between and. With the N-channel thin film transistor turned off, the gate electrode 20
When a negative potential is applied to 7, the portion of the channel formation region 204 in contact with the gate insulating film 206 becomes P-type. Therefore, if the thin film semiconductor forming the active layer (where the source / drain regions and the channel formation region are formed) is a single crystal, a PN junction will be formed between the source / drain and the source / drain No large current flows between them. However, when the thin film semiconductor forming the active layer has a polycrystalline structure or a microcrystalline structure, a high electric field formed between the source region or the drain region and the channel formation region causes carriers to pass through the crystal grain boundaries. Movement will occur. As a result, the OFF current becomes relatively large.

As a method of reducing the OFF current, a technique using an LDD structure or an offset gate structure is known. These structures prevent the electric field from concentrating on the interface between the source or drain region and the channel formation region and in the vicinity thereof, and reduce the OFF current.

[Process leading to the invention] According to the research conducted by the present inventors, the LDD structure and the offset gate structure are OF
Although it is certainly effective in reducing the F current, it has been found that essentially no significant improvement can be obtained. Therefore, various parameters were changed and the dependence of the OFF current on various parameters was investigated. As a result, it was found that the OFF current hardly changed even when the width of the active layer was changed. FIG. 2B shows a schematic shape of the active layer. Figure 2
In (B), 21 is a source region, 22 is a channel formation region, and 23 is a drain region. W is the width of the active layer and L is the length of the active layer.

First, when the width W of the active layer is changed, OF
No significant change was observed in the value of F current. If O
If the carriers causing the FF current are moved over the entire cross section of the active layer, the OFF current value should be changed by changing the width W of the active layer. This is because the area of the carrier passage that causes the OFF current (the cross-sectional area of the active layer) changes as the width W of the active layer changes.

On the other hand, when the thickness of the active layer was changed, a remarkable change in the OFF current value was observed depending on the change. That is, by reducing the thickness of the active layer, O
It was confirmed that the FF current decreased.

The above experimental facts result from the fact that the carriers causing the OFF current are mainly moved on the side surface 24 of the active layer. As described above, when carriers that cause an OFF current are mainly moved on the side surface 24 of the active layer, changing the cross-sectional area of the active layer has almost no effect on the carrier movement. The value of the current hardly changes. On the other hand, when the thickness of the active layer is reduced, the passage of carriers is narrowed, so that the OFF current is reduced.

Carriers move through the side surface of the active layer because a large number of traps are concentrated on the side surface of the junction between the channel forming region and the source or drain region. To do. The concentration of traps on the side surface of the active layer is due to the following reasons. Generally, a dry etching method such as RIE is used to form the active layer. In this case, plasma damage becomes significant at the peripheral edge of the active layer. Then, defects are intensively formed on the side surfaces of the etched active layer. That is, traps are concentrated on the side surface of the active layer.

In order to eliminate or reduce the traps existing on the side surface of the active layer, defects on the side surface of the active layer are reduced after the patterning process (patterning by dry etching) for forming the active layer to reduce the trap density. Needs to be lowered. That is, it is necessary to perform some annealing on the side surface of the active layer. The invention described in the present specification has been made through the processes described above.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to obtain a thin film transistor having a small OFF current.

[0014]

One of the inventions disclosed in the present specification is characterized in that the crystallinity of the peripheral edge of the active layer is particularly enhanced. In the above structure, as the active layer in which the source region, the drain region and the channel forming region are formed, the structures shown by 106, 108 and 107 in FIG. 1 can be mentioned. In FIG. 1, 106 and 10
Reference numeral 8 is a source region and a drain region, and 107 is a channel forming region. Further, in the configuration shown in FIG.
Source / drain regions and channel formation regions are formed in the active layer (semiconductor layer 103).
Further, a light doped region, an offset gate region, etc. may be formed in the active layer.

According to another aspect of the invention, the active layer has a source region, a drain region and a channel forming region, and the active layer is at least at the interface between the drain region and the channel forming region and / or in the vicinity thereof. The side surface of is particularly characterized by having enhanced crystallinity.

According to another aspect of the invention, a step of forming an amorphous silicon film on a substrate having an insulating surface, a step of crystallizing the amorphous silicon film into a crystalline silicon film, and the crystalline silicon film The method is characterized by including a step of patterning a film to form an active layer, and a step of irradiating the active layer with laser light or strong light.

In the above structure, examples of the substrate having an insulating surface include a glass substrate, a quartz substrate, a glass substrate having an insulating film formed thereon, a semiconductor substrate having an insulating film formed thereon, and a conductor substrate having an insulating film formed thereon. be able to.

As a method of crystallizing the silicon film, there are a heating method, a method of irradiating laser light or strong light, and a method of combining heating and irradiation of laser light or strong light. Further, it is useful to adopt a crystallization method using a metal element that promotes crystallization of the amorphous silicon film. In this case, metal elements such as Fe, Co, Ni, Cu, Ru,
One or more elements selected from Rh, Pd, Ag, Os, Ir, Pt, and Au can be used. In particular, a remarkable effect can be obtained when Ni (nickel) is used. Specifically, a crystalline silicon film can be obtained by heat treatment at 550 ° C. (conventional 600 ° C. or higher) for about 4 hours (conventional 12 hours or more). Further, it is effective to combine irradiation with laser light or intense light with crystallization by heating using this metal element.

In order to introduce this metal element into the amorphous silicon film, a thin film of the metal element or a thin film containing the metal element may be formed on the surface of the amorphous silicon film.

The concentration of the metal element in the active layer is 1 ×
It is preferably 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . If the concentration is lower than this range, the effect of promoting crystallization is small, and if the concentration is higher than this range, the characteristics of the semiconductor behave as a metal, which is inconvenient for use in semiconductor devices. It will be something like.

Irradiation with laser light or intense light after forming the active layer by patterning is performed by annealing the peripheral edge of the active layer to remove defects on the peripheral edge of the active layer, particularly on the side surface of the active layer. This is to reduce it.

It is effective to selectively and intensively irradiate the laser light or the intense light to the peripheral end portion of the active layer. Further, it is extremely effective to irradiate the side surface of the active layer with laser light.

According to another invention disclosed in the present specification, a step of forming an amorphous silicon film on a substrate having an insulating surface, a step of crystallizing the amorphous silicon film into a crystalline silicon film,
Patterning the crystalline silicon film to form an active layer, irradiating the active layer with a laser beam or strong light, and conducting at least a part of a side surface of the active layer opposite to the source / drain regions. And a step of implanting an impurity that imparts a mold.

The order of the step of irradiating laser light or intense light and the step of implanting an impurity imparting a conductivity type opposite to that of the source / drain regions to at least a part of the side surface of the active layer may be reversed.

The region for injecting the impurity imparting the conductivity type opposite to that of the source / drain region needs to be at least the side surface of the active layer where the interface between the channel forming region and the source / drain region exists.

[0026]

Function: Defects are intensively formed on the side surface of the active layer formed by patterning due to plasma damage or damage during etching. That is, defects are concentrated on the side surface of the active layer. Therefore, by irradiating laser light or intense light after forming the active layer, it is possible to reduce defects generated on the side surface of the active layer during formation. In particular, by irradiating the side surface of the active layer with laser light, the defects existing on the side surface of the active layer can be effectively reduced.

As described above, by reducing the defects existing on the side surface of the active layer by the irradiation of the laser beam or the intense light, the trap density on the side surface of the active layer can be decreased, and the trap on the side surface of the active layer can be reduced. The number of carriers traveling via can be reduced. Thus, a thin film transistor with a small OFF current can be realized.

Further, by making the peripheral end of the active layer have a conductivity type opposite to that of the source / drain region, a PN junction is formed between the channel forming region and the source / drain region on the side surface of the active layer during the OFF operation. It can be formed, and the insulating property between the source / drain can be improved.

[0029]

【Example】

[Embodiment 1] FIG. 1 shows an example of the thin film transistor shown in this embodiment. First, a silicon oxide film 102 is formed as a base film on a glass substrate 101 to a thickness of 2000 Å by a sputtering method. Next, an amorphous silicon film is formed to a thickness of 1000 Å by the plasma CVD method or the low pressure thermal CVD method. Then, heat treatment is performed to obtain a crystalline silicon film.
Irradiating a laser beam after the heat treatment is extremely effective in improving the crystallinity of the obtained crystalline film. Next, patterning is performed by etching using the RIE method to form an active layer 103 shown in FIG. In this state, the area indicated by 100 receives plasma damage. In particular, defects are intensively generated on the side surface of the active layer.

FIG. 3 is a sectional view taken along line BB ′ of FIG.
Shown in. 3A and 3B show a laser light irradiation method described later. In addition, A- in FIG.
A cross section cut along A ′ is shown in FIG. As shown in FIG. 3, the plasma-damaged area, indicated at 100, extends over the entire perimeter of the active layer.

By irradiating with laser light, plasma damage on the side surface of the active layer indicated by 100 can be annealed. Of course, the crystallinity of the entire active layer is also improved. The laser light is KrF
An excimer laser or a XeCl excimer laser can be used. Simultaneously with the irradiation of this laser light, sample 2
It is effective to heat to a temperature of 00 to 500 ° C. This is because by using the heating in combination, the melting time of the silicon surface following the irradiation of the laser light is lengthened and the annealing effect by the irradiation of the laser light is enhanced.

Intense light such as infrared light may be used instead of laser light. After irradiation with this laser light,
Further heat treatment is effective in reducing defects in the active layer.

As a method of irradiating with laser light, the method shown in FIG.
There are two methods shown in (A) and (B). The method shown in (A) is performed from the upper side to the entire surface, is the most general method, and is the method excellent in productivity and controllability. In this method, energy is concentrated on the peripheral edge of the active layer, so that the crystallinity on the side surface of the active layer can be made particularly high. That is, the crystallinity on the side surface of the active layer can be made particularly high in the entire active layer.

The method shown in (B) is a method in which the side surface of the active layer is positively irradiated with laser light by obliquely irradiating the laser light. When this method is adopted, the annealing effect on the side surface of the active layer can be made extremely high. In order to perform the laser light irradiation from the oblique direction as shown in (B), the substrate may be inclined and the laser light may be irradiated.

In this way, the defects on the peripheral side surface of the active layer can be eliminated or greatly reduced. Next, a silicon oxide film 104 functioning as a gate insulating film is formed to a thickness of 1000 Å by the plasma CVD method. Then, a well-known film mainly composed of silicon doped with phosphorus at a high concentration is formed and patterned to form the gate electrode 105. Then, phosphorus ions are implanted to form the source / drain regions. N here
Phosphorus ions are implanted to form a channel-type thin film transistor. If boron ions are implanted here, a P-channel thin film transistor can be obtained.

In this process, the source region 106 is self-aligned.
And a drain region 108 are formed. The channel formation region 107 is also formed at the same time. Then, laser light irradiation is performed to activate the source region 106 and the drain region 108. In this step, strong light may be irradiated instead of laser light irradiation. Further, the source / drain regions may be activated by heating.

Then, the silicon oxide film 10 is used as an interlayer insulating film.
9 is deposited to a thickness of 7,000 Å by the plasma CVD method, and a source electrode 110 and a drain electrode 111 are formed through a hole forming process. Then, heat treatment is performed in a hydrogen atmosphere at 350 ° C. for 1 hour, so that FIG.
The thin film transistor shown in is completed.

[Embodiment 2] This embodiment is an example in which the invention disclosed in the present specification is applied to a thin film transistor having an offset gate structure and a lightly doped region. FIG. 4 shows a manufacturing process of the thin film transistor shown in this embodiment.

First, a silicon oxide film is formed as a base film on the glass substrate 401 to a thickness of 2000 liters by the plasma CVD method or the sputtering method. Next, the amorphous silicon film 403
By plasma CVD or low pressure thermal CVD
Form a film with a thickness of 000Å. Then, nickel is introduced into the amorphous silicon as a metal element for promoting crystallization of the amorphous silicon film. Here, nickel is introduced into the amorphous silicon film 403 by using a nickel acetate salt solution. That is,
A nickel acetate solution is applied onto the amorphous silicon film 403 by using a spinner, so that the nickel element is held in contact with the surface of the amorphous silicon film 403. Further, the nickel concentration in the active layer is 1 × 10 ¹⁶ cm ⁻³
It is important to control the amount of nickel introduced so that the amount is 1 × 10 ¹⁹ cm ⁻³ . Here, the amount of nickel introduced may be controlled by controlling the nickel concentration in the nickel acetate salt solution. Further, as a method of introducing nickel, a plasma treatment, a sputtering method, a plasma CVD method, or an ion implantation method may be used.

Then, the amorphous silicon film is transformed into a crystalline silicon film by heating or irradiating laser light, or by combining heating and laser light irradiation. Here, heat treatment is performed at 550 ° C. for 4 hours in a nitrogen atmosphere to obtain a crystalline silicon film. (Fig. 4 (A))

Next, patterning is performed to form an active layer 404 of the thin film transistor. Here, isotropic etching is performed to form a peripheral edge portion of the active layer 404 indicated by 420 in a tapered shape. Details of this step will be described with reference to FIG. First, a resist mask 800 is formed on the upper surface of the silicon film 403. Then, by performing isotropic plasma etching, dotted lines 802 and 801 in FIG.
Etching progresses as shown by. As a result, the active layer 404 having a tapered shape can be obtained as indicated by 420 in FIG. 8B.

By tapering the portion indicated by 420, the wiring formed on the active layer can be prevented from being disconnected. However, since plasma damage is concentrated on the peripheral edge portion of the active layer indicated by 420, many traps are concentrated and exist. Then, laser light is irradiated to reduce traps on the side surface of the end portion of the active layer. Irradiation with laser light may be performed on the entire surface of the active layer as shown in FIG. 3A, or as shown in FIG. You can go.

After that, the silicon oxide film 400 is subjected to plasma CVD.
Method or low pressure thermal CVD method. Then 600
An aluminum film having a thickness of 0Å is formed by an electron beam evaporation method or a sputtering method. This aluminum film contains 1 wt% silicon or 0.1 wt% scandium. And 50 to 10 on the surface of the aluminum film
An anodic oxide film 405 of about 0Å is formed. This anodic oxide film is formed by performing anodic oxidation with an aluminum film as an anode in an ethylene glycol solution containing 3 to 10% tartaric acid. Here, the applied voltage is 1
A dense barrier type anodic oxide film is formed with a voltage of 00 to 200 V, for example 150 V.

Then, a mask using a photoresist is formed, and a patterned aluminum film 406 is formed by a dry etching method. On this aluminum film, there is a dense oxide layer 405 formed by the previous anodic oxidation. (Fig. 4 (C))

Next, anodic oxidation is performed in a 3 to 20% citric acid or nitric acid solution to obtain a thickness of 3000 to 1 μm.
m Porous oxide layer 40 having a thickness of, for example, 5000Å
Form 7. Here, by applying a voltage of 10 V for 25 minutes at 30 ° C. in a 10% nitric acid solution,
This anodic oxidation is performed. (Fig. 4 (D))

Next, the dense oxide layer 405 is removed and anodization is performed again in an ethylene glycol solution containing tartaric acid to form a dense oxide layer 408. The thickness of this oxide layer 408 is 2000Å. In addition, the gate electrode 409 is determined by this anodic oxidation process. (Fig. 4
(E))

Then, the silicon oxide film 400 is removed by dry etching using the oxide 407 as a mask. Thus, the state shown in FIG. 5A is obtained. In this state, an impurity imparting a conductivity type opposite to that of the impurity injected into the source / drain regions is injected into the peripheral edge of the active layer. Here, boron is implanted in a relatively dose amount of 1 × 10 ¹² to 1 × 10 ¹⁴ . As a result, the peripheral portion of the active layer becomes a weak P type.

After obtaining the state shown in FIG. 5A, the porous oxide layer 407 is selectively etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Then, impurity ions are implanted to form source / drain regions. N here
Phosphorus ions are implanted in order to manufacture a channel thin film transistor. In this step, the source region 410 and the drain region 416 are formed in a self-aligned manner. Further, lightly doped regions 411 and 415 and offset gate regions 412 and 414 are simultaneously formed. The lightly doped regions 411 and 415 are the remaining silicon oxide film 400.
Thus, a portion of the implanted ions are blocked, so that the ion implantation is performed at a lower concentration than the source region 410 and the drain region 416. The offset gate regions 412 and 414 include the gate electrode 4
Oxide layer 408 around 09 serves as a mask and impurity ions are not implanted. (Fig. 5 (B))

Then, a silicon oxide film 417 is formed as an interlayer insulating film.
To a thickness of 6000Å by plasma CVD. Further, a source electrode 418 and a drain electrode 419 are formed through a hole forming process. Here, since the side surface of the end portion of the active layer is formed in a taper shape, the electrode wiring formed on the active layer can be configured so that disconnection does not occur.
That is, since the side surface around the active layer indicated by 420 is formed in a taper shape, various electrode wirings formed above the side surface are formed at a smooth angle, and there is no step disconnection. You can In addition, since the tapered region has a conductivity type opposite to that of the source / drain region, PN is formed between the channel forming region and the source / drain region on the side surface of the active layer during the OFF operation.
A junction is formed and the insulation between the source / drain can be improved. Therefore, the OFF current can be reduced.

A photograph of a cross section of the thin film transistor is shown in FIG. FIG. 6 shows a thin-film active layer and its tapered end portion. Further, FIG. 7 shows a photograph of the thin film transistor shown in this embodiment taken from above. The photograph shown in FIG. 7 shows a fine pattern formed on the substrate. The cross section cut along AA 'in FIG. 7 corresponds to FIG. 5C, and the cross section cut along BB' in FIG. 7 corresponds to FIG.

Finally, the active layer is hydrogenated by heat treatment in a hydrogen atmosphere at 350 ° C. under atmospheric pressure to complete the thin film transistor.

[0052]

EFFECTS OF THE INVENTION By particularly enhancing the crystallinity of the side surface of the active layer, a thin film transistor with a small OFF current can be obtained.

[Brief description of drawings]

1A to 1C are diagrams illustrating a manufacturing process of a thin film transistor described in an example.

FIG. 2 is a diagram showing a schematic configuration of a general thin film transistor.

FIG. 3 is a view showing a method of irradiating an active layer with laser light.

4A to 4C are diagrams illustrating a manufacturing process of a thin film transistor described in an example.

5A to 5C are diagrams illustrating a manufacturing process of a thin film transistor described in an example.

FIG. 6 is a photograph showing a thin film forming a thin film transistor.

FIG. 7 is a photograph showing a fine pattern (thin film transistor) formed on a substrate.

FIG. 8 is a diagram showing a step of forming an active layer.

[Explanation of symbols]

101 ... Glass substrate 102 ... Silicon oxide film (base film) 103 ... Active layer 104 ... Silicon oxide film (Gate insulating film) 105 ... Gate electrode 106 ... Source region 107 ... Channel formation region 108 ... Drain region 109 ... Interlayer insulating film 110 ... Source electrode 111 ... Drain electrode 201 ... Glass substrate 202 ...・ ・ ・ Silicon oxide film 203 ・ ・ ・ Source region 204 ・ ・ ・ Channel formation region 205 ・ ・ ・ Drain electrode 206 ・ ・ ・Gate insulating film 207 ... Gate electrode 208 ... Interlayer insulating film 209 ... Source electrode 210 ... Drain electrode 21 ... Source region 22 ... Channel formation region 23 ... Drain region 400 ... Silicon oxide film (gate insulating film) 401 ... Glass substrate 402 ... Silicon oxide film (base film) 403.・ ・ ・ Silicon film 404 ・ ・ ・ ・ ・ ・ ・ ・ Active layer (crystalline silicon film) 405 ・ ・ ・ ・ ・ ・ Oxide layer (Dense oxide layer) 406 ・ ・ ・Aluminum film 407 ... Oxide layer (porous oxide layer) 408 ... Oxide layer (dense oxide layer) 409 ... Gate electrodes 410 ... Source regions 411, 415 ... Light-doped regions 412, 414 ... Offset Gate region 413 ... Channel formation region 416 ... Drain region 417 ... Interlayer insulating film 418 ... Source electrode 419. ..... Drain electrodes

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-132303 (JP, A) JP-A-4-290443 (JP, A) JP-A-4-340724 (JP, A) JP-A-4- 340725 (JP, A) JP-A-4-116846 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/20

Claims (4)

(57) [Claims] 1. An amorphous silicon film is formed on a substrate having an insulating surface, the amorphous silicon film is crystallized to form a crystalline silicon film, and a resist mask is formed on the crystalline silicon film. Etching the crystalline silicon film while retracting the resist mask by isotropic plasma etching,
A method for manufacturing a semiconductor device, wherein a side surface of the crystalline silicon film is tapered, and the crystalline silicon film is irradiated with laser light or strong light. 2. An amorphous silicon film is formed on a substrate having an insulating surface, the amorphous silicon film is crystallized into a crystalline silicon film, and a resist mask is formed on the crystalline silicon film. Etching the crystalline silicon film while retracting the resist mask by isotropic plasma etching,
A method for manufacturing a semiconductor device, wherein a side surface of the crystalline silicon film is tapered, and a side surface of the crystalline silicon film is irradiated with laser light or strong light. 3. An amorphous silicon film is formed on a substrate having an insulating surface, the amorphous silicon film is crystallized to form a crystalline silicon film, and a resist mask is formed on the crystalline silicon film. Etching the crystalline silicon film while retracting the resist mask by isotropic plasma etching,
A method of manufacturing a semiconductor device, wherein a side surface of the crystalline silicon film is tapered, and the crystalline silicon film is irradiated with laser light or strong light obliquely with respect to the insulating surface . 4. After the amorphous silicon film is formed, crystallization of the amorphous silicon film is promoted at a concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁹ cm ^{−3 in} the amorphous silicon film. the method for manufacturing a metal element introduced, a semiconductor device according to any one of claims 1 to 3 to heat treatment characterized by crystallizing the amorphous silicon film.