JP3374389B2 - LSI test equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI test apparatus, and more particularly to an LSI under test (hereinafter referred to as DUT (Device under t
est). ) Related to the LSI test apparatus capable of arbitrarily performing the cluster allocation.

[0002]

2. Description of the Related Art In a conventional LSI test apparatus, a waveform at a desired timing is generated by using a test pattern or the like, and this waveform is applied to a DUT via a plurality of test pins.
The operation test of the DUT is performed by taking in the output signal from T via the test pin.

Further, for convenience, all the test pins of the LSI test apparatus are classified into a plurality of test pins and managed, and this unit is called a cluster.

FIG. 3 is a plan view showing an arrangement example of test pins of a conventional LSI test apparatus on a test head. For example, it is assumed that the LSI test apparatus shown in FIG. 3 has 512 test pins and one cluster is formed for every 64 pins.

In FIG. 3, "a" is a "cluster 1" composed of the first to 64th pins, and "b" in FIG. 3 is a "cluster 2" composed of the 65th to 128th pins. Three
The middle "C" is a "cluster 3" composed of the 129th pin to the 192nd pin, and the "D" in Fig. 3 is the 193rd pin to the 2nd.
It is a "cluster 4" composed of 56 pins.

Similarly, "e" in FIG. 3 is "cluster 5" composed of the 257th pin to the 320th pin, "in FIG. 3"
“H” is the “cluster 6” composed of the 321st to 384th pins, “T” in FIG. 3 is the “cluster 7” composed of the 385th to 448th pins, and “H” is the Four
"Cluster 8" consisting of 49th to 512th pins
Is.

Further, in the conventional LSI test apparatus, there is a register circuit for setting the number of DUTs, and a cluster is uniquely assigned to each DUT based on the set value of the register circuit. In other words, when the number of DUTs is determined, usable clusters are determined.

FIG. 4 is a table showing the relationship between the number of DUTs and usable clusters. For example, as can be seen from FIG. 4, if the number of DUTs is one, "cluster 1" to "cluster 8" are selected. All are usable.

Further, for example, if the number of DUTs is two, "cluster 1", "cluster 3", "cluster 6" and "cluster 8" are provided in the first DUT and the second DUT is provided.
"Cluster 2", "cluster 4", "cluster 5" and "cluster 7" are assigned to the UT, respectively.

Further, for example, if the number of DUTs is 4, "cluster 1" and "cluster 3" are provided for the first DUT, and "cluster 2" and "cluster 4" are provided for the second DUT. "Cluster 5" and "cluster 7" are assigned to the third DUT, and "cluster 6" and "cluster 8" are assigned to the fourth DUT.

Here, let us consider a case where an operation test of one 64-pin DUT is performed. FIG. 5 is a plan view showing an example of using a cluster for one DUT. In FIG. 5, 1 is a DUT, and DUT 1 is “HA” and “” in FIG.
“Cluster 3” and “cluster 5” shown in “e” are used.

As described above, the test pins are classified into cluster units, and the usable clusters are determined according to the number of DUTs to be subjected to the operation test.

Considering, for example, a case where an operation test of two 64-pin DUTs is performed after the operation test shown in FIG. 5, one DUT is shown in FIG.
The "cluster 3" and "cluster 5" shown in the middle "c" and "e" cannot be used at the same time.

Therefore, for example, a usage example as shown in FIG. 6 can be considered. FIG. 6 is a plan view showing an example of using a cluster for two DUTs, where 1 and 2 are first and second.
Is a DUT.

As can be seen from FIG. 6, the first DUT 1 uses "cluster 1" and "cluster 3" shown in "a" and "c" in FIG. 6, and the second DUT 2 is "b" in FIG. And "cluster 2" and "cluster 4" shown in "d" may be used.

[0016]

However, each cluster is mounted with only the minimum pin electronics board necessary for the operation test of the DUT in terms of cost.
Jumper processing for connecting the DUT and the LSI test apparatus is performed according to the operation test of the DUT.

Therefore, every time the number of DUTs, the number of pins, and the test conditions such as the contents of the operation test change, it is necessary to add or move the pin electronics board and set the jumper process in the cluster. There was a point.

In particular, even if the same operation test is performed in FIGS. 5 and 6, the number of DUTs changes and the cluster to be used changes, and accordingly, “a”, “in FIG. 6”.
There was a problem that all the setting work of "cluster 1", "cluster 2", "cluster 3" and "cluster 4" shown in "b", "c" and "d" would be necessary. Therefore, the problem to be solved by the present invention is to realize an LSI test apparatus capable of arbitrarily performing cluster allocation regardless of the number of DUTs.

[0019]

In order to achieve such a object, according to the first aspect of the present invention, an LSI test apparatus uses a plurality of test pins classified into a plurality of test clusters. A desired cluster setting register circuit for setting an arbitrary cluster and a plurality of cluster fail signals from the plurality of clusters are selected based on the output from the used cluster setting register circuit and the LS to be tested is selected.
And a pass / fail judgment circuit for generating and outputting a fail signal of I.

In order to achieve such a subject, in the second aspect of the present invention, in the first aspect of the present invention, a plurality of LSs under test are tested.
Each I is provided with the use cluster setting register circuit and the pass / fail judgment circuit.

In order to achieve such a subject, in the third aspect of the present invention, in the first aspect of the present invention, the plurality of cluster fail signals are respectively connected to one input terminal of the pass / fail judgment circuit, and the other A plurality of AND circuits to which the outputs from the used cluster setting register circuits are connected respectively, and an OR circuit to which outputs of the plurality of AND circuits are connected and which outputs a fail signal of the LSI under test. It is characterized by being composed of.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the quality decision means of the LSI test apparatus according to the present invention.

In FIG. 1, 3a, 3b, 3c and 3d are 8-bit used cluster setting register circuits, 4a and 4a.
b, 4c and 4d are pass / fail judgment circuits, 5a, 5b, 5c,
Reference numerals 5d, 5e, 5f, 5g and 5h are AND circuits, and 6 is an OR circuit.

Further, 100a, 100b, 100c, 1
00d, 100e, 100f, 100g and 100h are cluster fail signals from "cluster 1" to "cluster 8" indicated by "a" to "h" in FIG.
1b, 101c and 101d are DUT fail signals.

Cluster fail signals 100a-100
h is the logical product circuits 5a to 5h forming the pass / fail judgment circuit 4a.
Is connected to one of the input terminals and a pass / fail judgment circuit 4b
Connected to ~ 4d.

The 8-bit output of the used cluster setting register circuit 3a is connected to the other input terminal of each of the logical product circuits 5a to 5h forming the pass / fail judgment circuit 4a.

Similarly, the used cluster setting register circuit 3
The 8-bit outputs b to 3d are also connected to the pass / fail judgment circuits 4b to 4d.

A logical product circuit 5 constituting the pass / fail judgment circuit 4a
The outputs of a to 5h are respectively connected to the input terminals of the logical sum circuit 6 which constitutes the pass / fail judgment circuit 4a, and the logical sum circuit 6 outputs the fail signal 101a.

Similarly, the pass / fail judgment circuits 4b-4d output fail signals 101b-101d, respectively.

Here, the operation of the quality determining means shown in FIG. 1 will be described. Since the configurations of the pass / fail judgment circuits 4a to 4d are the same, the used cluster setting register circuit 3a and the pass / fail judgment circuit 4a will be described.

In "cluster 1" to "cluster 8" shown in "a" to "h" in FIG. 3, when the operation test in the cluster fails, the cluster fail signal 1 is output.
Set 00a to 100h to "high level".

These cluster fail signals 100a
˜100h is input to one input terminal of each of the AND circuits 5a to 5h.

On the other hand, the used cluster setting register circuit 3a
Is set to the bit corresponding to the cluster used by the DUT.
1 ”is for the bit corresponding to the unused cluster
0 "are set respectively, and the outputs are logical product circuits 5a ...
It is input to the other input terminal of 5h.

In FIG. 1, "a", "b", "c", ""
D ”,“ H ”,“ H ”,“ T ”and“ H ”are shown in FIG.
It is a bit corresponding to "cluster 1" to "cluster 8" shown in "a" to "h".

Therefore, the logical product circuit corresponding to the bit in which "1" of the used cluster setting register circuit 3a is set is in the operating state, and the cluster fail signal input to the logical product circuit is "high level". Alternatively, if it is "low level", the output of the AND circuit becomes "high level" or "low level".

On the other hand, the used cluster setting register circuit 3a
The AND circuit corresponding to the bit for which "0" is set becomes inactive and outputs "low level" regardless of the state of the input cluster fail signal.

Since the outputs of the logical product circuits 5a to 5h are input to the logical sum circuit 6, the logical product circuits 5a to 5h.
If even one of the outputs becomes "high level", the logical sum circuit 6
The DUT fail signal 101a, which is the output of, becomes "high level".

The quality determination circuits 4a to 4d are circuits for determining quality of the first to fourth DUTs to be subjected to the operation test, and the fail signals 101a to 101 are output from the quality determination circuits 4a to 4d.
If d becomes "high level", the DUT is determined to be defective.

For example, FIG. 2 is a plan view showing an example of using a cluster for two DUTs, and in FIG. 2, 1a and 2a are first and second DUTs.

As can be seen from FIG. 2, the first DUT 1a uses "cluster 3" and "cluster 5" shown in "c" and "e" in FIG. 2, and the second DUT 2a is "d" in FIG.
And "cluster 4" and "cluster 6" shown in "f" are used.

In this case, the first DUT 1a is shown in FIG.
Since "cluster 3" and "cluster 5" shown in "H" and "e" are used, the third and fifth bits of the used cluster setting register circuit 3a of the first DUT 1a are set to "
Set to 1 ”and set to“ 00010100 ”.

Similarly, the second DUT 2a is "n" in FIG.
And "cluster 4" and "cluster 6" shown in "f" are used, the fourth and sixth bits of the used cluster setting register circuit 3b of the second DUT 2a are set to "1" and "00101000". Set.

In this state, when the cluster fail signal 100d from "cluster 4" shown by "d" in FIG. 2 becomes "high level", the used cluster setting register circuit 3
Since the fourth bit corresponding to "cluster 4" of a is "0", the fail signal 101a of the first DUT 1a remains "low level".

On the other hand, the used cluster setting register circuit 3b
Since the fourth bit corresponding to "cluster 4" of "1" is "1", the fail signal 101b of the second DUT 2a becomes "high level", and it is determined that the second DUT 2a is defective.

As a result, by selecting the cluster fail signal from the cluster used for the quality judgment of each DUT by using the quality judgment means shown in FIG. 1, the cluster allocation can be arbitrarily performed regardless of the number of DUTs. Will be possible.

For example, even when the operation test of two 64-pin DUTs is performed after the operation test shown in FIG. 5, the cluster is used as shown in FIG. 2 instead of FIG. 6 as in the conventional example. It will be possible.

In particular, if the operation tests of FIG. 5 and FIG. 2 are the same, the setting work of “cluster 3” and “cluster 5” shown in “c” and “e” in FIG. Since it is sufficient to perform the setting work only for the "cluster 4" and "cluster 6" shown in "D" and "F", it is possible to reduce the man-hours of the setting work.

The example of using the cluster for the two DUTs shown in FIG. 2 is merely an example, and any cluster can be used by appropriately setting the used cluster setting register circuits 3a and 3b. .

Further, in FIG. 1, the pass / fail judgment circuit 4a is composed of the logical product circuits 5a to 5h and the logical sum circuit 6,
The configuration is not limited to this as long as it is a configuration for selecting the cluster fail signal from the cluster used for the quality determination of each DUT.

Further, in the embodiments and the like, the test pins are classified into eight clusters for convenience of explanation, but the number is not limited to this.

Although the maximum number of DUTs is four in the example, of course, the number of DUTs is not limited to this. However, it is necessary to add a used cluster setting register circuit and a pass / fail judgment circuit to the pass / fail judgment means according to the number of DUTs.

[0052]

As is apparent from the above description,
The present invention has the following effects. By selecting the cluster fail signal from the cluster used for the pass / fail determination of each DUT using the pass / fail determination means, it is possible to realize an LSI test apparatus capable of arbitrarily performing cluster allocation regardless of the number of DUTs.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a quality determination unit of an LSI test apparatus according to the present invention.

FIG. 2 is a plan view showing an example of using a cluster for two DUTs.

FIG. 3 is a plan view showing an arrangement example of test pins of a conventional LSI test device on a test head.

FIG. 4 is a table showing a relationship between the number of DUTs and usable clusters.

FIG. 5 is a plan view showing a usage example of a cluster for one DUT.

FIG. 6 is a plan view showing an example of using a cluster for two DUTs.

[Explanation of symbols]

1, 1a, 2, 2a DUT 3a, 3b, 3c, 3d Used cluster setting register circuits 4a, 4b, 4c, 4d Pass / fail judgment circuits 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h Logical product circuit 6 Logic Summing circuits 100a, 100b, 100c, 100d, 100e,
100f, 100g, 100h Cluster fail signal 101a, 101b, 101c, 101d Fail signal

Claims (3)

(57) [Claims] 1. In an LSI test apparatus, a used cluster setting register circuit for setting an arbitrary cluster to be used among a plurality of clusters classified and managed for each of a plurality of test pins, and a plurality of clusters from the plurality of clusters. And a pass / fail judgment circuit for selecting the cluster fail signal based on the output from the used cluster setting register circuit and generating and outputting the fail signal of the LSI under test.
Test equipment. 2. The LSI test apparatus according to claim 1, further comprising the use cluster setting register circuit and the pass / fail judgment circuit for each of a plurality of LSIs to be tested. 3. The pass / fail judgment circuit includes a plurality of clusters.
Fail signals are respectively connected to one input terminal and a plurality of AND circuits to which outputs from the use cluster setting register circuits are respectively connected to the other input terminals, and outputs of the plurality of AND circuits are connected to each other. LSI under test
2. The LSI according to claim 1, further comprising an OR circuit for outputting the fail signal of
Test equipment.