JP3373930B2 - Time axis fluctuation correction device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis fluctuation correcting apparatus for correcting a time axis fluctuation of a video signal accompanied by a time axis fluctuation, and more particularly, it shows a phase fluctuation amount changed in one horizontal period of the video signal. The present invention relates to a time axis fluctuation correction device that also corrects velocity errors.

[0002]

2. Description of the Related Art A video signal obtained by demodulating an RF signal read from a video signal recording medium such as a video disk or a video tape has a problem in the case of a disk because of eccentricity or uneven rotation of the disk. In the case of tape, fluctuations in the time axis (time base error) occur due to uneven rotation of the video head. Therefore, the reproducing apparatus for the video signal recording medium is provided with the time axis fluctuation correcting apparatus for correcting the time axis fluctuation.

This time-axis fluctuation correction apparatus is a main time-axis fluctuation correction for one horizontal period (1H) interval, which is performed based on a color burst signal included in a video signal or a horizontal synchronization signal. 1H that cannot be corrected with
It is known to correct the residual phase fluctuation (velocity error) in the inside.

A time-axis variation correction device for performing such velocity error correction is disclosed in, for example, Japanese Patent Laid-Open No. 4-357794.
It is shown in the publication. The time-axis fluctuation correction device disclosed in this publication converts a video signal accompanied by a time-axis fluctuation into digital video data by an A / D converter by a clock pulse according to the time-axis fluctuation and writes it in a memory. At the same time, the main time axis fluctuation correction and the velocity error correction are performed by reading the video data written in the memory with the clock pulse obtained by phase-modulating the reference clock based on the velocity error.

[0005]

However, the time-axis fluctuation correction device of the above-mentioned publication uses a digital signal to calculate the velocity error amount, so that the circuit scale becomes large and a dedicated IC ( It was difficult to realize without development of integrated circuits).

In addition, as the time-axis fluctuation correction, a memory for reading with a reference clock is often used to perform only the main time-axis correction, but such an existing main-only time-axis fluctuation correction is used. If the IC is also used to achieve velocity error correction, the time axis fluctuation correction device described above could not be adopted.

In view of the above-mentioned drawbacks, it is an object of the present invention to achieve velocity error correction with a simple circuit configuration even if an IC for time axis correction of only the main is used. Another object of the present invention is to prevent unnecessary velocity error correction when the character information signal is on-screen when the character information signal has a function of on-screening the character information signal.

[0008]

SUMMARY OF THE INVENTION The present invention is an input video signal.
Velocity indicating the amount of phase fluctuation that changed in one horizontal period
Velocity error signal creating means for creating error signal
And the video signal output from the D / A converter
The velocity error output from the error
Phase modulation circuit that modulates the phase in the opposite phase with the error signal and the reference
A character information product that creates a character information signal in synchronization with a clock
Compose circuit and character information output from the character information creation circuit
Signal and the video signal output from the D / A converter.
A selection switch for selectively supplying the phase modulation circuit;
A control means for controlling the selection switch, and the control means
Character information signal output from the character information generating circuit
Is supplied to the phase modulation circuit.
Phase modulation operation of the phase modulation circuit when the switch is switched.
And a stopping means for stopping the work .

[0009]

[0010]

[Function] The present invention is created using a character font.
The function to on-screen the text information signal
When the character information signal is on-screen
Set the selection switch to the character information signal side, and
At this time, the stop means is operated to make the character information signal
Phase modulation circuit used to perform city error correction
To prevent the phase modulation.

[0011]

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a time axis change suitable for explaining the present invention .
FIG. 1 is a circuit block diagram showing an example of a motion compensation device , 1 is an input terminal to which a video signal obtained by demodulating an RF signal read from a video disk is input, and 2 is an analog input to the input terminal 1. An A / D converter for converting a video signal into digital video data, a memory 3 for temporarily storing the video data, and a memory 4 for absorbing a time-axis fluctuation of the video signal at intervals of one horizontal period (1H). A line memory for delaying the video data read from 3 by 1H, 5
Is a D / A converter for returning the video data read from the line memory 4 to an analog video signal, and 6 is a DC voltage level for the time axis fluctuation amount of the video signal input to the input terminal 1 at 1H intervals. A time-axis fluctuation signal generation circuit that detects a change and generates a time-axis fluctuation signal of a DC voltage level according to the fluctuation amount, 7 is a change in the time-axis fluctuation signal generated from the time-axis fluctuation signal generation circuit 6. A / D which is composed of an oscillator whose oscillation frequency is variable according to which the clock for setting the conversion timing by the A / D converter 2 is generated.
A clock generation circuit, 8 is a reference clock generation circuit that generates a reference clock with crystal oscillation accuracy, and 9 is the memory 3 in synchronization with the clock from the A / D clock generation circuit 7.
Of the time axis fluctuation signal from the time axis fluctuation signal generation circuit 6 is controlled by the memory control circuit 10 for controlling the writing of the time axis fluctuation signal from the reference clock generation circuit 8 and the reading of the memory 3 in synchronization with the reference clock from the reference clock generation circuit 8. The first sample that holds the DC voltage level for 1H at a predetermined timing.
Hold circuit (first S / H circuit), 11 is the first S / H
A second sample and hold circuit (second S / H circuit) 12 which holds the sample and hold output from the circuit 10 for 1H at a predetermined timing, and 12 detects a horizontal synchronizing signal of the video data read from the memory 3. A horizontal sync detection circuit 13 creates a timing pulse for setting the sample timing of the first S / H circuit 10 and the second S / H circuit 11 based on the horizontal sync signal detected by the horizontal sync detection circuit 12. Timing pulse generation circuit, 14 is the first S / H circuit 10 and the second S / H circuit
A difference signal generation circuit for generating a difference signal according to the difference between the sample and hold outputs of the circuit 11, and 15 is a difference signal output from the difference signal generation circuit 14 for the second S / H circuit 11
An integrating circuit for integrating the sample signal at the sample timing interval of 16 and a phase modulating circuit 16 for phase-modulating the video signal output from the D / A converter 5 in the opposite phase by the integrated output from the integrating circuit 15.

Next, the operation of the time-variation compensating apparatus having the above-described structure will be described with reference to the waveform chart showing various waveforms in each circuit of FIG. 1 shown in FIG. When the video signal shown in the waveform (a) (illustrated in FIG. 2) of FIG. 2 is input to the input terminal 1, the video signal is synchronized with the clock generated from the A / D clock generation circuit 7 and the A / D The converter 2 converts the video data into digital video data, and the video data is controlled to be written and read by the memory control circuit 9 and once written to the memory 3 and then read.

Here, the A / D clock generating circuit 7
Uses a color burst signal in the video signal to generate a clock whose oscillation frequency is changed according to the change of the time-axis fluctuation signal generated by the time-axis fluctuation signal generation circuit 6, and the A / D is generated by the clock. The conversion timing by the converter 2 and the writing timing of the memory 3 are set. Therefore, the writing timing of the memory 3 is set to 1 for the video signal that is input to the input terminal 1 and is accompanied by a time base fluctuation.
Synchronized at H intervals.

On the other hand, since the read timing of the memory 3 is synchronized with the reference clock generated from the reference clock generating circuit 8, the time axis fluctuation of the video signal at 1H intervals is absorbed by the memory 3.

The video data read from the memory 3 is delayed by 1H by the line memory 4 and then D
The signal is converted into an analog video signal by the / A converter 5 and input to the phase modulation circuit 16. In this case, as shown in the waveform (b), the video signal input to the phase modulation circuit 16 removes the time-axis fluctuation of 1H interval from the input video signal (waveform (a)), and the memory 3 and the line. Memory 4
Will be delayed by the storage time.

The writing and reading of the line memory 4 and the conversion operation of the D / A converter 5 are performed in synchronization with the reference clock from the reference clock generating circuit 8. Further, when the video signal shown in the waveform (a) of FIG. 2 is input to the input terminal 1, the video signal is input to the time axis fluctuation signal generation circuit 6, and the input video signal has a time interval of 1H. A time axis fluctuation signal whose DC voltage level changes in accordance with the axis fluctuation amount is created by the time axis fluctuation signal creating circuit 6 as shown in the waveform (c) of FIG.

The time base fluctuation signal is the first S / H circuit 1
0 is input and is held for 1H in synchronization with the first pulse of the first predetermined timing generated from the timing pulse generation circuit 13 by the first S / H circuit 10. Further, the sample and hold output from the first S / H circuit 10 is
Timing pulse generation circuit 1 by the second S / H circuit 11
It is held for 1H in synchronism with the second pulse of the second predetermined timing, which is generated from 3.

Here, the timing pulse generating circuit 1
3 creates a first pulse based on the generation timing of the horizontal sync signal detected by the horizontal sync detection circuit 12, and creates a second pulse based on the first pulse, and the first pulse is As shown in the waveform (d), it is matched with the generation timing of the horizontal synchronizing signal of the video signal (1H earlier in synchronization with the video signal of the waveform (b)) in which the time base fluctuation of the 1H interval is corrected by the memory 3. As shown in the waveform (e), the second pulse is set to a timing that rises earlier than the first pulse by the pulse width. Therefore, the first S
The / H circuit 10 generates a first sample-and-hold output having a waveform (f), and the second S / H circuit 11 generates a second sample-and-hold output having a waveform (g).

The first and second sample-and-hold outputs are respectively supplied to the difference signal generating circuit 14, and the difference signal generating circuit 14 calculates the difference between the voltage levels of the outputs as shown in the waveform (h). It is generated as a difference signal. This difference signal temporally coincides with the video signal (waveform (b)) output from the D / A converter 5, and the time axis fluctuation amount of 1H interval is excluded except for the pulse width of the second pulse. The DC voltage level is set accordingly.

The difference signal is integrated by the integrating circuit 15, converted into a velocity signal as shown in waveform (i), and supplied to the phase modulating circuit 16 as a time axis fluctuation signal (velocity error signal) within 1H. .

Therefore, the video signal (waveform (b)) output from the D / A converter 5 is a velocity error signal (waveform (i)) output from the integration circuit 15 by the phase modulation circuit 16. Phase modulation is performed in the opposite phase, and velocity error correction is performed.

Therefore, from the output terminal 17, a video signal (waveform (j)) is derived in which the video signal input to the input terminal 1 has been subjected to time axis fluctuation correction at 1H intervals and velocity error correction.

By the way, the first S / H circuit 10, the second S / H circuit 11, the timing pulse generating circuit 13, the difference signal generating circuit 14 and the integrating circuit 15 of FIG. 1 are the velocity error signals for generating the velocity error signal. Each circuit constituting the creating means and excluding the timing pulse creating circuit 13 can be constructed by using a general-purpose OP amplifier as shown in FIG. 3, for example.

In FIG. 3, the first OP amplifier 20, the capacitor 21, the first switch 22 and the feedback resistors 23 and 24 are provided.
Constitute the first S / H circuit 10, and the second OP amplifier 25,
The capacitor 26 and the second switch 27 form the second S / H circuit 11. The third OP amplifier 28 and the resistors 29, 30, 31, 32 constitute the difference signal generating circuit 14, and the fourth OP amplifier 33, the resistor 34, the capacitor 35 and the third switch 36 constitute the integrating circuit 15. Then, the first switch 22 is closed by the first pulse created by the timing pulse creation circuit 13,
The second switch 27 and the third switch 36 are configured to be closed by the second pulse created by the timing pulse creation circuit 13.

FIG. 4 shows a time axis fluctuation correcting apparatus according to the present invention .
FIG. 1 is a circuit block diagram showing an embodiment, and is a time-axis fluctuation compensation
A function to on-screen the character information signal is added to the primary device.
Has been done. In FIG. 4, the same circuits as those in FIG. 1 have the same drawing numbers.

In FIG. 4, 37 is a character information creating circuit for creating a character information signal synchronized with a reference clock using a character font, and 38 is the character information creating circuit 37.
Selection switch for selecting the character information signal output from the D / A converter 5 and the video signal output from the D / A converter 5 and supplying it to the phase modulation circuit 16, 39 indicates the velocity error signal output from the integration circuit 15 A mute switch 40 that selectively shuts off the supply path supplied to the phase modulation circuit 16 performs setting switching when the character information signal from the character information generation circuit 37 is on-screen, and the selection switch 38 and the mute. The control circuit is composed of a microcomputer that controls switching of the switch 39.

In FIG. 4, when the character information signal is not in the on-screen state, the control circuit 40 switches the selection switch 38 to the state of selecting the video signal from the D / A converter 5, and the mute switch 39 is integrated. Circuit 1
It is possible to switch to a state in which the velocity error signal output from 5 is supplied to the phase modulation circuit 16. Therefore, in this state, the video signal from the D / A converter 5 is phase-modulated in the opposite phase by the velocity error signal from the integration circuit 15 by the phase modulation circuit 16, and the output terminal 17 outputs 1H interval. A video signal whose time axis fluctuation is corrected and velocity error is corrected is derived.

On the other hand, when the character information signal is set to the on-screen state, the control circuit 40 activates the character information creating circuit 37 as shown in the figure, and
The selection switch 38 is switched to a state of selecting the character information signal from the character information creation circuit 37, and the mute switch 39 is switched to a state of not supplying the velocity error signal from the integration circuit 15 to the phase modulation circuit 16. Therefore, in this state, the phase modulation circuit 16
The phase modulation operation is stopped and the character information signal from the character information creating circuit 37 is supplied to the phase modulating circuit 16.

Therefore, from the output terminal 17, the character information signal from the character information generating circuit 37 is directly output, and the character information signal synchronized with the reference clock has an unnecessary phase due to the velocity error signal. No modulation is done.

[0031]

As described above, according to the present invention, according to the present invention, calibration
Character information signals created using the character font are turned on.
Selection switch when adding the function of
When the switch is switched to the character information signal side, the stop means is operated.
Then, the character information signal performs velocity error correction.
Stop the phase modulation by the phase modulation circuit used for
Unnecessary for on-screen character information signal
ON without any velocity error correction being performed.
Disturbance of the character information signal on the screen can be prevented.

[0032]

[Brief description of drawings]

FIG. 1 is a time axis fluctuation correction device suitable for explaining the present invention.
It is a circuit block diagram which shows an example of a device.

FIG. 2 is a waveform diagram showing various waveforms in each circuit of FIG.

FIG. 3 is a circuit diagram showing a specific example of a main circuit of FIG. .

FIG. 4 shows an embodiment of a time axis fluctuation correction device according to the present invention .
It is a circuit block diagram shown .

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 G11B 20/10 G11B 20/18

Claims (2)

(57) [Claims] 1. An input video signal is converted into digital video data by an A / D converter and temporarily stored in a memory, and the video data is read from the memory with a reference clock, and the video data is stored. In a time axis fluctuation correcting device configured to correct time axis fluctuations of a horizontal period interval of a video signal by returning to an analog video signal by a D / A converter, a phase fluctuation amount changed within one horizontal period of an input video signal. And a video signal output from the D / A converter is inverted in phase by a velocity error signal output from the velocity error signal creating unit. A phase modulation circuit that performs phase modulation, a character information creation circuit that creates a character information signal in synchronization with a reference clock, and an output from the character information creation circuit. Selecting a character information signal and a video signal output from the D / A converter and supplying it to the phase modulation circuit, control means for switching the selection switch, and control means for controlling the character. Time axis fluctuation including stop means for stopping the phase modulation operation of the phase modulation circuit when the selection switch is switched to a state in which the character information signal output from the information generation circuit is supplied to the phase modulation circuit Correction device. 2. The velocity error when the selection switch is switched to a state in which a character information signal output from the character information generating circuit by the control means is supplied to the phase modulation circuit. time base fluctuation correcting apparatus according to claim 1, wherein the the velocity error signal from the signal generating means is configured to cut off the supply path for supplying to the phase modulation circuit.