JPH0648618Y2 - PCM playback device - Google Patents

Description

[Detailed Description of the Invention] [Industrial field of application] The present invention relates to a PCM reproducing device, such as a PCM recording device or a PC.
It is suitable for use when reading digital data recorded in an M recording device, digital data memory device, or the like.

[Background technology and its problems]

For example, a PCM that uses a video tape recorder (VTR) to convert a video signal into a PCM (pulse code modulation) signal for recording
In the case of a recording device, in order to reproduce the logical level of each bit of the reproduced PCM signal without error, as shown in FIG.
PCM playback devices have been used conventionally. That is, the reproduction output S1 reproduced from the tape 1 by the head 2 is converted into digital data S2 in the digital reproduction circuit 3. As shown in FIG. 2 (A), since the relative movement of the head 2 with respect to the tape 1 is not constant in the digital data S2, the transition phase of the logic level at the boundary position of each data bit fluctuates and the amplitude of each data bit also changes. It exhibits a so-called eye pattern that fluctuates. Therefore, in order to reproduce the logic level of each data bit without error, it is necessary to sample the logic level of each data bit at the time position with the largest aperture ratio in the eye pattern. Therefore, the digital data S2 is supplied to the D input terminal of the sampling and holding circuit 4 having the D flip-flop circuit structure, and the clock signal S3 reproduced by the clock reproducing circuit 5 is supplied to the clock input terminal SK.

The clock reproducing circuit 5 applies the digital data S2 to the frequency multiplying circuit 6 and rises at each boundary position of each data bit as shown in FIG. 2 (B), and has a frequency doubled output of the digital data S2. It is adapted to obtain the signal S4. This doubled output signal S4 is given as a comparison input to the phase comparison circuit 8 of the PLL circuit 7, and the comparison output is converted to a DC level in the loop filter 9 and then given to the VCO (voltage controlled oscillator) circuit 10. VCO10 frequency output S
5 is given to the phase comparison circuit 8 as a feedback signal, and thus the VCO circuit 10 outputs a frequency 90 ° ahead of the doubled output signal S4 as shown in FIG. 2 (C).
S5 is sent to the phase shifter 11 as the output of the PLL circuit 7.

The phase shifter 11 sends out a clock signal S3 (FIG. 2 (D)) obtained by shifting the frequency output S5 by 90 ° so that its rising occurs at a time position of about 180 ° of the doubled output signal S4. Has been done.

As a result, at the output end of the sampling and holding circuit 4, as shown in FIG.
A reproduction data output signal S6 is obtained which is phase-shifted by 0 ° and is stable in synchronization with the rising edge of the clock signal S3 and has no amplitude fluctuation at a large aperture ratio. It will be sent as the output of the PCM player.

However, according to the configuration of FIG. 1, the digital data S2
To get the clock signal S3 rising at the 180 ° position, the PLL
Since the frequency output S5 of the circuit 7 is configured to shift the phase, a dedicated circuit must be provided to shift the phase, which complicates the configuration and increases the number of elements as a whole. There is a problem that the increased variation of the circuit constants becomes a problem and that a measure for adjusting the variation is required. It is possible to delay the signal by using a delay line, a gate circuit, or the like instead of the phase shifter 11, but there is a similar problem even in this case.

[Purpose of device]

The present invention has been made in consideration of the above points, and by adding a relatively simple structure to the VCO circuit that constitutes the PLL circuit, a frequency output signal 90 ° phase-shifted with respect to the conventional case Is obtained directly from the VCO circuit, thereby eliminating the need to provide a dedicated circuit configuration for phase shifting.

[Outline of device]

In order to achieve such an object, in the present invention, the VCO circuit is composed of an Emitta-Cupple type differential transistor circuit in which a timing capacitor is connected between the emitter and the VCO circuit main body, and the both-end voltage of the timing capacitor is compared and the both-end voltage is compared. A differential circuit that inverts when the levels of A and B are reversed is provided, and the differential output signal of this differential circuit is obtained as a frequency output signal.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. First
As shown in FIG. 3 in which the same parts as those in the figure are designated by the same reference numerals, the PCM reproducing apparatus is designed to directly apply the frequency output signal S11 of the VCO circuit 10 to the clock input terminal of the sampling and holding circuit 4. , The VCO circuit 10 is composed of an emmit-tupple-coupled differential circuit.

The VCO circuit 10 of the emmit-tupple-coupled differential circuit configuration has the principle configuration shown in FIG. In FIG. 4, transistors Q6 and Q7 that operate differentially to each other are provided, and their emitters are connected in common through transistors Q8 and Q9, respectively, and are connected to the constant current source I ₁ . The collectors of transistors Q6 and Q7 are connected to power supply V _CC through transistors Q2 and Q3, respectively. These transistors Q2
And the base of Q3 is connected to the power supply voltage V _{CC by} resistors R3 and R4.
A reference voltage V1 obtained by dividing the voltage is given.

The base of one transistor Q6 is connected to the power supply V _CC through a transistor Q5 having the base connected to the collector of the transistor Q7, and the base of the transistor Q7 is
It is connected to power supply V _CC through transistor Q4 whose base is connected to the collector of transistor Q6. The bases of these transistors Q4 and Q5 are connected to the power supply V _CC through the diode D1 and the resistors R1 and R2, respectively, and thus the transistors Q4 and Q5 are controlled to be always on. Note that I ₂ and I ₃ are constant current sources as driving sources for the transistors Q5 and Q4.

In addition to this, the timing capacitor C1 is connected between the emitters of the transistors Q6 and Q7, and the capacitor C1 is discharged through the transistors Q8 and Q9 in accordance with the change of the voltage across the capacitor C1 and thus the emitter voltage of the transistors Q6 and Q7. The charging operation is performed, and thereby the emitter voltages of the transistors Q6 and Q7 are changed to turn on and off the transistors Q6 and Q7. The on / off cycle of these transistors Q6 and Q7 is the reference voltage connected to the base of transistor Q9.
It is controlled according to the change of the input control voltage V2 applied to the base of the transistor Q8 with respect to V3.

Transistor Q6 is turned off and the transistor Q7 is a Natsuta the ON state at time t ₁ of FIG. 5 in the above configuration. At this time, the transistor Q3 is on and the transistor Q2 is off. Therefore, the base potential V _B6 of the transistor Q6 (Fig. 5 (A)) becomes V _B6 = V _CC -2V _BE -V ₁ (1) through the system of the reference voltage V ₁ , the transistor Q3 and the transistor Q5. Against the base voltage V of transistor Q7
_B7 (Fig. 5 (B)) is the power supply V _CC , diode D1, resistor R
1. Through the system of transistor Q4, V _B7 = V _CC -2V _BE (2). Note that the value of 2V _BE in equation (1) is the sum of the base-emitter voltage V _BE of transistors Q3 and Q5, and (2)
2V _{BE in the} equation is the voltage across the diode V1 and the transistor Q
It is the sum of 4 base emitter voltages V _BE . Therefore, the emitter voltage V _E7 (FIG. 5 (D)) of the transistor Q7 in the ON state is a voltage V _E7 = V _CC -3V _BE ((3) which is the base emitter voltage V _BE lower than the base voltage V _B7 ). ) become. On the other hand, the emitter voltage V _E6 (FIG. 5 (C)) of the transistor Q6 in the off state depends on the charging voltage of the capacitor C1, and at the time t ₁ , V _E6 = V _CC -3V _BE + V ₁ ... As (4), the capacitor C1 is discharged with the discharge current I _1/2 as the time elapses, and thus the capacitor C1 decreases almost linearly.

This state continues for time T ₁ , and at time t ₂ , the emitter voltage V _E6 of the transistor Q6 changes to the base voltage V _B6 (= V _CC
-2V _BE -V ₁ ), when the base emitter voltage V _BE becomes lower (= V _CC -3V _BE -V ₁ ), this transistor Q6
Operates from the off state to the on state. At this time, the emitter voltage V _E6 of the transistor Q6 can be forcibly raised to a voltage lower than the base voltage V _B6 by the base emitter voltage V _BE .
As a result, the emitter voltage V _{E7 of the} transistor Q7 is
Will be raised through 1, transistor Q7
Works off. The transistor Q6 thus turned on turns on the transistor Q2, and the transistor Q7 turned off causes the transistor Q3 to turn off. Therefore, the base potential V _B6 of the transistor Q6 becomes V _B6 = V _CC -2V _BE (5) through the system of the power supply V _CC , the diode D1, the resistor R2 and the transistor Q5, while the base potential V _B of the transistor Q7 is _B7 becomes V _B7 = V _CC -2V _BE -V ₁ (6) through the system of reference voltage V1, transistor Q2 and transistor Q4.

So emitter voltage V of the transistor Q6 at the time t _2
E6 becomes the voltage V _E6 = V _CC -3V _BE ((7)) which is the base emitter voltage V _BE reduced from the base voltage V _B6 (= V _CC -2V _BE ), and thus the potential V _E6 rapidly increases at time t ₂ . To voltage V
That's a rise of ₁ . Therefore, the emitter voltage of the transistor Q7 is increased by the increased amount V ₁ through the capacitor C1 and becomes V _E7 = V _CC -3V _BE + V ₁ (8).

As is clear from comparing equations (5) to (8) with equations (1) to (4), the operating condition at time t ₂ is higher than that at time t ₁ by transistor Q6 and It can be seen that the situation is the same as when the conditions of Q7 were replaced. Therefore, the circuit of FIG. 4 is inverted from the state at time t ₁ at time t ₂ .

In this state, the capacitor C1 continues to discharge with the current I _1/2 through the transistor Q9. Therefore, the emitter voltage V _E7 of the transistor Q7 decreases almost linearly. This state continues for the second T ₁ section, and when the potential V _E7 of the emitter of the transistor Q7 drops from the base potential V _B6 by the base-emitter voltage V _BE at time t ₃ , the transistor Q7 turns on. Thus, transistor Q6 is inverted to the off state in the same manner as described above for time t ₂ , and thus the circuit of FIG. 4 is generally inverted to the same state as described above for time t ₁ .

Similarly, every time time T ₁ elapses, transistor Q6
And Q7 repeat the inversion operation, and thus, for example, the base potential V _B7 of the transistor Q7 is V _CC − when the transistor Q7 is on.
When the high potential of 2V _BE (corresponding to logic “H” level) and the transistor Q7 is turned off V _CC −2V _BE −
This may transmitted as frequency output S5 using to become lower potential of V ₁ (corresponding to a logic "L" level).

By the way, the discharge time T ₁ of the capacitor C1 is And the frequency f ₀ of the frequency output S5 is Can be expressed as

The clock reproducing circuit according to the present invention has a VCO circuit main body 21 having the above-described principle structure, and additionally has a differential circuit 22 having a pair of transistors Q10 and Q11 as shown in FIG. The emitters of the transistors Q10 and Q11 are connected to each other and to the current source I ₄ , and the collectors are connected to the power supply V _CC through resistors R5 and R6, respectively. In addition to this configuration, the base of one transistor Q10 is connected to the emitter of one transistor Q6 of the VCO circuit body 21, and the base of the other transistor Q11 is connected to the emitter of the transistor Q7 of the VCO circuit body 11.

In the above structure, the VCO circuit main body 21 operates in the same manner as described above with reference to FIG. 4 (as shown in FIGS. 7A to 7D corresponding to FIGS. 5A to 5D). ), And accordingly, the transistors Q10 and Q11 of the differential circuit 22 operate as shown in FIGS. 7E and 7F to obtain the frequency output S11 obtained as the potential difference between the collectors thereof.
(Fig. 7 (G)) Frequency output S5 (Fig. 7 (B))
A signal whose phase is shifted by 90 ° can be obtained.

The transistors Q10 and Q11 forming the differential circuit 22 are turned on when the potential applied to the base, that is, the higher one of the emitter potentials V _E6 and V _E7 of the transistors Q6 and Q7,
And the other turns off. Here, as is apparent from FIGS. 7C and 7D, the emitter voltage V _E6 of the transistor Q6 is at the potential V _CC −3V _BE + V ₁ between the times t ₁ and t _2.
From V _CC −3V _BE −V ₁ to V _CC −3V _BE, the emitter voltage V _E7 of the transistor Q7 maintains the potential V _CC −3V _BE, and between the time points t _{2 and} t ₃ , the transistor Q7 is turned on. The emitter voltage V _E7 of the potential is V _CC -3V _BE + V ₁ to V _CC -3V _BE
While decreasing to −V ₁ , the emitter voltage V _{E6 of the} transistor Q6 maintains the potential V _CC −3V _BE .

Follow go-between time t ₁ the first half of the period of the interval T ₁ of the ~t ₂ T _1/2 (time t ₁ ~
t ₁₂ and between), the second half of the section of the section T ₁ of the to time t ₂ no t ₃ T ₁ /
2 (time t _{23 to} t ₃ ), the emitter voltage of transistor Q6
V _E6 is higher than the emitter voltage V _{E7 of} transistor Q7, and therefore transistor Q10 is on and transistor Q10 is on.
11 is turned off.

This time against t ₁ ~t ₂ of the second half of the T _1/2 interval (time t ₁₂ ~t
And between _2), T _1/2 interval (time t ₂ ~ of the first half of the time t ₂ ~t ₃
During t ₂₃ ), the emitter voltage of transistor Q7 is V _E7
Is higher than the emitter voltage V _E6 of the transistor Q6. Therefore, in these sections, the transistor Q11 is turned on and the transistor Q10 is turned off.

When the transistor Q10 or the transistor Q11 is turned on in this manner, the current I ₄ flows through the resistor R5 or R6, so that the collector voltage V _C10 or V _C11 of the transistor Q10 or Q11.
The potential of becomes a low level potential V _CC −I ₄ R5 or V _CC −I ₄ R6, and conversely, if the transistor Q10 or Q11 is turned off, no current flows through the resistor R5 or R6. The collector voltage V _C10 or V _C11 of the transistor Q10 or Q11 becomes the high potential V _CC .

The voltage difference between these collector voltages V _C10 and V _C11 is sent out as an output clock signal S11 as shown in FIG. 6, and the clock input terminal SK of the sampling and holding circuit 4 in FIG.
Given to.

This clock signal S11 is at a low potential -I ₄ R5 corresponding to the logic level "L" at the times t _{1 to} t ₁₂ . And time t
_{At 12} , the potential I ₄ R6 corresponding to the high logic level “H” is transitioned to, and this logic level “H” is maintained during the times t _{12 to} t ₂₃ . Then falling to a logic level "L" low at time t _23, during the time point t ₂₃ ~t ₃ to maintain this level.

Therefore, the clock signal S11 of FIG. 7 (G) is supplied to FIG. 7 (B).
As is clear from comparison with the base voltage V _B7 of VCO (which is the frequency output S5 of VCO circuit body 21 as described above with reference to FIG. 4), VCO circuit body 21
An output clock signal S11 having a rising edge obtained by shifting the rising edge of the frequency output S5 of 90 ° by 90 ° can be obtained from the differential circuit 22.

Incidentally, the delay time T of the output clock signal S11 in FIG.
Expressed _1/2 as the phase φ shifted, become.

As described above, according to the configuration of FIG. 5, by providing the differential circuit 22 having a simple configuration in the VCO circuit main body 21, the signal level transits at a time position where the aperture ratio of the eye pattern of the digital data S2 is sufficiently large. Such a sampling clock signal S3 can be directly sent from the VCO circuit 10 to the sampling and holding circuit 4.

[Effect of device]

As described above, according to the present invention, the clock signal S11 to the sampling and holding circuit 4 can be directly obtained from the VCO circuit 10 at the time position where the reproduced digital data has a large aperture ratio. The phase shifter 11 can be omitted as compared with the configuration described above, and thus the configuration as a whole can be further simplified, and the number of elements can be significantly reduced, so that the PCM reproducing device has less temperature characteristics and variations. Can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional PCM reproducing device, FIG. 2 is a signal waveform diagram for explaining the operation thereof, and FIG. 3 is a block diagram showing an embodiment of the PCM reproducing device according to the present invention.
FIG. 5 is a connection diagram showing the principle configuration of the circuit body of the VCO circuit of FIG. 3, FIG. 5 is a signal waveform diagram used to explain its operation, and FIG.
Fig. 7 is a connection diagram showing the concrete configuration of the VCO circuit of Fig. 3,
The figure is a signal waveform diagram for explaining the operation. 1 ... tape, 2 ... head, 3 ... digital playback circuit, 4 ... sampling hold circuit, 5 ... clock playback circuit, 6 ... doubler circuit, 7 ... PLL circuit, 8 ...
Phase comparator circuit, 9 ... Loop filter, 10 ... VCO circuit, 11 ... Phase shifter.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masamitsu Honma 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni-Inside Co., Ltd. (72) Kazuo Sudo 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo No. Soni-Incorporated (56) References JP-A-53-34449 (JP, A)

Claims (1)

[Scope of utility model registration request] 1. A PLL circuit for generating a sampling clock signal based on the clock data included in the reproduced digital data, and a logic value of each bit of the reproduced digital data received in the clock signal. And a sampling and holding circuit for sampling, wherein the PLL circuit includes a comparator for receiving the clock data as a comparison input, a loop filter, and a VCO circuit, which are sequentially connected in series and the VCO circuit is connected.
The frequency output signal of the circuit is fed back to the phase comparator and the frequency output signal of the VCO circuit is sent as the clock signal to the sample and hold circuit.The VCO circuit connects a timing capacitor between the emitters. Comparing the voltage across the VCO circuit, which has an emitter-coupled differential transistor circuit that generates a frequency signal that is phase-synchronized with the reproduced clock data, and the voltage across the timing capacitor, the voltage level across the voltage is inverted. And a differential circuit that generates a differential output that is phase-shifted by 90 ° with respect to the frequency signal generated in the VCO circuit main body by performing an inverting operation. Is phase-shifted by 90 ° with respect to the frequency signal generated in the VCO circuit body. A PCM reproducing device characterized in that a phase shift of substantially 180 ° is performed by sending out as the above frequency output signal.