JP3366062B2 - Overmold type semiconductor device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to semiconductor devices, and more particularly to overmolded semiconductor devices having a plurality of electronic components or components and methods of making such devices.

[0002]

Semiconductor devices are widely used in various types of electronic products, consumer products, automobiles, integrated circuit cards, and others. One feature of semiconductor devices that is important in many of these applications is that the semiconductor die
A small size semiconductor device, including both an inductor die and a package in which a semiconductor die is housed. Keeping device dimensions as small as possible is important not only for single-chip devices, but also for multi-chip devices. However, the overall size of semiconductor devices tends to increase, or competition for additional I / O results in devices with very fine lead pitches that are difficult for end users to handle. There is hope to do so.

In addition to establishing small device sizes, manufacturers are also driven to maintain the low cost of manufacturing devices. Lead frames are a significant material cost in manufacturing semiconductor devices other than semiconductor dies. For many devices, a customized leadframe must be designed and manufactured for each semiconductor die, which is costly and time consuming.

Although the number of multi-chip semiconductor devices is increasing,
It is a multi-chip device that is a substrate, eg a printed circuit (P
C) This significantly increases the packing density of devices on the substrate. However, one problem that has slowed the industrial acceptance of multi-chip devices is unacceptable manufacturing costs. Many multi-chip devices use expensive ceramic substrates and use additional thin film processes on the semiconductor die, which greatly increases manufacturing costs.

The resin-encapsulated semiconductor device is usually packaged by one of two methods.
In one method, the semiconductor die, or dies, are packaged and then the packages are individually mounted on a circuit board. Alternatively, the semiconductor die, or dies, is mounted directly on the circuit board and then provided with a protective encapsulation structure. The first method has the advantage that the die is sealed and protected by the package. The packaged device is easy to test, handle, and assemble, and the sealed package provides the desired degree of protection to the environment. In contrast, the second method, in which the die are directly connected to the substrate, minimizes the area required by the die and thus allows for very high substrate packing densities. However, with this method, unpackaged dies are not as easy to handle, test, and assemble, and are more susceptible to undesired environmental effects.

In addition to mounting multiple semiconductor dice on a substrate to increase packing density, substrate space can be saved by mounting semiconductor devices vertically. Vertical devices are attractive because they have a very narrow cross-section, allowing for greater circuit board packing density. A typical vertical mount device is a zigzag inline package (ZIP), with leads exiting through the lower edge of the package. The disadvantage of ZIP is that it is a through-hole type package, and the leads can be damaged or bent, which makes the connection to the board unreliable.
Another type of vertical device is a single in-line memory module (SIMM). SIMMs actually consist of multiple individually packaged devices mounted on a substrate with edge connectors for plugging into sockets.

[0007]

The disadvantage of the SIMM board is its size due to the individual package. SIM
Yet another disadvantage of M is the cost associated with the assembly process of packaging each semiconductor die separately.

Therefore, it is an object of the present invention to provide a low-cost, overmolded semiconductor device and a method of manufacturing the same which can realize a multi-chip module without increasing the size of a completely packaged device. It is in.

[0009]

SUMMARY OF THE INVENTION According to one embodiment of the present invention, a semiconductor device is manufactured by providing a substrate having a pattern of conductive traces provided on the surface of the substrate. At least one electronic component or element is interconnected to the pattern of conductive traces, and a package body is overmolded around the electronic component and a first portion of the pattern of conductive traces to form a conductive trace of the conductive traces. The second part of the pattern is exposed. A plurality of solder balls are attached to a portion of the second portion of the conductive trace, and a plurality of edge leads are externally connected to the periphery of the substrate, both the solder balls and the plurality of edge leads. Provides an external electrical connection to the device.

These and other features and advantages will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. It is important to point out that the drawings are not necessarily drawn to scale and that there may be other embodiments of the invention not specifically shown.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIGS. 1, 3 and 4 are sectional views showing the process steps involved in one embodiment of the present invention, and FIG. 4 shows a more completed multichip semiconductor device 10. Figure 2
Shows another process step of FIG. 1, but does not affect the remaining process steps shown in FIGS. As shown in FIG. 1, a substrate 12 is prepared and a conductive trace is formed on a first side of the substrate 12.
s) a first pattern 14 is provided and a second pattern 16 of conductive traces is provided on a second opposite side of the substrate 12. Substrate 12 can be a traditional printed circuit board made of resin-filled fiberglass, such as FR4 or G10 material with conductive trace patterns 14 and 16 on both the top and bottom surfaces of the substrate. Methods of forming a pattern of conductive traces on a PCB substrate are well known in the art. As shown in FIG. 1, the trace 1 on the first (head) surface of the substrate 12
4 is part of trace 1 on the second (bottom) surface of substrate 12
It is connected to a portion of 6 by a plurality of conductive through holes 18 so that each trace can be shared between parts of the device. Typical examples of shared traces include traces used for power and traces used for ground.

As shown in FIG. 1, the semiconductor die 20 is electrically connected to the first pattern 14 of conductive traces by wire bonds 22. However, tape automated bonding (TAB), flip chip /
Other methods of electrical connection such as direct tip attachment, etc. can also be used. The die 20 is also mechanically attached to the substrate 12. Mechanical attachment can be done by using die attach epoxy or any other suitable adhesive medium. After the die 20 is electrically connected to the conductive traces 14, a first molding operation is performed to seal the semiconductor die 20, the wire bonds 22, and the first portion of the first pattern 14 of conductive traces. First package body 2 overmolded with material
4 is formed. The package body 24 is formed by a traditional method, such as transfer molding, where the substrate 12 with the semiconductor die 20 attached is inserted into a mold cavity and the encapsulant is heated to a high temperature and pressure. Sent in. Alternatively, the package body 24 can be formed by injection molding, pour molding, or a "glob-top" process.
In each of these overmolded operations, a sealing material is formed on one side of the substrate 12. The encapsulant material thus covers at least a first portion of the pattern of semiconductor dies, wire bonds, and conductive traces 14.

FIG. 2 illustrates a flip chip attachment method for semiconductor die 20, as previously described. Multiple solder bumps 2
5 is used to attach the die 20 directly to the substrate 12.
When flip chip / direct chip attachment is used, the solder bumps 25 underfill
rfilling) 26 is required prior to the molding operation. The underfilling 26 is typically a polymer adhesive material having a low viscosity. The underfilling 26 completely fills the volume under the die 20. Underfilling 26
Also acts as a stress relieving medium for the die.
Since the underfilling 26 is a stress relieving medium,
The material used for the underfilling should have an appropriate amount of additive material to control the coefficient of thermal expansion of the underfilling 26 so as to minimize the thermal mismatch between the silicon die 20 and the substrate 12. Is. Once the die 20 is flip chip bonded to the substrate 12,
The overmolding operation can be performed as described above.

After the overmolding operation, the semiconductor die 2
0 can be tested functionally via conductive trace 14. Die 20 can be tested using existing test methods and equipment, for example using traditional test probes, pogo-pins, or sockets.

Upon completion of die testing, additional semiconductor die 27, or other electronic component, is mounted to the second side of substrate 12, as shown in FIG. Although FIG. 3 is shown with semiconductor die 27 mounted directly opposite semiconductor die 20, such an arrangement is not necessary for the practice of the invention. Die 27
It can be placed anywhere on the second side of the substrate 12 as long as proper interconnection to the second portion of the conductive trace 16 is possible. As shown in FIG. 3, the semiconductor die 27 is electrically connected to the conductive traces 16 using wire bonds 22.

After the semiconductor die 27 is attached to the second side of the substrate 12 and the appropriate interconnections have been made to the conductive traces 16, a second molding step is performed to produce a second.
Of the package body 28 is formed, where a portion of the conductive traces 16 is exposed to allow electrical access to the semiconductor die 27. The package body 28 is also an overmolded resin package body similar to the package body 24. One difference between the two package bodies is that package body 28 is package body 2
It is smaller than 4. In accordance with the present invention, the lower package body 28 is smaller than the upper package body 24 so that electrical connections can be made to the second portion of the conductive traces on the bottom surface area of the substrate. Should be. When molded, the package body 28 exposes a portion 16 of the conductive traces around the package body 28.

As shown in FIG. 4, a plurality of solder balls 32 are attached and electrically coupled to a portion of the exposed portion of electrically conductive trace 16. The solder balls can also form a thermal path from the device to the next level substrate, eg, a PC substrate. Adhesiveness of the solder ball 32 and the trace 16 and solder wettability (sol
To improve der-wetability, an intermediate conductive layer (not shown) can be added to the exposed portions of the conductive traces. Common materials used to promote adhesion and wettability include gold, copper, and others. The plurality of solder balls 32 should be large enough to reside beyond the package body 28, as shown in FIG. The presence of the solder balls beyond the package body 28 allows the solder balls to be easily bonded to the substrate without interference from the package body.

It should be noted that package bodies 24 and 28 have tapered sidewalls 30. Although not a requirement of the present invention, the sloping sidewalls for the package formed on the bottom side of the device according to the present invention facilitate solder ball attachment. The vertical sidewalls on the package body adjacent the solder ball locations interfere with the manufacturing equipment used to place the solder balls in place. The sloped sidewalls provide more space for accommodating various manufacturing equipment. The sloped sidewalls also help release the package body from the molding tool.

Further, FIG. 4 shows a plurality of edge leads 36 that are selectively mounted externally and electrically coupled to one or both of the upper and lower conductive traces 14 and 16 around the periphery of the substrate 12. It is shown. These leads are commercially available in strip format with standard lead pitch, such as 0.65 mm or 0.5 mm, and are soldered to conductive traces 14 and 16 by a reflow process. After the leads 36 are attached, they can be trimmed and formed into the desired lead shape. In this figure, each lead is a gull-wing shape.
configuration),
Other shapes are also possible, such as J-leaded.

Externally mounted leads are advantageous for several reasons. Instead of customizing the leadframe, which is costly and time consuming for each particular semiconductor die, only the substrate 12 and its associated conductive trace patterns 14 and 16 are customized for a given die. Good. Substrate changes only require simple mask changes with faster cycle times than leadframe design changes, which can be days to weeks. Furthermore, 5 mm x 5 mm to 40 mm x 4
32mm to 520 leads with 0mm body size
The same lead pitch in the range of can be used for semiconductor devices. Another advantage of attaching the outer leads after the molding step is the elimination of the dam bar commonly used in leadframes, thus eliminating the subsequent processing step of removing the dam bar.
In traditional semiconductor devices with metal leadframes, the dam bars flash and bleed the mold compound during the molding operation.
Is a physical barrier between the leads used to control the This dambar must be mechanically removed from the device in the next operation to avoid shorting the leads. Removing dam bars between leads becomes more difficult as lead pitch becomes finer. Therefore, the assembly process can be more easily controlled without the dambar removal step.

FIG. 4 further shows a completed multi-chip semiconductor device 10, where the device has a plurality of conductive traces 40 corresponding in position to solder balls 32 and edge leads 36. Is placed on a traditional substrate 38, such as A plurality of solder balls 32 can be used for power and ground connections. Due to the short distance between the device and the power and ground planes, the inductance and resistance of the device are kept to a minimum.
Thus, the combination of solder balls and edge leads in a device allows for increased I / O without increasing the size of the packaged device.

Testing of semiconductor die 20 in device 10 may be performed at various points in manufacturing. For example,
The die can be functionally tested after the second molding process but before the solder balls are attached. Alternatively, the test can be performed after the solder balls have been attached. However, in order to obtain the highest yielding die for device 10, it is recommended that the lower yielding die be assembled first and the second higher yielding die be assembled. By doing so, the most vulnerable die is identified during the first functional test operation that occurs after the first molding step and before additional components are attached to the other side of the substrate. . Early defect identification eliminates unnecessary manufacturing steps until after the first molding process. For the drawings, see FIG.
And the steps shown in FIG. 4 are eliminated if die 20 is marked as a defective part and subsequent manufacturing costs are avoided. Or if die 27 is die 2
With yields below 0, manufacturing is likely to continue to the second containment stage before defects are identified.

FIG. 5 is a bottom view of the substrate 12. As shown in FIG. 5, and as previously described, the package body 28 does not cover the entire surface area of the second side of the substrate 12, thus exposing a portion 16 of the conductive trace. . The conductive trace 16 has a plurality of solder pads 42 around the package body 28. The solder balls 32 are electrically and physically coupled to the solder pads 42. In addition to solder pads 42, conductive traces 16 also
2 has a plurality of edge connectors 44 on the periphery thereof. Edge leads 36 are electrically and physically coupled to these edge connectors 44. The first (top) side of substrate 12 also has edge connectors as part of the pattern of conductive traces 14. An optional process step is to coat the edge leads with a polymer after they are soldered to the edge connector, which adds mechanical strength to the solder joints and protects them from possible corrosion or leakage between leads. .

The remaining figures, which illustrate yet another embodiment of the present invention, introduce many of the same or similar elements as described above with respect to apparatus 12. Accordingly, like reference numerals indicate the same or corresponding parts throughout the subsequent drawings.

FIG. 6 illustrates another process step leading to another embodiment of the present invention. In this example, the method described in FIG. 1 is used to attach the semiconductor die 20 to the substrate 12
Assemble on top. Once the semiconductor die 20 is mounted on the first side of the substrate 12, wirebonded and overmolded, the substrate 12 is flipped over for mounting the second electronic component. As shown in FIG. 6, passive electronic components 50, such as resistors, diodes, decoupling capacitances, etc., are electrically coupled to the conductive traces 16 by solder joints 51. The electronic component 50 need not be overmolded with the encapsulating material. Parts 50 once
Is attached to the second surface of substrate 12, solder balls 32 and edge leads 36 can be attached to the substrate as described above, forming semiconductor device 52 as shown in FIG.

In another embodiment of the present invention, FIG.
A cross-sectional view of a semiconductor device 60 vertically mounted on a board 62 is shown. The device 60 is processed and assembled by a first step, such as a conventional pad array carrier.
The semiconductor die 64 is mounted and electrically connected to a substrate 66 having a pattern of conductive traces 68 by wire bonds 70. However, other electrical connection methods such as tape automated bonding (TAB), flip chip / direct chip attachment, and others can also be used. After die 64 is electrically connected to conductive traces 68, an overmolding operation is performed to form semiconductor die 6
4, the wire bonds 70, and the first portion 68 of the pattern of conductive traces are covered with the encapsulating material to form the package body 72. The package body 72 is formed by traditional methods such as transfer molding. Alternatively, the package body 72 may also be an injection mold or a pour mold.
g), or "glob-top"
It can be formed by a process. In each of these overmold type operations, a sealing material is formed on one side of the substrate 66. The sealing material is therefore the semiconductor die 64,
Surrounding the wire bonds 70 and at least a first portion 68 of the pattern of conductive traces. However,
Unlike the previous embodiment, only a portion of the conductive traces along one edge of device 60 are exposed, thus providing a single-in-line contact configuration.

After the overmolding operation, the semiconductor die 6
4 can be tested functionally via conductive traces 68.
Once the die is confirmed to be functional, a plurality of solder balls 74 are attached to solder lands 76 that are part of the conductive traces 68. Solder lands 76 are not covered by the package body and are located along the lower edge 78 of substrate 66. Lower edge 78 is P
The PC board 62 is inserted into the C board 62 and has a slot 80 for mounting the semiconductor device 60 in the vertical direction. The PC board 62 has conductive traces 82 corresponding to the positions of the solder balls 74, and the insertion aligns the solder balls 74 with the traces 82. The solder balls 74 are then reflowed to firmly secure the semiconductor device 60 to the PC board 62.

FIG. 9 shows another embodiment in which the semiconductor device 86 essentially has the same elements as the device 60 of FIG. However, the substrate 88 is multilayered so that the conductive traces 68 'can be routed to both sides of the substrate. In the embodiment shown in FIG. 9, a plurality of solder balls 74 ′ are solder lands 7.
It is attached to both sides of the substrate 88 corresponding to the 6'position. The lower edge 78 'of the substrate 88 is the PC board 9
0, where the PC board 90 has solder balls 7
It has a slot 92 with conductive traces 94 aligned with 4 '. Reflowing the solder balls 74 creates symmetrical solder joints on both sides of the substrate 88 to provide firm support for vertically mounted devices.

FIG. 10 shows still another embodiment of the present invention, in which a multichip semiconductor device 98 is vertically mounted on a PC board 90 '. In this embodiment, the semiconductor die 100 is mounted on each side of the substrate 102, thereby increasing the die density per device. Although this embodiment shows only one die per side of the substrate, the invention is not really limited to only one die per side, but multiple semiconductors per side. Can accommodate dice. Therefore, packing density is increased by the multi-chip capability of each device as well as by the vertical mounting of the device. In FIG. 10, the solder joint 10
4 is shown as device 98 already reflowed to PC board 90 '.

FIG. 11 shows another embodiment of the present invention, in which case the semiconductor device 110 can have one of two configurations. The device 110 has alignment pins 112 on both ends of the board 114 for insertion into the PC board 116.
Alternatively, the device 110 can be manufactured without the alignment pins. Without the alignment pins, placement equipment is required to hold the device in place before it is soldered to the substrate. In the embodiment with the alignment pins 112, the PC board 116 has two holes 118 at both ends of the board 114 instead of the slots according to FIGS. These holes 118 are not connected to any conductive trace. A plurality of solder balls 74 'are attached to solder pads (not shown) on the substrate 114. Once pin 1
When 12 is inserted into hole 118, solder ball 74 '
Contact is made with the conductive traces 120 on the C substrate 116. The lower edge of the substrate 114 acts as a travel limiter when the pin 112 is inserted into the hole 118. The solder balls 74 'are then reflowed to the PC board 116, thereby holding the semiconductor device 110 in place.

FIG. 12 shows a seventh embodiment of the present invention,
Edge half vias that are used to mount the device in a vertical direction to the PC board (not shown) (edge Half
vias) 126 is a perspective view of a semiconductor device 124. The half vias 126 are and arranged plating at the bottom edge 128 of the substrate 130 of the device 124. Also shows a plurality of solder balls 132 attached to the half via 126 in FIG. 12.

FIG. 13 shows a vertically arranged device 124 on a PC board 134 having conductive traces 136. The solder balls 132 in FIG.
And reflowed to form a physical and electrical solder connection 138 between the conductive trace 136 and the conductive trace 136. In this embodiment, the PC board 134 does not require slots or holes to mount the device on the PC board.

[0033]

The foregoing description and illustrations show many of the advantages associated with the present invention. In particular, it has been found that the manufacturing process utilizing the PCB substrate approach can be used to manufacture low cost multi-chip semiconductor devices. Further, the footprint of the multi-chip semiconductor device according to the present invention can be made very small by having the semiconductor die or other component at two different levels within the device. The two levels are 2
Produced as a result of two encapsulation operations, the first of which is preferably used to encapsulate the lower yield die, while the second is used to encapsulate the higher yield die. Unlike many traditional multi-chip devices, functional testing can be done prior to the second encapsulation operation.
Therefore, defects can be detected early and the manufacturing costs associated with unnecessary processes are avoided.

Thus, it should be apparent that the present invention provides a multi-chip semiconductor device and method for its manufacture that overcomes the problems associated with prior art devices and methods. Although the present invention has been described and illustrated with respect to particular embodiments thereof, it is not intended that the invention be limited to these described embodiments. Those skilled in the art will recognize that changes and modifications can be made without departing from the spirit of the invention. For example, the pattern of semiconductor traces used on the substrate is not limited by the present invention. The pattern of conductive traces depends on the type and shape of the various semiconductor dies and electronic components used in the device. Further, it is possible to interchange the multilayer substrate with a substrate having plated through holes in either embodiment, or vice versa. Moreover, the present invention is not limited to any particular number or type of semiconductor die used. Also, other components can be used in place of or in addition to the semiconductor die. By way of example, commonly used passive components, including resistors and capacitors, can be used to advantage in the device according to the invention. In addition, materials and methods other than those described for encapsulating the device are possible. Also, solder ball configurations or shapes other than those specifically shown are expected to be suitable in practicing the present invention. In addition, conductive epoxies can be used in place of solder balls to attach the device to the PC board. Furthermore, some of the illustrated embodiments may be inserted into sockets instead of being soldered to the board. Therefore, all such variations and modifications that fall within the scope defined by the appended claims are considered to be included in the present invention.

[Brief description of drawings]

1 is a cross-sectional view showing process steps according to a first embodiment of the present invention for manufacturing a semiconductor device.

FIG. 2 is a cross-sectional view showing a flip-chip / direct-chip attachment method, which is another process step than that shown in FIG.

FIG. 3 is a cross-sectional view showing the remaining process steps according to the first embodiment of the present invention for manufacturing a semiconductor device.

FIG. 4 is a cross-sectional view showing the remaining process steps according to the first embodiment of the present invention for manufacturing a semiconductor device.

5 is a bottom view showing a substrate of the semiconductor device shown in FIG.

FIG. 6 is a cross-sectional view showing process steps according to a second embodiment of the present invention for manufacturing a semiconductor device.

FIG. 7 is a cross-sectional view showing process steps according to a second embodiment of the present invention for manufacturing a semiconductor device.

FIG. 8 is a sectional view showing a vertically mounted semiconductor device having solder balls on one side of a substrate according to a third embodiment of the present invention.

FIG. 9 is a sectional view showing a vertically mounted multilayer substrate semiconductor device having solder balls on both sides of a substrate according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view showing a vertically mounted multi-chip semiconductor device according to a fifth embodiment of the present invention.

FIG. 11 is a front view showing a vertically mounted semiconductor device having an optional alignment pin structure according to a sixth embodiment of the present invention.

FIG. 12 is a perspective view showing a semiconductor device having edge half vias filled with solder balls according to a seventh embodiment of the present invention.

13 is a front view showing a state in which the semiconductor device of FIG. 11 is vertically mounted on a PC board by reflow solder ball bonding.

[Explanation of symbols] 10 Multi-chip semiconductor device 12 substrates 14 First pattern of conductive traces 16 Second pattern of conductive traces 18 Conductive through hole 20 semiconductor die 22 wire bond 24 First package body 25 Solder dump 26 Underfilling 27 Additional semiconductor die 28 Second package body 30 sloping sidewalls 32 solder balls 36 Edge Lead 38 substrates 40 Conductive trace

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identifier FI H01L 25/18 (72) Inventor Michael B. McShane Texas, USA 78750, Split Rail Cove 12407 (56) References JP-A-57-79652 (JP, A) JP-A-1-302757 (JP, A) JP-A-59-161898 (JP, A) Actually open 57-57547 (JP, U) Actually open 1 -118459 (JP, U) Actually open 4-74458 (JP, U) Actually open 1-97560 (JP, U) Actually open 62-87479 (JP, U) (58) Fields investigated (Int.Cl . ^7, DB name) H01L 25/04 H01L 25/065 H01L 25/07 H01L 25/18 H05K 1/14

Claims (5)

(57) [Claims] 1. An overmolded semiconductor device (52) comprising: a substrate (12) having a first pattern of conductive traces (14) on a first side of the substrate; A second pattern of conductive traces (16) on a second side of the substrate, the substrate also having a perimeter; a first pattern of conductive traces on the first side of the substrate A first electronic component (20) electrically connected to and mounted on a second electronic component electrically connected to and mounted on a conductive trace of the second pattern on the second side of the substrate. An electronic component (50), the first electronic component and a first portion of a first pattern of conductive traces on a first surface of the substrate are overmolded to form a conductive trace of the first pattern. The first package body (2 that leaves the second portion exposed)
4) a plurality of solder balls (32) on the second surface of the substrate and a plurality of edge leads (36) externally connected to the outer periphery of the substrate, An overmolded semiconductor device (52), wherein both of the plurality of edge leads provide external electrical connection to the device. 2. An overmolded semiconductor device (10) comprising: a substrate (12) having a first pattern of conductive traces (14) on a first side of the substrate; Having a second pattern of conductive traces (16) on a second side of the substrate, the substrate also having a perimeter; conductive traces of the first pattern on the first side of the substrate A first semiconductor die (20) electrically connected to and mounted to a second semiconductor die electrically connected to and mounted to the conductive traces of the second pattern on the second side of the substrate. A semiconductor die (27), the first semiconductor die and a first portion of the first pattern of conductive traces on a first side of the substrate, overmolded to form the first pattern of conductive traces; Second
The first package body (2
4), overmolding a first portion of the second pattern of conductive traces on the second surface of the second semiconductor die and the substrate to form a second portion of the second pattern of conductive traces. A second package body (28) leaving a portion of the substrate exposed, a plurality of solder balls on the exposed second portion of a second pattern of conductive traces on the second surface of the substrate ( 32), and a plurality of edge leads (36) externally connected to the outer periphery of the substrate, both of the solder balls and the edge leads providing an external electrical connection to the device. What is provided is an overmolded semiconductor device (10). 3. An overmolded semiconductor device (52) comprising: a substrate (12) having a first pattern of conductive traces (14) on a first side of the substrate and Having a second pattern of conductive traces (16) on a second side of the substrate, the substrate also having a perimeter; conductive traces of the first pattern on the first side of the substrate A semiconductor die (20) electrically connected to and mounted to the passive die (50) electrically connected to and mounted to the conductive traces of the second pattern on the second side of the substrate. Overmolding a first portion of the first pattern of conductive traces on the first semiconductor die and the first surface of the substrate to expose a second portion of the first pattern of conductive traces. The first package body to leave 24), a plurality of solder balls (32) on the second surface of the substrate, and a plurality of edge leads (36) externally connected to the outer periphery of the substrate, the solder balls and the solder balls An overmolded semiconductor device (52), characterized in that both of the plurality of edge leads provide external electrical connection to the device. 4. A method of manufacturing an overmolded semiconductor device (10), comprising: a substrate (12), the substrate having a first pattern of conductive traces (14) on a first side of the substrate. ) And on the second side of the substrate a second pattern of conductive traces (1
6), the substrate also having a perimeter, wherein a first semiconductor die (20) having a die surface on a first side of the substrate is mounted and a conductive trace first Electrically coupling to a first pattern, a first semiconductor die and a first surface of the first surface of the substrate.
Overmolding a first portion of the conductive traces of the pattern to form a first package body (24), leaving a second portion of the conductive traces of the first pattern exposed. Testing a first semiconductor die on the substrate, a second semiconductor die (2) on the second side of the substrate.
7) and electrically connecting to the conductive traces of the second pattern, the second semiconductor die and the second on the second side of the substrate.
Overmolding a first portion of the conductive traces of the pattern to form a second package body (28);
Leaving the second portion of the conductive traces of the pattern exposed, a plurality of solder balls () on the second portion of the conductive traces of the second pattern on the second surface of the substrate ( 32) mounting and soldering a plurality of edge leads (36) to the outer periphery of the substrate, both solder balls and the edge leads providing an external electrical connection to the device. A method of manufacturing an overmolded semiconductor device (10), comprising: 5. A method of manufacturing an overmolded semiconductor device (52), comprising: a substrate (12), the substrate having a first pattern of conductive traces (14) on a first side of the substrate. ) And on the second side of the substrate a second pattern of conductive traces (1
6) having a substrate also having a perimeter, mounting a semiconductor die (20) on a first side of the substrate and electrically connecting to conductive traces of a first pattern. Bonding, overmolding a first portion of a conductive trace of a first pattern on a first side of the semiconductor die and the substrate to form a first package body (24); Leaving a second portion of the conductive traces of the pattern exposed, testing a first semiconductor die on the substrate, mounting a passive electronic component (50) on a second side of the substrate And electrically coupling to the second pattern conductive traces, attaching a plurality of solder balls (32) to the second pattern conductive traces on the second side of the substrate, and the substrate Multiple around the Soldering an edge lead (36), wherein both the plurality of solder balls and the plurality of edge leads provide an external electrical connection to the device. A method of manufacturing a mold type semiconductor device (52).