JP3364933B2 - Multilayer printed wiring board and copper foil for inner layer electric circuit - Google Patents

Multilayer printed wiring board and copper foil for inner layer electric circuit

Info

Publication number
JP3364933B2
JP3364933B2 JP26026491A JP26026491A JP3364933B2 JP 3364933 B2 JP3364933 B2 JP 3364933B2 JP 26026491 A JP26026491 A JP 26026491A JP 26026491 A JP26026491 A JP 26026491A JP 3364933 B2 JP3364933 B2 JP 3364933B2
Authority
JP
Japan
Prior art keywords
copper foil
electric circuit
inner layer
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26026491A
Other languages
Japanese (ja)
Other versions
JPH05102656A (en
Inventor
利三郎 吉田
明良 村木
保弘 佐久間
清智 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP26026491A priority Critical patent/JP3364933B2/en
Publication of JPH05102656A publication Critical patent/JPH05102656A/en
Application granted granted Critical
Publication of JP3364933B2 publication Critical patent/JP3364933B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は接着性絶縁層を介し積層
された内層用回路板と外層回路板を備える多層印刷配線
板とその内層電気回路用銅箔に関し、特に内層用回路板
に設けられた銅箔製の電気回路と上記接着製絶縁層との
接着不良が防止できると共に、製造工程途上で適用され
た適宜処理剤が上記内層電気回路と接着性絶縁層との界
面に残留し難い多層印刷配線板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board including an inner layer circuit board and an outer layer circuit board laminated with an adhesive insulating layer interposed therebetween and a copper foil for the inner layer electric circuit, and more particularly to an inner layer circuit board. Adhesive failure between the electric circuit made of copper foil and the insulating layer made of adhesive can be prevented, and an appropriate treating agent applied during the manufacturing process is unlikely to remain at the interface between the electric circuit of the inner layer and the adhesive insulating layer. The present invention relates to a method for manufacturing a multilayer printed wiring board.

【0002】[0002]

【従来の技術】この種の多層印刷配線板は、例えば、図
3から図9に示すような各工程を経て製造されている。
以下その概略を説明すると、図3に示すように銅箔によ
り形成された電気回路を有する複数枚の内層用回路板a
を外層用銅箔a1と共に接着性絶縁層(プリプレグ)b
を介し積層して一体化し、かつ、適宜穿設手段により図
4に示すようなスルーホールcを穿設(ドリリング)し
た後、このスルーホールcの内壁面を銅膜にて覆うため
銅によるスルーホール無電解メッキ処理を施して図5に
示すようなメッキ層dを積層体表面とスルーホールc内
壁面にそれぞれ形成する。
2. Description of the Related Art A multilayer printed wiring board of this type is manufactured through the steps shown in FIGS. 3 to 9, for example.
The outline will be described below. As shown in FIG. 3, a plurality of inner layer circuit boards a having an electric circuit formed of copper foil.
Together with the outer layer copper foil a1 and the adhesive insulating layer (prepreg) b
After the through hole c as shown in FIG. 4 is drilled (drilled) by a suitable drilling means, the inner wall surface of this through hole c is covered with a copper film so that the through hole made of copper is used. A hole electroless plating process is performed to form a plating layer d as shown in FIG. 5 on the surface of the laminate and the inner wall surface of the through hole c.

【0003】次いで、このメッキ層dの面上にスルーホ
ールc周辺の一部と外層電気回路形成部位を除きフォト
レジスト層eをパターン状に形成する(図6参照)と共
に、このフォトレジスト層eから露出する部位に銅・半
田メッキ層fを形成(図7参照)し、かつ、上記フォト
レジスト層eを除去した後、この銅・半田メッキ層fを
マスクにして図8に示すように上記メッキ層d等をエッ
チングにより除去して外層電気回路を形成し、更にこれ
等面上にソルダー・レジスト層gを成膜して図9に示す
ような多層印刷配線板hを製造する方法が採られてい
る。
Next, a photoresist layer e is formed in a pattern on the surface of the plated layer d except for a part around the through hole c and a portion where an outer layer electric circuit is formed (see FIG. 6), and the photoresist layer e is also formed. After forming the copper / solder plating layer f on the exposed portion (see FIG. 7) and removing the photoresist layer e, the copper / solder plating layer f is used as a mask as shown in FIG. The plating layer d and the like are removed by etching to form an outer layer electric circuit, and a solder / resist layer g is further formed on these surfaces to manufacture a multilayer printed wiring board h as shown in FIG. Has been.

【0004】ところで、上記複数枚の内層用回路板aを
接着性絶縁層(プリプレグ)bを介し積層する際、内層
用回路板aに設けられた内層電気回路が表面平滑な銅箔
により構成されているため上記接着性絶縁層bとの接着
強度が不十分となり内層電気回路と接着性絶縁層とが経
時的に剥離し易い欠点があった。
By the way, when the plurality of inner layer circuit boards a are laminated via the adhesive insulating layer (prepreg) b, the inner layer electric circuit provided on the inner layer circuit board a is formed of a copper foil having a smooth surface. Therefore, the adhesive strength with the adhesive insulating layer b is insufficient, and there is a drawback that the inner layer electric circuit and the adhesive insulating layer are easily separated with time.

【0005】このため、従来においては図10の(A)
から(B)に示すように銅箔より成る内層電気回路iの
表面を、例えば、水酸化ナトリウム(NaOH)が15
から25g/l程度溶解されたアルカリ性亜塩素酸ナト
リウム水溶液等で酸化処理してCuOとCu2 Oより成
る針状結晶の酸化膜jを形成し、上記内層電気回路iの
表面を粗面化させて接着性絶縁層bとの接着強度の向上
を図る方法が採られている。
Therefore, in the conventional case, FIG.
To (B), the surface of the inner layer electric circuit i made of copper foil is coated with, for example, sodium hydroxide (NaOH) 15
To 25 g / l dissolved in an alkaline sodium chlorite aqueous solution to form an acicular crystal oxide film j of CuO and Cu 2 O to roughen the surface of the inner layer electric circuit i. A method of improving the adhesive strength with the adhesive insulating layer b.

【0006】[0006]

【発明が解決しようとする課題】このような方法を採る
ことで、全体的には内層電気回路iと接着性絶縁層bの
接着強度の向上が図れる反面、CuOとCu2 Oとで構
成された酸化膜jはアルカリ溶液に対し耐性を有するも
のの酸には比較的容易に溶解されてしまうため、多層印
刷配線板の製造工程途上において図11(A)に示すよ
うにスルーホールcの内壁面から露出する積層面が酸性
の処理剤に触れた場合(例えば上述したスルーホールの
無電解メッキ処理の際、無電解メッキに対する触媒性を
付与するため塩酸酸性のパラジウム・錫水溶液にて処理
するような場合)、その接触部位の酸化膜jが図11
(B)に示すように酸により溶解して上記内層電気回路
iの金属銅が露出され、図12に示すようにピンク色の
リングrがスルーホールcの周縁に沿って形成される”
ハローイング”と称される現象があった。
By adopting such a method, it is possible to improve the adhesive strength between the inner electric circuit i and the adhesive insulating layer b as a whole, but on the other hand, it is composed of CuO and Cu 2 O. The oxide film j has resistance to an alkaline solution but is relatively easily dissolved in acid. Therefore, as shown in FIG. 11A, the inner wall surface of the through hole c is dissolved during the manufacturing process of the multilayer printed wiring board. When the laminated surface exposed from the substrate comes into contact with an acidic treatment agent (for example, in the case of the above-mentioned electroless plating of through holes, it is necessary to treat with a hydrochloric acid-acidic palladium / tin aqueous solution in order to impart catalytic properties to the electroless plating. 11), the oxide film j at the contact site is shown in FIG.
As shown in (B), it is dissolved by an acid to expose the metal copper of the inner layer electric circuit i, and a pink ring r is formed along the periphery of the through hole c as shown in FIG.
There was a phenomenon called "haloing".

【0007】そして、この現象が発生すると図13に示
すようにスルーホールcの内壁面の内層電気回路iと接
着性絶縁層bの界面に空隙sが形成されてしまうためこ
れらの間の接着強度の低下が起こって経時的に剥離し易
くなる問題点があり、かつ、この空隙s内に上記処理剤
が残留し易くなるため多層印刷配線板としての信頼性を
著しく低下させる問題点があった。
When this phenomenon occurs, a void s is formed at the interface between the inner layer electric circuit i on the inner wall surface of the through hole c and the adhesive insulating layer b as shown in FIG. Of the multi-layer printed wiring board is remarkably reduced because the treatment agent is likely to remain in the voids s. .

【0008】このような技術的背景の下において本発明
者等が上記酸化膜jに耐酸性を付与する方法を鋭意研究
したところ、従来法において酸化膜が耐酸性を示さない
原因は酸により容易に溶解されるCuOが上記酸化膜j
中に多量に存在するためで、このCuOの比率を下げ比
較的耐酸性を有するCu2 Oの比率を上げることにより
酸化膜jに耐酸性を付与できること、ミラー指数(11
1)、(110)、(100)の各配向性を持った3種
類の単結晶銅に酸化膜を形成し、X線回折法により測定
したところ(111)、(100)面の単結晶銅ではC
2 Oは確認されず、(100)面(X線回折法では
(200)面が観測される)の単結晶だけにCu2 Oが
確認され、従ってCu結晶の配向面とCu2 Oの生成が
関連すること、従ってCu結晶の配向面を特定の配向面
とすることによりCu2 Oの比率を上げて酸化膜jに耐
酸性を付与できることを見いだし本発明を完成するに至
ったものである。
Under the above technical background, the inventors of the present invention have conducted extensive studies on a method for imparting acid resistance to the oxide film j, and as a result, the reason why the oxide film does not exhibit acid resistance in the conventional method is easily caused by the acid. CuO dissolved in the oxide film
Since it is present in a large amount in the inside, acid resistance can be imparted to the oxide film j by decreasing the ratio of CuO and increasing the ratio of Cu 2 O having relatively acid resistance. Miller index (11
1), (110), and (100) three types of single crystal copper having orientations were each formed with an oxide film and measured by X-ray diffractometry. The (111) and (100) planes of single crystal copper were measured. Then C
u 2 O is not observed, (100) plane (in the X-ray diffraction (200) plane is observed) Cu 2 O was confirmed by a single crystal, and thus the orientation plane of the Cu crystals and Cu 2 O in It has been found that the formation is relevant, and therefore the ratio of Cu 2 O can be increased to impart acid resistance to the oxide film j by making the orientation plane of the Cu crystal a specific orientation plane, and thus the present invention has been completed. is there.

【0009】因みに、従来法における酸化膜中のCu2
OのCuOに対する比(Cu2 O/CuO×100)は
30から40%程度であり、また、上記ハローイングの
発生量(図12中、直径0.35mmのスルーホールc
端縁からの距離Lで示されるリングの幅により表示され
る)は平均で130から150μmであり、数百μmに
なることもあった。
Incidentally, Cu 2 in the oxide film in the conventional method is
The ratio of O to CuO (Cu 2 O / CuO × 100) is about 30 to 40%, and the amount of haloing generated (through hole c having a diameter of 0.35 mm in FIG. 12).
(Indicated by the width of the ring indicated by the distance L from the edge) was 130 to 150 μm on average and could be several hundred μm.

【0010】そこで、本発明の課題とするところは、上
記ハローイングの発生量を極力小さいものとすることに
より内層用回路板に設けられた銅箔製の内層電気回路と
上記接着性絶縁層との接着不良が防止できると共に製造
工程途上で適用された適宜処理剤が上記配線層と接着製
絶縁層との界面に残留し難い多層印刷配線板と、この多
層印刷配線板に使用される内層電気回路用銅箔を提供す
ることにある。
Therefore, an object of the present invention is to reduce the amount of haloing generated as much as possible so that the inner layer electric circuit made of copper foil provided on the inner layer circuit board and the adhesive insulating layer are provided. The multilayer printed wiring board which can prevent the adhesion failure of the above, and the appropriate treatment agent applied during the manufacturing process does not easily remain at the interface between the wiring layer and the adhesive insulating layer, and the inner layer electric wiring used for this multilayer printed wiring board. It is to provide a copper foil for a circuit.

【0011】[0011]

【課題を解決するための手段】すなわち、請求項1記載
の発明は、少なくとも、銅箔により形成された内層電気
回路を有する内層用回路板の前記内層電気回路表面を酸
化処理し、CuOとCu 2 Oからなる酸化膜とする工程
と、前記内層電気回路の酸化処理面に接着性絶縁樹脂層
を介して外層用銅箔を積層する工程と、前記積層体にス
ルーホールを穿設する工程と、前記スルーホール内壁面
を酸性前処理剤で処理する工程と、前記スルーホール内
壁面および外層用銅箔にメッキ層を形成する工程と、外
層用銅箔およびメッキ層の積層体を所定のパターンに形
成し外層電気回路とする工程と、ソルダー・レジスト層
を形成する工程とを行うことで得られる多層印刷配線板
において、ラー指数(200)面のX線回折法による
回折光のピーク強度が、(111)面の回折光のピーク
強度の41%以上である銅箔にて上記内層電気回路を構
成することで、上記酸化処理の際に形成されるCu 2
の比率をCuOより上げ、前記酸性前処理剤による酸化
膜の溶解を防止したことを特徴とする。
That is, according to the invention of claim 1, at least the surface of the inner layer electric circuit of the inner layer circuit board having the inner layer electric circuit formed of a copper foil is acidified.
Process to form oxide film of CuO and Cu 2 O
And an adhesive insulating resin layer on the oxidation treated surface of the inner layer electric circuit.
The step of laminating the outer layer copper foil via the
The step of forming a through hole and the inner wall surface of the through hole
The inside of the through hole with a step of treating the
The process of forming a plating layer on the wall surface and outer layer copper foil, and
Form a layered copper foil and plated layer laminate into a predetermined pattern
Process for forming outer layer electric circuit and solder resist layer
In the multilayer printed wiring board obtained by performing the step of forming the peak intensity of the light diffracted by the mirror index (200) face X-ray diffraction method is 41% of the peak intensity of the diffracted light (111) plane The inner layer electric circuit is constructed with the above copper foil.
By the formation of Cu 2 O formed during the above-mentioned oxidation treatment.
The ratio of CuO is higher than that of CuO and oxidation by the acidic pretreatment agent
It is characterized by preventing dissolution of the film .

【0012】また、請求項2記載の発明は、請求項1記
載の発明を前提とし、上記スルーホール内壁面および外
層用銅箔に形成したメッキ層を無電解メッキ層とした
とを特徴とする。
The invention according to claim 2 is based on the invention according to claim 1, and is based on the inner wall surface and the outside of the through hole.
The plating layer formed on the layer copper foil is an electroless plating layer .

【0013】更に請求項3記載の発明は、請求項1又は
請求項2記載の多層印刷配線板の内層電気回路を構成す
る銅箔において、ミラー指数(200)面のX線回折法
による回折光のピーク強度が、(111)面の回折光の
ピーク強度の41%以上であることを特徴とする。
Further, the invention according to claim 3 is the copper foil constituting the inner layer electric circuit of the multilayer printed wiring board according to claim 1 or 2, wherein the diffracted light of the mirror index (200) plane by the X-ray diffraction method. Is 41% or more of the peak intensity of the diffracted light on the (111) plane.

【0014】このような技術的手段において、CuのX
線回折法によるピーク強度とは回折光のうち最も強度の
大きいものの強度をいい、具体的には入射光線と回折光
の角度で定義される2θを横軸に、回折光の強度を縦軸
に取ってグラフを描き、このグラフ上で最大の高さとな
る強度を測ればよい。そして、Cuの(200)面のX
線回折法による回折光のピーク強度が(111)面の回
折光のピーク強度の41%以上である銅箔は、これを酸
化処理した時CuOに較べてCu2 Oが従来の銅箔より
多く形成され、従って酸化処理されたこの銅箔が無電解
メッキの前処理剤等の酸性の処理剤に触れた場合も、ハ
ローイング現象の発生が抑制され、酸性処理剤の残留が
生じ難い。
In such technical means, Cu X
The peak intensity by the line diffraction method is the intensity of the highest intensity of the diffracted light. Specifically, 2θ defined by the angle between the incident ray and the diffracted ray is on the horizontal axis and the intensity of the diffracted light is on the vertical axis. Just draw a graph, and measure the strength at which the maximum height is reached on this graph. Then, the X of the (200) plane of Cu
The copper foil having a peak intensity of the diffracted light by the line diffraction method of 41% or more of the peak intensity of the diffracted light of the (111) plane has more Cu 2 O than the conventional copper foil when oxidized. Even when the formed and thus oxidized copper foil comes into contact with an acidic treatment agent such as a pretreatment agent for electroless plating, the occurrence of the haloing phenomenon is suppressed, and the acid treatment agent is unlikely to remain.

【0015】請求項2はこのような技術的背景に基づい
てなされたもので、内層電気回路を貫通し、酸性前処理
剤で内壁面を処理されたスルーホールと、この前処理面
に積層された無電解銅メッキ層を有することを特徴と
し、このスルーホール周辺のピンクリングの発生と前処
理剤の残留が抑制される。ここで、酸性前処理剤として
は従来から使用されている塩化パラジウム等がそのまま
使用できる。
A second aspect of the present invention is based on such a technical background. A through hole which penetrates an inner layer electric circuit and whose inner wall surface is treated with an acidic pretreatment agent is laminated on the pretreatment surface. It is characterized by having an electroless copper plating layer, and the generation of pink rings around the through holes and the residual pretreatment agent are suppressed. Here, as the acidic pretreatment agent, conventionally used palladium chloride or the like can be used as it is.

【0016】また、このような技術的手段において、上
記銅箔を酸化処理するための処理液としては、従来同
様、アルカリ性亜塩素酸ナトリウム水溶液やアルカリ性
過硫酸カリ水溶液等がそのま適用でき、また、その処理
方法も従来同様、予め脱脂処理された内層用回路板をこ
の処理液に浸漬することによって行われる。
Further, in such a technical means, as the treatment liquid for oxidizing the copper foil, an alkaline sodium chlorite aqueous solution, an alkaline potassium persulfate aqueous solution or the like can be applied as it is, as before. Similarly to the conventional method, the treatment method is also performed by immersing the inner layer circuit board that has been degreased in advance in this treatment solution.

【0017】尚、上述の酸化処理がなされた内層用回路
板を積層した後における多層印刷配線板の製造工程は任
意であり、例えば、上述した従来法と同様な工程を経て
製造してもよいし、他の工程を経てもよい。また、適用
される内層用回路板についてはその一面側にのみ銅箔を
有するものでもあるいは両面側にそれぞれ配線層を有す
るものでもよく任意である。
Incidentally, the manufacturing process of the multilayer printed wiring board after laminating the inner layer circuit boards subjected to the above-mentioned oxidation treatment is arbitrary, and for example, it may be manufactured through the same steps as the above-mentioned conventional method. However, other steps may be performed. Further, the inner layer circuit board to be applied may be one having a copper foil only on one surface side thereof or one having wiring layers on both surface sides respectively.

【0018】[0018]

【作用】請求項1〜3記載の発明によれば、内層電気回
路を構成する銅箔のミラー指数(200)面のX線回折
法による回折光のピーク強度が(111)面の回折光の
ピーク強度の41%以上であるから、内層電気回路用銅
箔を酸化処理してこの結晶面にはCu2 Oの比率の高い
酸化膜が形成され、酸処理等を施してもハローイング現
象が生じ難い。
According to the present invention, the peak intensity of the light diffracted by the X-ray diffraction method of the mirror index (200) plane of the copper foil forming the inner layer electric circuit is (111) plane. Since the peak strength is 41% or more, the copper foil for the inner layer electric circuit is subjected to an oxidation treatment to form an oxide film having a high Cu 2 O ratio on this crystal face, and the haloing phenomenon occurs even when subjected to an acid treatment or the like. Hard to happen.

【0019】[0019]

【実施例】(実施例1)まず、R=(ミラー指数(20
0)面のX線回折光のピーク強度/(111)面のX線
回折光のピーク強度)×100が47%の銅箔が表裏両
面に貼着されたガラス・エポキシ銅貼積層板(340m
m×510mm×1.6mm)を用い、従来同様、フォ
トエッチング処理により上記銅箔を内層電気回路形状に
パターニングして内層回路板を製造した。
EXAMPLE (Example 1) First, R = (Miller index (20
(0) peak X-ray diffracted light intensity / (111) -face X-ray diffracted light peak intensity) x 100% glass foil / epoxy copper laminated plate (340 m) with a copper foil adhered to both sides
(m × 510 mm × 1.6 mm), the inner layer circuit board was manufactured by patterning the copper foil into the inner layer electric circuit shape by photoetching treatment as in the conventional case.

【0020】次に、ニュウトラル・クリーン68(商
標、シップレー社製)の25%溶液を用い、60℃の条
件で上記内層用回路板の両面側に形成された内層電気回
路を脱脂処理し、かつ、水洗した後、エッチ(Etc
h)746(商標、シップレー社製)を15%及びH2
2 を10%含む処理液を用いて60秒間のソフトエッ
チング処理を施し、かつ水洗し、更に硫酸を主成分とす
る固形酸(44g/l)を用いて酸洗いし、かつ水洗し
た。
Next, using a 25% solution of Neutral Clean 68 (trademark, manufactured by Shipley Co., Ltd.), the inner layer electric circuits formed on both sides of the inner layer circuit board were degreased at 60 ° C., and , After washing with water, Etch (Etc
h) 15% 746 (trademark, manufactured by Shipley) and H 2
A treatment solution containing 10% of O 2 was used for soft etching treatment for 60 seconds, followed by washing with water, further with a solid acid containing sulfuric acid as a main component (44 g / l), and then washing with water.

【0021】この様に前処理された内層用回路板の内層
電気回路を以下の条件で酸化処理し、水洗して内層電気
回路の表面にCu2 OとCuOから成る厚さ1μmの酸
化膜を形成した。 酸化処理液の組成:Na3 PO4 ・12H2 O 17g/l NaOH 31g/l NaClO2 43g/l 処理液温度:80℃ 処理時間:4分30秒
The inner layer electric circuit of the inner layer circuit board thus pretreated is oxidized under the following conditions and washed with water to form an oxide film of Cu 2 O and CuO having a thickness of 1 μm on the surface of the inner layer electric circuit. Formed. Composition of oxidation treatment solution: Na 3 PO 4 · 12H 2 O 17 g / l NaOH 31 g / l NaClO 2 43 g / l Treatment solution temperature: 80 ° C. Treatment time: 4 minutes 30 seconds

【0022】尚、上記酸化膜2の厚みはオージェ分光分
析により0.6μmであることが、Cu2 O/CuO×
100の比率はX線回折装置により177%であること
が分かった。
The thickness of the oxide film 2 is 0.6 μm according to Auger spectroscopic analysis, which means that Cu 2 O / CuO ×
The ratio of 100 was found to be 177% by X-ray diffractometer.

【0023】次いで上記酸化膜2が形成された内層用回
路板を乾燥させた後、複数枚の内層用回路板を外層用銅
箔とともに接着性絶縁層を介して重合し、加熱加圧して
多層印刷配線板を製造した。
Next, after drying the inner layer circuit board having the oxide film 2 formed thereon, a plurality of inner layer circuit boards are polymerized together with the outer layer copper foil through the adhesive insulating layer, and heated and pressed to form a multilayer. A printed wiring board was manufactured.

【0024】そして、図2に示すように、従来と同様に
この多層印刷配線板をドリルにより孔開け加工して直径
0.35mmのスルーホールを形成し、かつ、下記組成
の塩化パラジウム処理液で処理し、無電解銅メッキを施
してスルーホール内壁面と多層印刷配線板表面に20μ
mの銅メッキ層を形成し、更に水洗、酸洗等の処理を施
し、かつ従来同様のフォトレジスト層形成処理、20μ
mの電解銅メッキ処理、エッチング処理、ソルダー・レ
ジスト層形成処理等を経て多層印刷配線板を製造した。
Then, as shown in FIG. 2, this multilayer printed wiring board is drilled in the same manner as in the prior art to form a through hole having a diameter of 0.35 mm, and a palladium chloride treatment liquid having the following composition is used. 20μ on the inner wall surface of the through hole and the surface of the multilayer printed wiring board
m copper plating layer is formed, and further, a treatment such as water washing, pickling, etc. is performed, and a photoresist layer forming treatment similar to the conventional one, 20 μm
m electrolytic copper plating treatment, etching treatment, solder / resist layer formation treatment and the like to produce a multilayer printed wiring board.

【0025】 塩化パラジウム処理液組成: NKM−552A(日鉱メタルプレーティング(株)製) 3.5容量% NKM−552B(日鉱メタルプレーティング(株)製) 1.5容量% NKM−552C(日鉱メタルプレーティング(株)製) 2.7容量% ホルマリン 0.3容量% 処理液温度:30℃ 処理時間:約12分[0025]   Palladium chloride treatment liquid composition:     NKM-552A (manufactured by Nikko Metal Plating Co., Ltd.) 3.5% by volume     NKM-552B (manufactured by Nikko Metal Plating Co., Ltd.) 1.5% by volume     NKM-552C (manufactured by Nikko Metal Plating Co., Ltd.) 2.7% by volume     Formalin 0.3% by volume         Treatment liquid temperature: 30 ° C           Processing time: about 12 minutes

【0026】こうして得られた多層印刷配線板のハロー
イング発生量について測定したところ、ピンクリングの
幅Lの平均値は40μmであった。
When the amount of haloing generated in the thus obtained multilayer printed wiring board was measured, the average value of the pink ring width L was 40 μm.

【0027】(比較例1)R=39%の銅箔を内層回路
用銅箔として使用した他は実施例1と略同様に内層電気
回路の表面に酸化膜2を形成した。酸化膜2のCu2
/CuO×100の比率はX線回折装置により147%
であることが分かった。
(Comparative Example 1) An oxide film 2 was formed on the surface of the inner layer electric circuit in substantially the same manner as in Example 1 except that a copper foil of R = 39% was used as the inner layer copper foil. Cu 2 O of oxide film 2
/ CuO × 100 ratio is 147% by X-ray diffractometer
It turned out that

【0028】また、この内層回路板を使用して実施例1
と略同様多層印刷回路板を製造した。ピンクリングの幅
Lの平均値は59μmであった。
In addition, the inner layer circuit board is used in the first embodiment.
A multilayer printed circuit board was manufactured in substantially the same manner as. The average width L of the pink ring was 59 μm.

【0029】(比較例2)R=32%の銅箔を内層回路
用銅箔として使用した他は実施例1と略同様に内層電気
回路の表面に酸化膜2を形成した。酸化膜2のCu2
/CuO×100の比率はX線回折装置により117%
であることが分かった。
(Comparative Example 2) An oxide film 2 was formed on the surface of the inner layer electric circuit in substantially the same manner as in Example 1 except that a copper foil with R = 32% was used as the copper foil for the inner layer circuit. Cu 2 O of oxide film 2
/ CuO x 100 ratio is 117% by X-ray diffractometer
It turned out that

【0030】また、この内層回路板を使用して実施例1
と略同様多層印刷回路板を製造した。ピンクリングの幅
Lの平均値は76μmであった。
In addition, this inner layer circuit board is used in the first embodiment.
A multilayer printed circuit board was manufactured in substantially the same manner as. The average width L of the pink ring was 76 μm.

【0031】(比較例3)R=24%の銅箔を内層回路
用銅箔として使用した他は実施例1と略同様に内層電気
回路の表面に酸化膜2を形成した。酸化膜2のCu2
/CuO×100の比率はX線回折装置により89%で
あることが分かった。
(Comparative Example 3) An oxide film 2 was formed on the surface of the inner layer electric circuit in substantially the same manner as in Example 1 except that a copper foil with R = 24% was used as the copper foil for the inner layer circuit. Cu 2 O of oxide film 2
The ratio of / CuO × 100 was found to be 89% by X-ray diffractometer.

【0032】また、この内層回路板を使用して実施例1
と略同様多層印刷回路板を製造した。ピンクリングの幅
Lの平均値は94μmであった。
In addition, this inner layer circuit board is used in the first embodiment.
A multilayer printed circuit board was manufactured in substantially the same manner as. The average width L of the pink ring was 94 μm.

【0033】[0033]

【発明の効果】請求項1記載の発明によれば、内層電気
回路用銅箔を酸化処理してこの結晶面にはCu2 Oの比
率の高い酸化膜が形成され、酸処理等を施してもハロー
イング現象が抑制されるから、内層電気回路と接着性絶
縁層との接着不良が防止できると共に内層電気回路と接
着性絶縁層との界面に上記酸処理剤等が残留し難くなる
ため、多層印刷配線板としての信頼性を著しく向上でき
る効果を奏する。
According to the first aspect of the present invention, the copper foil for the inner layer electric circuit is subjected to an oxidation treatment to form an oxide film having a high Cu 2 O ratio on the crystal plane, and the oxidation treatment is performed. Since the haloing phenomenon is also suppressed, the adhesion failure between the inner layer electric circuit and the adhesive insulating layer can be prevented, and at the same time, the acid treatment agent and the like hardly remain at the interface between the inner layer electric circuit and the adhesive insulating layer. This has the effect of significantly improving the reliability of the multilayer printed wiring board.

【0034】また、請求項2記載の発明によれば、スル
ーホール内壁に露出する内層電気回路用銅箔にCu2
の比率の高い酸化膜が形成され、酸処理等を施してもハ
ローイング現象が抑制されるから、内層電気回路と接着
性絶縁層との接着不良が防止してスルーホール周辺の接
着力を向上すると共に内層電気回路と接着性絶縁層との
界面に上記酸処理剤等が残留し難くなるため、多層印刷
配線板としての信頼性を著しく向上できる効果を奏す
る。
According to the second aspect of the invention, Cu 2 O is formed on the copper foil for the inner layer electric circuit exposed on the inner wall of the through hole.
The oxide film with a high ratio is formed, and the haloing phenomenon is suppressed even when subjected to acid treatment, etc., so that the adhesion failure between the inner layer electric circuit and the adhesive insulating layer is prevented and the adhesive strength around the through hole is improved. At the same time, the acid treatment agent and the like are less likely to remain at the interface between the inner layer electric circuit and the adhesive insulating layer, so that the reliability of the multilayer printed wiring board can be significantly improved.

【0035】更に、請求項3記載の発明によれば、この
ような信頼性を向上した多層印刷配線板に使用できる銅
箔が提供されるという効果を奏する。
Further, according to the invention described in claim 3, there is an effect that a copper foil which can be used for such a multilayer printed wiring board having improved reliability is provided.

【0036】[0036]

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例に係る内層用回路板の一部拡大断面図。FIG. 1 is a partially enlarged sectional view of an inner layer circuit board according to an embodiment.

【図2】実施例に係る多層印刷配線板の一部拡大斜視
図。
FIG. 2 is a partially enlarged perspective view of a multilayer printed wiring board according to an embodiment.

【図3】従来の多層印刷配線板の製造工程途上の斜視
図。
FIG. 3 is a perspective view of a conventional multilayer printed wiring board during a manufacturing process.

【図4】従来の多層印刷配線板の製造工程途上の斜視
図。
FIG. 4 is a perspective view in the process of manufacturing a conventional multilayer printed wiring board.

【図5】従来の多層印刷配線板の製造工程途上の斜視
図。
FIG. 5 is a perspective view of a conventional multilayer printed wiring board during a manufacturing process.

【図6】従来の多層印刷配線板の製造工程途上の斜視
図。
FIG. 6 is a perspective view of a conventional multilayer printed wiring board during a manufacturing process.

【図7】従来の多層印刷配線板の製造工程途上の斜視
図。
FIG. 7 is a perspective view of a conventional multilayer printed wiring board during a manufacturing process.

【図8】従来の多層印刷配線板の製造工程途上の斜視
図。
FIG. 8 is a perspective view of a conventional multilayer printed wiring board during a manufacturing process.

【図9】従来の多層印刷配線板の概略斜視図。FIG. 9 is a schematic perspective view of a conventional multilayer printed wiring board.

【図10】図10(A)〜(B)は従来の内層電気回路
表面を酸化処理する工程説明図。
FIG. 10A to FIG. 10B are explanatory views of a process of oxidizing the surface of a conventional inner layer electric circuit.

【図11】図11(A)〜(B)はスルーホール形成後
におれる従来の多層印刷配線板の一部拡大断面図。
11 (A) and 11 (B) are partially enlarged cross-sectional views of a conventional multilayer printed wiring board after formation of through holes.

【図12】スルーホール形成後における従来の多層印刷
配線板の一部拡大斜視図。
FIG. 12 is a partially enlarged perspective view of a conventional multilayer printed wiring board after forming through holes.

【図13】図12のW−W線面の部分断面図。13 is a partial cross-sectional view taken along the line WW of FIG.

【符号の説明】[Explanation of symbols]

1 内層電気回路 2 酸化膜 1 Inner layer electric circuit 2 oxide film

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平3−80595(JP,A) 特開 昭63−119594(JP,A) (58)調査した分野(Int.Cl.7,DB名) H05K 3/10 - 3/46 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-3-80595 (JP, A) JP-A-63-119594 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H05K 3/10-3/46

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】少なくとも、銅箔により形成された内層電
気回路を有する内層用回路板の前記内層電気回路表面を
酸化処理し、CuOとCu 2 Oからなる酸化膜とする工
程と、前記内層電気回路の酸化処理面に接着性絶縁樹脂
層を介して外層用銅箔を積層する工程と、前記積層体に
スルーホールを穿設する工程と、前記スルーホール内壁
面を酸性前処理剤で処理する工程と、前記スルーホール
内壁面および外層用銅箔にメッキ層を形成する工程と、
外層用銅箔およびメッキ層の積層体を所定のパターンに
形成し外層電気回路とする工程と、ソルダー・レジスト
層を形成する工程とを行うことで得られる多層印刷配線
板において、 ラー指数(200)面のX線回折法による回折光のピ
ーク強度が、(111)面の回折光のピーク強度の41
%以上である銅箔にて上記内層電気回路を構成すること
で、上記酸化処理の際に形成されるCu 2 Oの比率をC
uOより上げ、前記酸性前処理剤による酸化膜の溶解を
防止したことを特徴とする多層印刷配線板。
1. At least the surface of an inner layer electric circuit of an inner layer circuit board having an inner layer electric circuit formed of a copper foil.
Oxidation process to form an oxide film consisting of CuO and Cu 2 O
And an adhesive insulating resin on the oxidation treated surface of the inner layer electric circuit.
A step of laminating the outer layer copper foil through the layer, and the laminated body
The step of forming a through hole, and the inner wall of the through hole
The step of treating the surface with an acidic pretreatment agent, and the through hole
A step of forming a plating layer on the inner wall surface and the copper foil for the outer layer,
Laminate the outer layer copper foil and plating layer into a predetermined pattern
Process to form outer layer electric circuit and solder resist
In the multilayer printed wiring board obtained by performing a step of forming a layer, the peak intensity of the light diffracted by the mirror index (200) face X-ray diffraction method is the peak intensity of the diffracted light (111) plane 41
Constituting the above inner layer electric circuit with copper foil whose content is at least%.
The ratio of Cu 2 O formed during the above-mentioned oxidation treatment is C
higher than uO to dissolve the oxide film by the acidic pretreatment agent
A multilayer printed wiring board characterized by being prevented .
【請求項2】上記スルーホール内壁面および外層用銅箔
に形成したメッキ層を無電解メッキ層としたことを特徴
とする請求項1記載の多層印刷配線板。
2. A copper foil for the inner wall surface of the through hole and the outer layer
The multilayer printed wiring board according to claim 1, wherein the plating layer formed on the substrate is an electroless plating layer .
【請求項3】請求項1又は請求項2記載の多層印刷配線
板の内層電気回路を構成する銅箔において、 ミラー指数(200)面のX線回折法による回折光のピ
ーク強度が、(111)面の回折光のピーク強度の41
%以上であることを特徴とする多層印刷配線板の内層電
気回路用銅箔。
3. The copper foil constituting the inner layer electric circuit of the multilayer printed wiring board according to claim 1 or 2, wherein the peak intensity of the diffracted light by the X-ray diffraction method on the Miller index (200) plane is (111). ) Surface of the peak intensity of the diffracted light 41
% Or more, a copper foil for an inner layer electric circuit of a multilayer printed wiring board.
JP26026491A 1991-10-08 1991-10-08 Multilayer printed wiring board and copper foil for inner layer electric circuit Expired - Fee Related JP3364933B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26026491A JP3364933B2 (en) 1991-10-08 1991-10-08 Multilayer printed wiring board and copper foil for inner layer electric circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26026491A JP3364933B2 (en) 1991-10-08 1991-10-08 Multilayer printed wiring board and copper foil for inner layer electric circuit

Publications (2)

Publication Number Publication Date
JPH05102656A JPH05102656A (en) 1993-04-23
JP3364933B2 true JP3364933B2 (en) 2003-01-08

Family

ID=17345639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26026491A Expired - Fee Related JP3364933B2 (en) 1991-10-08 1991-10-08 Multilayer printed wiring board and copper foil for inner layer electric circuit

Country Status (1)

Country Link
JP (1) JP3364933B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5387034B2 (en) 2009-02-20 2014-01-15 大日本印刷株式会社 Conductive substrate
JP6569545B2 (en) * 2016-01-27 2019-09-04 住友金属鉱山株式会社 Thick film copper electrode or wiring and method for forming the same

Also Published As

Publication number Publication date
JPH05102656A (en) 1993-04-23

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