JP3362982B2 - Drive control circuit for brushless motor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a brushless motor for detecting the rotor position of a brushless motor having a plurality of phase coils, accurately determining the timing of energization to each coil, and controlling the rotational speed of the rotor. The present invention relates to a drive control circuit.

[0002]

2. Description of the Related Art Conventionally, for example, in a three-phase coil brushless motor, the induced voltage of each phase of the three-phase coil is passed through an integrator and the phase thereof is delayed, and the neutral point voltage of the motor is compared to determine the rotor. Is used as a position detection signal for each coil to energize each coil. However, with the above means,
There is a problem that the induced voltage cannot be detected when the motor rotates at low speed.

Therefore, the neutral point voltage is converted into a waveform that changes stepwise based on a predetermined clock pulse, and the neutral point voltage is compared with the original neutral point voltage to obtain the neutral point voltage. It has been proposed to determine the polarity of the slope of the point voltage and to determine the peak position of the neutral point voltage (for example, see Japanese Patent Laid-Open No. 5-199595).

According to this, since the peak position can be determined only by the neutral point voltage without using the induced voltage, the rotor position can be recognized regardless of whether the rotation speed is low or high and the stability is stable. Can drive a brushless motor.

[0005]

However, the brushless motor applied in the above-mentioned prior art is premised to be rotated at a constant speed regardless of whether the rotation speed is low or high. While the operation is in progress, drive control can be performed without any problem. For example, when the supply voltage is PWM controlled (pulse width control) to change the rotation speed, noise corresponding to the duty and frequency of the supply voltage is generated. It occurs at the neutral point voltage (see FIG. 4).

Therefore, in addition to the true plus side peak points (points a and c in FIG. 4A) and minus side peak points (points b and d in FIG. 4A) of the neutral point voltage, noise is also present. Of the noise (points e and f in FIG. 4C) exist, and the peak point of this noise (points e and f in FIG. 4C) may be mistakenly recognized as a true peak point. That is, as shown in FIG. 4C, the polarity of the slope changes (changes from positive to negative or from negative to positive) in one mountain caused by noise, and this change point is a peak (true peak point). ).

Such erroneous recognition causes so-called step-out of the motor, which causes a problem that the speed control of the brushless motor cannot be performed.

In consideration of the above facts, the present invention can surely detect the rotor position based on the neutral point voltage even if the rotational speed of the brushless motor is controlled to be changeable, thereby performing stable speed control. It is an object to obtain a drive control circuit for a brushless motor that can be used.

[0009]

According to a first aspect of the present invention, there is provided a clock pulse generating means for generating a clock pulse having a frequency sufficiently higher than the frequency of the neutral point voltage of a brushless motor having a plurality of phase coils. Voltage conversion means for performing a sample hold operation based on a first timing signal formed by dividing a clock pulse, and converting the neutral point voltage into a stepwise neutral point voltage waveform that is stepwise changed; Comparison means for comparing the stepwise neutral point voltage waveform and the neutral point voltage and outputting the comparison result as a data signal, and for outputting the first timing signal and for holding operation of the voltage converting means. Timing signal generating means for outputting a second timing signal for reading the data signal, and inputting the second timing signal,
A logic circuit that holds the state of the data signal at the time of inputting the second timing signal, an energization control circuit that controls energization to each phase based on a signal output from the logic circuit, and an energization control circuit The voltage control circuit for controlling the rotation speed of the rotor by changing the duty of the voltage to be supplied and at least the circuit before the step-like neutral point voltage is generated by the voltage converting means are interposed between the voltage control circuit and the brush.
In the frequency band of the neutral point voltage of theless motor, this neutral point
The duty control of the nth order or more so that the pressure phase does not shift
Outputs the neutral point voltage by cutting the frequency noise
In series with the low-pass filter
Connected and output from the low pass filter
The point voltage is input and output from the low pass filter.
The nth order (n is a natural number) included in the neutral point voltage
The noise of frequencies below the
And a band elimination filter that outputs pressure .

According to a second aspect of the present invention, there is provided a clock pulse generating means for generating a clock pulse having a frequency sufficiently higher than the frequency of the neutral point voltage of the brushless motor having a plurality of phase coils, and the rising edge of the clock pulse. Timing signal generating means for generating a first timing signal having a pulse width having a pulse width and a second timing signal having a pulse width between the falling edges of the clock pulse;
Voltage conversion means for converting the neutral point voltage into a stepwise neutral point voltage waveform in which the neutral point voltage is stepwise changed by holding the neutral point voltage at the hold timing of the first timing signal constant; Comparing means for comparing the neutral point voltage and the stepped neutral point voltage and outputting the comparison result as a data signal, and the state of the data signal at the rise of the second timing signal are as follows. Logic circuit that holds the timing signal until the rising edge, an energization control circuit that controls energization to each phase based on the signal output from the logic circuit, and the duty of the voltage supplied by the energization control circuit is changed. by a voltage control circuit for controlling the rotational speed of the rotor is interposed in the circuit of the previously generated said stepped neutral point voltage by at least the voltage conversion unit, a brush The frequency band of the neutral point voltage of Sumota
Then, if the phase of the neutral point voltage is not shifted,
Cut the noise of the duty control frequency
A low-pass filter that outputs a characteristic point voltage;
From the low pass filter connected in series with the filter
The neutral point voltage output is input and the low pass voltage is input.
The n included in the neutral point voltage output from the filter.
(N is a natural number) Individually cuts noise of frequencies below the order
And band elimination that outputs the neutral voltage
And a filter .

According to a third aspect of the present invention, in the invention according to the first or second aspect, they are connected in series with each other.
And individually cut noise of different frequencies
Is provided with a plurality of the band elimination filters
It is characterized in that that.

[0012]

[0013]

According to the invention described in claim 1 or 2,
A stepwise neutral point voltage is generated by periodically holding the neutral point voltage value based on a predetermined clock signal, and a region that can reliably detect the difference from the neutral point voltage of the base is defined. The polarity of the slope of the neutral point voltage is judged based on the comparison result in (1) and the peak point is detected. At this time, Bruno size b in the neutral point voltage caused by the duty control. Where the book
In the invention, at least the voltage conversion means causes the step-like neutral point to
A low-pass filter is inserted in the circuit before the voltage is generated.
Existence Input the neutral voltage to this low-pass filter
To be done. The neutral voltage is input to the low pass filter
As a result, the data of the nth order or more, which does not shift the phase of the neutral point voltage,
The noise of the duty control frequency is cut. According to
The neutral point voltage output from the low pass filter is
Noise of the above duty control frequencies is cut
However, the phase of the frequency that must not be out of phase is retained.
It Then, in this way, the duty control frequency of the nth order or more
The neutral voltage with some noise cut is
Output to the low-pass filter in series.
Input to the filtered band elimination filter. B
The neutral point voltage output from the -pass filter is
The low pass filter is input to the termination filter.
The above n included in the neutral point voltage that is not cut by the
(N is a natural number) Noise of frequencies below the order is individually cut
Is output. In this way, noise generated in the neutral point voltage due to duty control is
By the pass filter and band elimination filter
To be removed Ri, polarity changes other than the true peak point (inversion) or without inconvenience be shifted in phase neutral point voltage can be reliably detect true peak point.

According to the third aspect of the invention, a plurality of balls are provided.
Band elimination filters connected in series with each other.
The neutral point voltage output from the low pass filter is
Pass multiple band elimination filters
Noises of different frequencies contained in the neutral point voltage are
It is cut by the band elimination filter.

[0015]

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a common end of each coil of a three-phase coil 19 of a brushless device and a common end of three detection resistors R connected in parallel to each coil of the three-phase coil 19 are differential amplifiers. is input to the 1 4, so that the the difference is output (neutral point voltage VMN).

The neutral point voltage V _MN is applied to each of the transistors T _{UH to} T _WH , T of the three-phase inverter circuit 18 for driving the motor.
It is adapted to be utilized as a signal for obtaining the base signal of the _UL through T _WL.

[0018] That is, as shown in FIG. 2, the three-phase coils 19, the induced voltage E _U, E _V, E _W are generated. For each of these induced voltages, the timing of energizing the brushless motor is at the position indicated by the circle.

As a means for detecting the position of this mark, the positive / negative peak value position of the neutral point voltage V _MN is used. Square waveform output P _SMN that detects the peak value position of this neutral point voltage V _MN
As an input signal of the three-phase ring counter circuit 17, each of the transistors T _{UH to} T U of the three-phase inverter circuit 18 is
_Produces the base signal of _WL .

The PWM signal generator 22 of the PWM control section 20 is connected to the three-phase ring counter circuit 17. From the PWM signal generator 22, the voltage supplied to each coil of the brushless motor can be duty-controlled based on the operation of the operation unit (not shown) of the PWM control unit 20.

The detection method of the square wave output P _SMN indicating the positive and negative peak value positions of the neutral point voltage V _MN will be described below.

FIG. 3 shows concrete waveforms of respective parts for detecting the neutral point voltage V _MN .

The voltage controlled oscillator circuit 11 has a neutral point voltage V
_MN is input via the peak hold circuit 10 and outputs a pulse signal of frequency f ₀ which changes according to the amplitude of the neutral point voltage. The voltage controlled oscillator circuit 11 is
It is connected to the ring counter circuit 12 and supplies the pulse signal of the frequency f ₀ to the ring counter circuit 12.
In the ring counter circuit 12, the supplied pulse signal is used as a clock signal, the clock signal is frequency-divided,
A timing signal f _a having a pulse width of two cycles of the clock signal is generated.

Further, the neutral point voltage V _MN signal is input to the sample and hold circuit 3 of FIG. 1 through the filter circuit 24 which is a feature of the present invention. Filter circuit 2
4, noise included in the neutral point voltage V _MN (see FIG. 4 (B))
The waveform (see FIG. 4A) from which the reference (see) is removed is output. This noise is caused by the duty control of the voltage by the PWM control unit, and details of these will be described later.

As shown in FIG. 1, the timing signal f _a of the ring counter circuit 12 is input to the sample and hold circuit 13 as _a logic signal,
When the timing signal f _a is 1 (H), the neutral point voltage V _MN
The voltage value of is sampled (detected) and stored in the capacitor.
Further, when the timing signal f _a becomes 0 (L), the electric charge accumulated in the capacitor is held to hold (hold) the voltage value at the time of sampling (detection).

Staircase deformation neutral point voltage V _SMN obtained here
The signal and the neutral-point voltage signal V _MN are adapted to be compared by the comparator 16. As a result of this comparison, the signal P _VSMN output from the comparator 16 (hereinafter _{referred to} as the unstable stabilization pulse signal P _VSMN ) is as follows when the timing signal f _a output from the sample and hold circuit 13 is 1 (H).
Since the neutral point voltage V _MN and the stepwise modified neutral point voltage V _{SM N} of the sample-and-hold circuit 13 have the same value, the indefinite stable pulse output P _VSMN of the comparator 16 is in an indefinite state and repeats 1 and 0 like noise. .

However, the sample and hold circuit 13
When the timing signal f _a at 0 is 0 (L), the step-deformed neutral point voltage V _SMN of the sample-and-hold circuit always shows a value larger or smaller than the neutral point voltage V _MN. The indefinite stable pulse output P _VSMN of 1 generates a stable output at 1, 0.

The range in which the stable indefinite stable pulse output P _VSMN is obtained is the 0 (L) section of the timing signal f _a having the pulse width between the rising _edges of the clock signal output from the ring counter circuit 12, that is, the sample. This is a section in which the AND-hold circuit 13 is in the hold operation.

The sample and hold circuit 13
Anxiety of the comparator 16 while holding operation
Constant pulse output P_VSMNTiming signal to read the status of
Issue f _b1The ring counter circuit 12 is a D flip-flop.
Outputs to rop 15. This timing signal f
_b1Ring counter circuit 12 is sample and hole
Timing signal f output to the drive circuit 13_a0
Since the pulse rises in the section (L), the D
The flop 15 has an unstable power supply during the hold operation.
Loose output P_VSMNThe state of can be adopted.

At this time, the unstable stable pulse output P _VSMN of the comparator 16 is input to the D terminal of the D flip-flop 15, and the timing signal f _b2 is _supplied to the D flip-flop 15.
The square wave output P _SMN is output from the D flip-flop 15.

This square wave output P _SMN is the comparator 1
If the unstable stable pulse output of 6 is stable 1, the square wave output P _SMN of the D flip-flop 15 is 1, and the unstable stable pulse output of the comparator 16 is stable 0 when the timing signal f _b2 rises. Thus, the square wave output P _SMN of the D flip-flop is zero.

For this reason, the rising and falling of the square wave output P _SMN of the D flip-flop 15 changing to 1 or 0 are the positive and negative peak values of the neutral point voltage V _MN , which is exactly the same as for the brushless motor. The energization timing is shown.

Here, the configuration of the filter circuit 24 before the neutral point voltage V _MN is input to the sample and hold circuit 13 will be described.

As shown in FIG. 5, the filter circuit 24 is composed of three independent filters 26, 28 and 30.

The filter 26 at the front stage is called a Bessel type filter and has a function as a so-called low-pass filter. The input neutral point voltage V _MN is connected to the plus side input terminal of the OP amplifier 36 via the resistors 32 and 34. Between the resistor 34 and the input terminal of the OP amplifier 36 on the side of the plume is grounded via a capacitor 38 (potential; 1/2 of the battery).
) Has been. The negative input terminal of the OP amplifier 36 is connected to the output terminal of the OP amplifier 36, and the output terminal of the OP amplifier 36 is connected to the resistor 32 and the resistor 3 via a capacitor 40.
It is connected between 4 and. The signal output from the output terminal of the OP amplifier 36 is supplied to the connection terminal 44 connected to the middle filter 28 via the resistor 42. The resistor 42 and the connection terminal 44 are grounded via a capacitor 46.

The filters 28 and 30 in the middle stage and the latter stage are T
Type filter, which has a function as a so-called band elimination filter. Since these have the same circuit configuration, the description of the configuration of the filter 28 in the middle stage will be omitted by describing the configuration of the filter 28 in the middle stage.

The signal line connected to the connection terminal 44 is branched, resistors 48 and 50 are connected in series, capacitors 52 and 54 are connected in series, and are connected to the positive side input terminal of the first OP amplifier 56. ing. The minus side input end of the first OP amplifier 56 is connected to the output end, and this output end is grounded via the resistors 58 and 60. The signal output from the output terminal of the first OP amplifier 56 is supplied to the connection terminal 62 to which the filter 30 in the subsequent stage is connected.

A second OP is provided between the resistor 58 and the resistor 60.
It is connected to the plus side input terminal of the amplifier 64. The negative side input terminal of the second OP amplifier 64 is connected to the output terminal, is connected between the resistor 48 and the resistor 50 via the capacitor 66, and is connected to the capacitor 52 and the capacitor via the resistor 68. And 54.

Here, in the filter 26 in the preceding stage, about 3K
When the frequency exceeds Hz, the signal begins to be attenuated, and the signal of 50 KHz or more is almost cut. Further, in the middle filter 28, a signal near 10 KHz is cut. Further, in the latter filter 30,
The signal near KHz is cut.

As shown in FIG. 6A, the respective filters 26, 28 and 30 are combined, and the filter circuit 24 as a whole has a filter having the characteristics shown in FIG. 6B. . At this time, since the cut frequency by the filter 26 is set to 30 to 50 KHz, the phase of the neutral point voltage V _MN can be maintained up to 400 Hz. This 400 Hz corresponds to the maximum frequency of the neutral point voltage V _MN at the maximum value of the rated voltage of the brushless motor applied in this embodiment, and as a result, the neutral point voltage V _MN by passing through the filter circuit 24.
The phase shift of is prevented. Also, 10KHz and 20KHz that cannot be cut to eliminate this phase shift.
The frequency bands of the
0) It is configured to cut.

That is, by passing through the filter circuit 24, the frequency band of every 10 KHz to 10 KHz of the signal of the neutral point voltage V _MN is cut. Such a specific frequency band is f = 1 / 2πCR
The value of each resistor and capacitor can be determined by setting the frequency f to be cut from the relational expression of (C: capacitor capacity, R: resistance value).

The circuit of this embodiment is based on the PWM signal generator 22.
The PWM frequency of is set to 10 KHz,
Due to the duty control of the voltage by the M signal generator 22,
Noise at every 10 KHz as shown in FIG. 7A is generated, and this noise causes the noise as shown in FIG. 4B. Therefore, the filter circuit 24 cuts the signal in the frequency band of 10 KHz to cut the noise of 10 KHz (states of FIGS. 7A to 7B). As a result, the neutral point voltage V _MN passing through the filter circuit 24 is
The sawtooth-shaped noise has been removed to form a triangular wave, and the polarity does not change between the true peak points.

The operation of this embodiment will be described below. First,
When the base signals of the transistors T _{UH to} T _WL of the three-phase inverter circuit 18 are generated by being controlled by the three-phase ring counter 17, current flows through each coil of the three-phase coil 19 and the brushless motor rotates.

[0044] Here, the differential amplifier 1 4, and the common ends of each coil of the three-phase coils 19 of the brushless over data, three detection resistor R connected in parallel to each coil of the three-phase coil 19
The difference (neutral point voltage VMN) from the common end of the peak hold circuit 10 and the filter circuit 24 is input.

The peak hold circuit 10 obtains the amplitude of the neutral point voltage V _MN , and the voltage controlled oscillator circuit 11 generates the clock signal f ₀ having a frequency proportional to the neutral point voltage V _MN . The ring counter circuit 12 generates _a timing signal f _a and a timing signal f _b1 based on the generated clock signal f ₀ , and the timing signal f _a is applied as a logic signal of the sample and hold circuit 13. To the sample-and-hold circuit 13, the neutral point voltage V _MN from which the noise output from the filter circuit 24 is removed is input as data.

[0046] That is, the neutral point voltage VMN output from the differential amplifier 1 4, the duty control of the voltage by the PWM signal generator 22, with a saw-like noise as shown in FIG. 4 (B) Since the waveform is output, the detection of the peak by the sample and hold circuit 13 is hindered. Therefore, by removing this noise by the filter circuit 24, the normal neutral point voltage VMN (see FIG. 4A) can be supplied to the sample and hold circuit 13.

In the sample and hold circuit 13,
Timing signal f which is a Zick signal _aBased on the stairs
State neutral point voltage V_SMNIs created, this is the comparator
16 neutral voltage V_MNBy comparing with
Output is clearly set to either "0" or "1"
It can be divided into a region to be defined and a region to be indeterminate.

The output result of the comparator 16 is input to the D flip-flop 15 as a data signal.

On the other hand, the timing signal f _b1 is used as a clock signal for the D flip-flop 15.

As a result, the D flip-flop 15 outputs a square wave signal P _{SMN which} is inverted at every true peak of the neutral point voltage V _MN , and based on this a current is supplied to each coil of the three-phase coil 19. Control of. Note that an error α or β occurs in the drawing (FIG. 3) between the inversion timing of the square wave signal P _SMN and the true peak position of the neutral point voltage V _MN , which is due to the clock signal f. _This can be solved by setting the frequency of ₀ to be much higher than the frequency of the neutral point voltage V _MN , and since it is a stationary error based on the clock signal f ₀ , it may be adjusted by calculation.

According to the present embodiment, even if the current increases due to an increase in load on the brushless motor and the neutral point voltage waveform is distorted by the armature reaction, the brushless motor is always placed at a place where the positive and negative points of the neutral point voltage are high. Since the current can flow to the motor, the motor efficiency is always the best, and even if the motor rotation speed changes, the current is supplied to the motor at a place where the positive / negative of the neutral point voltage is high, so that the motor efficiency is good.

This is because the neutral point voltage V _MN always appears even when the brushless motor is rotating at a very low rotation speed, so that its peak value can be detected. For example, when the integral filter is used, the low speed rotation occurs. It is possible to solve the problem that the rotor position cannot be detected.

Further, in this embodiment, the PWM signal generator 22 can freely change the rotational speed of the brushless motor during drive by controlling the duty of the supply voltage, and the neutral point generated by this duty control can be obtained. Since the noise of the voltage V _MN is removed by the filter circuit 24, the true peak of the neutral point voltage V _MN can be stably detected. Therefore, even if the rotation speed of the brushless motor changes, it is possible to have a predetermined torque without losing step-out from the low speed region to the high speed region.

Further, the filter circuit 24 is divided into three stages,
The filter 26 (low-pass filter) in the front stage reliably holds the phase of the frequency (400 Hz or less) that should not be out of phase, and the frequency band (10 KHz, 20 KHz) that could not be cut by this filter 26 in the middle stage and the latter stage. Since the filters 28 and 30 (band elimination filters) individually cut, the phase shift of the neutral point voltage V _MN that occurs when the frequency band of 10 KHz or higher where noise is generated is simply removed by the low pass filter is prevented. can do.

[0055]

As described above, the drive control circuit for a brushless motor according to the present invention can reliably detect the rotor position based on the neutral point voltage even when the rotation speed of the brushless motor is changed. It has an excellent effect that stable speed control can be performed.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a drive control circuit of a brushless motor according to an embodiment.

FIG. 2 is a time chart showing the operating principle of a brushless motor.

FIG. 3 is a time chart for rotor position detection based on a neutral point voltage.

4A is a normal neutral voltage characteristic diagram, FIG. 4B is a characteristic diagram of a neutral point voltage having noise caused by duty control, and FIG. 4C is a partially enlarged view of FIG. 4B. .

FIG. 5 is a circuit diagram for killing the inside of the filter circuit according to the present embodiment.

FIG. 6A is a schematic characteristic diagram showing a cut region in each filter, and FIG. 6B is a gain and phase shift characteristic diagram resulting from synthesis of each filter.

FIG. 7A is a characteristic diagram showing an attenuation change occurring in the neutral point voltage before the filter is attached, and FIG. 7B is a characteristic diagram showing an attenuation change in the neutral point voltage after the filter is attached.

[Explanation of symbols]

11 Voltage controlled oscillator 12 ring counter circuit 13 sample and hall circuit 15 D flip-flop circuit 16 comparator 19 three-phase coil 22 PWM signal generator 24 Filter circuit 26 (Low-pass) filter 28, 30 (band elimination) filter

Claims (3)

(57) [Claims] 1. A clock pulse generating means for generating a clock pulse having a frequency sufficiently higher than the frequency of the neutral point voltage of a brushless motor having a multi-phase coil, and a first pulse pulse dividing means for dividing the clock pulse. Voltage conversion means for performing a sample hold operation based on a timing signal and converting the neutral point voltage into a stepwise neutral point voltage waveform in which the neutral point voltage is stepwise changed; the stepwise neutral point voltage waveform and the neutral point voltage And a second timing signal for outputting the comparison result as a data signal and outputting the first timing signal and reading the data signal during the hold operation of the voltage conversion means. And a timing signal generating means for outputting the second timing signal and holding the state of the data signal at the time of inputting the second timing signal. Rotation circuit for controlling the rotation of the rotor by changing the duty of the voltage supplied by the energization control circuit and the energization control circuit that controls energization to each phase based on the signal output from the logic circuit. And a voltage control circuit for controlling the brushless motor, which is interposed at least in the circuit before the step-like neutral point voltage is generated by the voltage converting means .
In the frequency band of the neutral point voltage, there is no phase of this neutral point voltage.
Of the duty control frequency above the n-th order
Low pass buffer that cuts noise and outputs the neutral voltage
Filter and the low pass filter connected in series with the low pass filter.
The neutral point voltage output from the filter is input,
Included in the neutral point voltage output from the low-pass filter.
The noise of a frequency less than the n (n is a natural number)
Band Eli which outputs the neutral voltage by cutting it individually.
A drive control circuit for a brushless motor having a termination filter . 2. A clock pulse generating means for generating a clock pulse having a frequency sufficiently higher than the frequency of the neutral point voltage of a brushless motor having a multi-phase coil, and a pulse width having a pulse width between rising edges of the clock pulse. Timing signal generating means for generating a first timing signal having the first timing signal and a second timing signal having a pulse width between the falling edges of the clock pulse; and the neutral point voltage at the hold timing of the first timing signal. By holding the voltage at a constant level, the neutral point voltage is converted into a stepwise neutral point voltage waveform in which the neutral point voltage is changed stepwise, and the neutral point voltage and the stepwise neutral point voltage are compared. Comparing means for outputting the comparison result as a data signal, and a state of the data signal at the rise of the second timing signal as a second A logic circuit that holds the minging signal until the rising edge, an energization control circuit that controls energization to each phase based on a signal output from the logic circuit, and a duty of the voltage supplied by the energization control circuit is changed. Thus, the voltage control circuit for controlling the rotation speed of the rotor and at least the circuit before the step-like neutral point voltage is generated by the voltage converting means are interposed , and
In the frequency band of the neutral point voltage, there is no phase of this neutral point voltage.
Of the duty control frequency above the n-th order
Low pass buffer that cuts noise and outputs the neutral voltage
Filter and the low pass filter connected in series with the low pass filter.
The neutral point voltage output from the filter is input,
Included in the neutral point voltage output from the low-pass filter.
The noise of a frequency less than the n (n is a natural number)
Band Eli which outputs the neutral voltage by cutting it individually.
A drive control circuit for a brushless motor having a termination filter . 3. Connected in series and having different frequencies.
Multiple band eliminators that individually cut noise
A drive control circuit of the brushless motor of claim 1 or claim 2, wherein further comprising a Deployment filter.