JP3228775B2 - Device for detecting rotor position of brushless motor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotor position detecting device for a brushless motor which can reliably detect a rotor position without a magnetic sensor even when the brushless motor rotates at a low speed.

[0002]

2. Description of the Related Art In a conventional brushless motor drive system without a magnetic sensor, an induced voltage of each phase of a three-phase coil of the motor is passed through an integrator to delay the phase and a neutral point voltage of the motor. There is a method in which a current is supplied to a three-phase coil of the motor by using the signal as a position detection signal of the rotor by comparison. According to this method, since the integrator is used, the induced voltage cannot be detected when the brushless motor is rotating at a low speed.

As a conventional driving method without a magnetic sensor, Japanese Patent Application Laid-Open No. 57-160385 will be described as a representative example. FIG.
Is a position detection circuit diagram showing the configuration of this conventional system,
Subsequent to the input terminals a ₃ , b ₃ , c ₃ of each phase of the position detection circuit connected to the three-phase coil, filter circuits a ₄ , b ₄ , c ₄ corresponding to each phase are provided, respectively. Each filter circuit has a first-order integrating filter and a first-order differentiating circuit by resistors 7 and 8 and capacitors 9 and 10, respectively. Further, in the conventional method, the filter circuit a ₄ neutral voltage combining circuit 12 synthesizes the output voltage of all phases of the to c _4, and the filter circuit a ₄ to c ₄ of the output voltage and neutral-point voltage synthesis and a rotor position detection circuit comprising a comparator a ₅ to c ₅ Metropolitan for comparing the output voltage of the circuit 12.
Then, has a three-phase coil is treated by the logic processing circuit 6 the output voltage of the comparator a ₅ to c ₅ so energized in response to the rotor position.

FIG. 10 shows the state of the signal voltage of each part for illustrating this method. Motor phase terminal voltages V _U , V _V , V _W
What has become π / 2 (rad) triangular delay the phase by integral filter _{■ V u dt, ■ V v} dt, ■ V w d
t. It delayed this phase _{■ V u dt, ■ V v} dt,
■ create a voltage n obtained by combining the _{V w dt, ■ V u dt} , ■ V v
P _u , P _v , and P _w are obtained by comparing dt, ΔV _w dt and n with the comparators a _{5 to} c ₅ , respectively. This P _U ,
P _V and P _W are input to the logic processing circuit 6 to obtain base signals T _{UH to} T _WL of motor drive transistors. Here, the above-mentioned integration filter has characteristics shown in FIG. At this time, when the frequencies of the terminal voltages V _U , V _V , V _W are the smallest,
In other words, by always using the motor rotational speed and ωa the frequency when the minimum has a phase delay of - [pi] / 2 (rad) _{■ V u dt, ■ V v} dt, to obtain a ■ V _w dt You can. However, it is known that the gain of the integrating filter is reduced by several dB at the frequency of ωa. This is particularly the case where the rotational speed of the brushless motor is very slow, there is a disadvantage that of course the value of the terminal voltage of the integrating filter for even small _{■ V u dt, ■ V v} dt, ■ V w dt can not be detected.

[0005]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a rotor position detecting device for a brushless motor which can reliably detect the rotor position even when the brushless motor is rotating at a low speed and can operate the brushless motor. This is the first problem. The second problem is that even if the number of rotations of the brushless motor increases, the rotor position can be accurately detected,
An object of the present invention is to provide a rotor position detecting device that does not delay the energization timing of a brushless motor.

[0006]

According to the present invention, there is provided a brushless motor rotor for detecting a rotor position using a neutral point voltage (V _MN ) of each phase coil of the brushless motor. A position detecting device, wherein a duty ratio of a frequency higher than a frequency of the neutral point voltage (V _MN ) is 5;
A pulse generating means for generating a 0% pulse output (f _o ) , and a pulse width signal (f _a , f _a) having a pulse width between a rising edge and a falling edge of the clock signal using the pulse output (f _o ) as a clock signal . a pulse width signal generating means for generating f _b1), and the pulse width signals between the falling (f _b1) and data and pulse output of the pulse generating means (f _o)
With the pulse width signal (f _b1 ) as a clock signal .
The pulse width signal occurs with a first logic circuit for generating and falling between the pulse width signal of one period delay of the clock signal (f _b2), the neutral point voltage (V _MN) an analog input signal the rise between the pulse width signal means as a logic signal, detects the analog input signal when the said logic signal is "1", and the logic signal is "0" Tsu Na
Holds the voltage value of the neutral voltage (V _MN) when the sample-and generating the neutral point voltage (V _MN) stepwise altered allowed stage deformation neutral voltage (V _MSN) A hold circuit compares the step deformed neutral point voltage (V _MSN ) with the neutral point voltage (V _MN ) and has an indefinite portion and a stable portion.
Undefined stable pulse output to the comparing means for generating (P _VSMN), the indefinite stable pulse output of the comparator means (P _VSMN)
, And the stable portion of the unstable pulse output (P _VSMN ) is changed from “0” to “0” by using the pulse width signal (f _b2 ) between the falling _{edge of} one cycle delayed generated by the first logic circuit as a clock signal. stand for change "to" 0 "1" and "1
A second logic circuit for generating a square wave output ( _PSMN ) having rising and falling _edges, and a rotor position detecting device for a brushless motor. Even when the brushless motor is running at a very low speed, the neutral point voltage always appears, and its peak value can be detected.

Further, in order to solve the second problem, the present invention keeps the peak value of the neutral point voltage whose frequency and voltage value change due to a change in the rotation speed of the brushless motor, instead of the pulse generating means. A peak hold means for generating a voltage output (V _PH ) corresponding to the number of rotations of the motor, and a voltage controlled oscillator for oscillating a pulse output having a duty ratio of 50% at a frequency varying according to the voltage output value of the peak hold means Means for detecting the rotor position of a brushless motor according to claim 1. Since the output voltage of the peak holding means is a peak value detection signal which always holds the peak value of the neutral point voltage, there is no deviation between the output signal and the peak value of the neutral point voltage.

[0008]

First Embodiment A first embodiment will be described with reference to the configuration circuit of FIG. 1 and the operation timing charts of FIGS. 2 and 3. In FIG. 1, a neutral point voltage VMN is obtained by detecting a difference between the neutral point voltage of the three-phase coil 9 of the brushless motor and the neutral point voltage of three detection resistors R connected in parallel to each three-phase coil 9.
(Hereinafter simply referred to as neutral point voltage), the transistors TUH to TWH, TUL of the three-phase inverter circuit 8 for driving the motor.
.About.TWL. First, induced voltages EU, EV, and EW shown in FIG. 2 are generated in the three-phase coil 9. In each of the induced voltages, the energization timing to the brushless motor is at a position indicated by a mark. As means for detecting the position of the circle, the position of the positive or negative peak value of the neutral point voltage VMN is detected. The base signal of each of the transistors TUH to TWL of the three-phase inverter circuit 8 is generated by using the square wave output PSMN, which detects the peak value position of the neutral point voltage VMN, as the input signal of the three-phase ring counter circuit 7 . . Hereinafter, a method of detecting a square wave output PSMN indicating the positive / negative peak value position of the neutral point voltage VMN will be described.

FIG. 3 shows waveforms at various points in the detection method. Duty ratio 50 which is f _o from the astable oscillation circuit 1
% Pulse output is generated. The pulse output f _o as the clock signal of the ring counter circuit 2 to obtain a rise between the pulse width signals f _a and falling between the pulse width signal f _b1 of the clock signal. Further, this f _{b1 is set} to D (data) of the D flip-flop 4, and the pulse output f _{o is set} to CK.
In addition to the (clock) signal, a falling edge pulse width signal f _b2 delayed by one cycle is obtained. Following these pulse signals f _o, and the pulse width signal f _a, f _bi, will with respect to the f _b2.

Firstly when the rise between the pulse width signals f _a of the neutral point voltage V _MN signal of FIG. 3 is an analog signal of the sample-and-hold circuit 3 in FIG. 1 the ring counter circuit 2 is set to logic signals, sample-and-hold Rise pulse width signal f _a inputted as logic signal to circuit 3
Is "1"("High"), the voltage value of the neutral point voltage _VMN as an analog input signal is sampled (detected), stored in a capacitor, and the rising pulse width signal fa as a logic signal is set to "0". (“Low”), the sample (detection) is performed by holding the charge stored in the capacitor.
The voltage value at the time of holding is held.

Now, when the comparator 6 compares the obtained staircase deformed neutral point voltage VSMN signal with the neutral point voltage signal VMN, an unstable pulse output PVSMN shown in FIG. 3 is obtained. In the unstable pulse output PVSMN, the output of the pulse width signal fa between the sample (detection) section of the sample and hold circuit 3, that is, the rising edge of the ring counter circuit 2, is "1""(Hi
gh) ”, the neutral point voltage VMN and the step-modified neutral point voltage VSMN of the sample-and-hold circuit 3 have the same value, so that the unstable stable pulse output PVSMN of the comparator 6 is in an indeterminate state and noise is“ 1 ”. Repeat “0.” However, the hold of the sample and hold circuit 3
In the section, that is, the pulse width signal fa between rising edges of the ring counter 2
Is "0"("LOW"), the step-and-hold neutral point voltage VSMN of the sample and hold circuit is the neutral point voltage VMN
On the other hand, since it always indicates a large or small value, the unstable pulse output PVSMN of the comparator 6 generates a stable output of "1" and "0". Therefore, the comparator 6 outputs
An indefinite portion where "1" and "0" are repeated
Indefinite stable pulse output with stable part at “0”
A force (P _VSMN ) is generated. Range From boss was indefinite stable pulse output PVSMN is obtained is a section of "1" of falling between pulse width signal fb1 of the ring counter circuit 2 ( "High"). Based on this falling pulse width signal fb1, D
The falling pulse width signal fb2 delayed by one cycle generated by the flip-flop 4 is "1" of the falling pulse width signal fb1.
(“High”) (at the center of “0” (LOW) of the fa signal), ie, 1 within the stable range of “1” or “0” of the unstable pulse output PVSMN of the comparator 6.
The pulse width signal fb2 between the falling edges of the period delay rises.

At this time, the unstable pulse output P _VSMN of the comparator 6 is used as D (data) of the D flip-flop 5, and the pulse width output f _b2 between the falling _edges of the D flip-flop 4 which is delayed by one cycle is output from the D flip-flop 5. CK (clock) to obtain its square wave output P _SMN . This square wave output P _SMN is the unstable pulse output P _{VSMN of the} comparator 6
Can be determined whether the output is stable "1" or "0". In other words, when the pulse width signal f _b2 between the falling edges of the D flip-flop 4 with a one-cycle delay rises and the unstable pulse output of the comparator 6 is stable “1”, the square wave output P _SMN of the D flip-flop 5 becomes “1”, the falling _edge pulse width signal f _b2 delayed by one cycle of the D flip-flop 4
At the time of rising, if the unstable stable pulse output of the comparator 6 is stable “0”, the square wave output P _SMN of the D flip-flop is “0”. When the square wave output P _SMN of the D flip-flop 5 changes to “1” or “0”, the rise and fall fall near the positive and negative peak values of the neutral point voltage V _MN (the pulse of the reference astable oscillation circuit). is approaching the peak value of the neutral voltage V _MN higher frequency of the output f _o), which is exactly indicate the energization timing of the brushless motor.

The effect of the first embodiment is that, even if the current increases due to an increase in the load on the brushless motor and the neutral point voltage waveform is distorted by the armature reaction, the neutral point voltage always has a high positive / negative point. Since the current can flow to the brushless motor, the motor efficiency is always the best.Even if the motor rotation speed fluctuates, the motor timing is high because the current flows at the place where the neutral point voltage is positive or negative. There are things. This is because even when the brushless motor is rotating at a very low speed, the neutral point voltage V _MN always appears and its peak value can be detected. This solves the problem that the rotor position cannot be detected at the time.

[0014]

[Problems of the first embodiment and the object of the second embodiment rotor position detecting apparatus of the first embodiment, between the rising and astable dividing the pulse output f _o of the oscillator circuit for outputting a fixed frequency is to obtain a pulse width signal f _a, the a rising pulse to pulse width signal f _a neutral point voltage V _MN then sample and hold generates phase deformation neutral voltage V _SMN, the magnitude relationship between the neutral point voltage , A square wave output P _SMN that changes between “1” and “0” near the peak value of the neutral point voltage V _MN is detected. Although the frequency of the pulse output f _o of this time the astable oscillating circuit is fixed for the neutral point voltage V _MN
And the square wave output P _SMN produce _a one-cycle deviation α ° of the rising pulse width signal fa as shown in FIG.
Frequency f of the neutral point voltage V _MN when the brushless motor is operating at a high rotational (N _HS) is high, the neutral voltage V _MN when the brushless motor is operating at low rotational frequency f ( N _LS ) becomes lower.

In FIG. 3, when the frequency of the neutral point voltage V _MN is f (N _HS ), the pulse width signal fa between rising edges inputted to the sample-and-hold circuit has _a fixed frequency. The difference between the peak value of the point voltage V _MN and the square wave output P _SMN for peak value detection is α ° _HS (α ° _HS is the electrical angle of one cycle f (N _HS ) of the neutral point voltage V _MN. Angle when 360 °). In FIG. 3, the difference between the peak value of the neutral point voltage V _MN and the square wave output P _SMN for detecting the peak value is α.
° _LS (α ° _LS is one cycle f of the neutral point voltage V _MN
(Angle when (N _LS ) is 360 electrical degrees). At this time, whether the rotation of the brushless motor is high or low,
Frequency of rise between pulse width signal f _a to be inputted alpha ° _HS for a fixed, alpha ° _LS time t alpha ° _HS, the t alpha ° _LS is the same.

The frequency of the neutral point voltage V _MN is f
(N _HS ) to f (N _LS ), and this time is 1 / f
(N _HS ) to 1 / f (N _LS ). That is, from this, tα ° _HS = tα ° _LS , tα ° _HS / (1 / f
(N _HS ) 〜1 / f (N _LS )). These indicate that the ratio of the deviation from the peak value of the neutral point voltage V _MN is increased by shortening the time of one cycle (the frequency of the neutral point voltage V _MN is high). That is, the higher the number of rotations of the brushless motor is, the longer the energization timing of the brushless motor is, and thus the lower the motor efficiency is. The second embodiment aims to solve this problem.

[0017]

Second Embodiment The configuration of the second embodiment is shown in FIG. The second embodiment differs from the first embodiment in that the unstable oscillation circuit is replaced with a peak hold circuit 10 and a voltage controlled oscillator 11. As a rotor position detecting device of the present embodiment, a peak hold circuit 10 for holding the peak value of the neutral point voltage V _MN of the three-phase coil 9 of the brushless motor, and a frequency corresponding to the output voltage V _PH of the peak hold circuit 10 There is a voltage controlled oscillator 11 that oscillates the pulse output f _o of
It further includes a ring counter circuit 2, a sample and hold circuit 3, first and second D flip-flops 4, 5, a comparator 6, a three-phase ring counter 7, and a three-phase inverter circuit 8.

The second embodiment shows an operation of reliably detecting the rotor position when the brushless motor rotates at a low speed as in the first embodiment. However, even when the rotation speed of the brushless motor 9 increases, the operation of the brushless motor is continued. In this case, the effect that the energization timing is not delayed will not occur. Second
The operation and effect of the embodiment will be described below.

FIG. 5 shows waveforms of various parts when the brushless motor is rotating at high speed, and FIG. 6 shows waveforms of various parts when the brushless motor is rotating at low speed. FIG. 7 shows a change in the output voltage V _PH of the peak hold circuit 10 of the neutral point voltage V _MN according to the second embodiment. FIG. 8 shows the voltage V _PH and the pulse of the voltage controlled oscillator 11 according to the second embodiment. shows the relationship between the frequency of the output f _o.

The frequency of the neutral point voltage V _MN changes due to a change in the number of revolutions of the three-phase coil 9 of the brushless motor. Furthermore,
By frequency neutral point voltage V _MN varies, also changes the magnitude of the neutral point voltage V _MN. At this time, if the peak value of the neutral point voltage V _MN is maintained, an output voltage V _PH corresponding to the rotation speed of the brushless motor can be obtained.
This peak hold circuit 10 functions as an FV converter (FIG. 7). The output voltage V _PH that changes in response to the change in the number of revolutions of the brushless motor is input to the voltage control oscillator 11. The voltage controlled oscillator 11 is to oscillate a pulse output f _o comprising a 50% duty ratio for the output voltage V _PH (Fig. 8). Enter the pulse output f _o to the ring counter circuit 2, the rising between pulse width signal f _a, falling between pulse width signal f _b1, further one cycle delay of the pulse width signal f
_b2 , the neutral point voltage V _MN is input to the sample-and-hold circuit 3, and a square wave output P _SMN is obtained from the step-changed neutral point voltage V _SMN of the sample-and-hold circuit 3 as in the first embodiment. Then, a signal is sent from the three-phase ring counter circuit 7 to the bases of the transistors T _{UH to} T _WL of the three-phase inverter circuit 8.

[0021] When the brushless motor three-phase coils 9 is operating at high rpm 5, high frequency of rising between the pulse width signals f _a of the ring counter circuit 2, a low brushless motor three-phase coils 9 in FIG. 6 When operating by rotation, the pulse width signal f between rising edges of the ring counter circuit 2
Frequency of of _a is low. When the brushless motor three-phase coil 9 is operating at high rotation, the frequency (f (N _HS )) of the neutral point voltage V _MN is high, and the brushless motor three-phase coil 9
Is operating at a low speed, the frequency (f (N _LS )) of the neutral point voltage V _MN is also low. That is, the sample-and-hold when when high frequency neutral point voltage V _MN is increasing the frequency of the rising pulse to pulse width signal f _a is the input to the sample-and-hold circuit 3, the low frequency neutral voltage V _MN I'll make low frequencies rising between the pulse width signals f _a is the input to the circuit 3. At this time, the difference between the peak value of the neutral point voltage V _MN and the square wave output P _SMN which is the peak value detection signal (FIG. 5 α _HS , FIG. 6 α _LS ) changes the frequency of the neutral point voltage V _MN. However, the pulse output f _{o of the} voltage controlled oscillator 11 is always delayed by the same angle with respect to one cycle of 360 °.
Set.

The above operation is a problem of the prior art in the present invention (the neutral point voltage V _MN always appears even if the brushless motor speed is very low, so that the rotor position cannot be detected using an integration filter. The same effect as that obtained by overcoming the above problem) is obtained, and even if the rotational speed of the brushless motor fluctuates, the energizing position to the motor is always performed at the same position with respect to the rotor position. Can be prevented from decreasing due to an increase in the number of rotations.

[0023]

As described above, the first aspect of the present invention is a brushless motor rotor position detecting device for detecting a rotor position using a neutral point voltage (V _MN ) of each phase coil of the brushless motor. the neutral point voltage (V _MN) 50% duty cycle pulse output frequency higher than the frequency of (f _o)
And a pulse output (f _o )
Pulse width signal having a pulse width between the rising and between the falling of the clock signal as a clock signal (f _a,
a pulse width signal generating means for generating f _b1), as a standing to a pulse width signal between downlink (f _b1) and data and pulse output (f _o) the clock signal of the pulse generating means,
For the pulse width signal (f _b1 ), one of the clock signals
A first logic circuit for generating a pulse width signal (f _b2 ) between falling edges with a period delay, the neutral point voltage (V _MN ) being used as an analog input signal, and a pulse width between rising edges of the pulse width signal generating means. the signal as a logic signal, the logic signal is detected the analog input signal at "1", and before
The neutral point voltage when the serial logic signal is "0" and Tsu names in
It holds the voltage value of (V _MN), the neutral voltage (V _MN)
Comparing the sample and hold circuit for generating a stepwise variation is allowed stage deformation neutral voltage (V _MSN), the step variations neutral voltage (V _MSN) and the neutral point voltage and (V _MN) of and, comparing means for generating an indefinite stable pulse output (P _VSMN) having a undefined portion and stable portion, prior to said comparing means
The unstable pulse output (P _VSMN ) is used as data and the first
As a clock signal-made 1 cycle delayed falling between pulse width signal (f _b2) by the logic circuit, the indefinite stable Pas
Pulse output from the (P _VSMN) stable portions of "0""1" Oyo
Because and a second logic circuit that generates a square wave output (P _SMN) having a rising and falling changes from "0" to beauty "1", the brushless motor is reliably even at a low rotating rotor There is an excellent effect that the position can be detected and the brushless motor can be operated.

According to a second aspect of the present invention, in place of the pulse generating means, a peak value of a neutral point voltage whose frequency and voltage value change due to a change in the number of revolutions of the brushless motor continues to be held in accordance with the number of revolutions of the motor. Means for generating a voltage output (V _PH ) , and a duty ratio of 50% at a frequency which varies according to the voltage output value of the peak hold means.
% Of the pulse output, the rotor position can be reliably detected when the brushless motor rotates at a low speed, and the rotor position can be accurately detected even when the brushless motor rotates at a high speed. However, there is an excellent effect that the energization timing to the brushless motor is not delayed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a rotor position detecting device according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation principle of the first embodiment.

FIG. 3 is a timing chart showing an actual operation of the first embodiment.

FIG. 4 is a circuit diagram illustrating a configuration of a rotor position detecting device according to a second embodiment.

FIG. 5 is a timing chart showing waveforms of respective parts of the second embodiment when the brushless motor is rotating at a high speed.

FIG. 6 is a timing chart showing waveforms of respective parts of the device of the second embodiment when the brushless motor is rotating at a low speed.

FIG. 7 is a waveform diagram showing a change in an output voltage of a neutral point voltage peak hold circuit according to a second embodiment.

FIG. 8 is a characteristic diagram showing the relationship between the output voltage of the peak hold circuit according to the second embodiment and the frequency of the pulse output of the voltage controlled oscillator.

FIG. 9 is a circuit diagram showing a configuration of a conventional rotor position detecting device.

FIG. 10 is a timing chart showing a state of signal voltages of respective parts in a conventional system.

FIG. 11 is a characteristic diagram showing characteristics of an integration filter used in a conventional method.

[Explanation of symbols]

1. Astable oscillation circuit 2. Ring counter circuit
3 ... Sample and hold circuit, 4,5 ... D flip-flop, 6 ... Comparator, 7 ... Three-phase ring counter circuit, 8 ... Three-phase inverter circuit, 9 ...
Brushless motor three-phase coil, 10 ... peak hold circuit, 11 ... voltage controlled oscillator, 12 ... comparator. f _o ... Pulse output, f _a ... rising between pulse width signal, f _b1 ... falling between pulse width signal, falling between the pulse width signal f _b2 ... 1 cycle delay, V _SMN. .. stage deformation neutral point voltage, P _VSMN ... indefinite stable pulse output, P _SMN ... square wave output, V _MN ... neutral point voltage, R ... detection resistor.

Claims (2)

(57) [Claims] 1. A brushless motorEach phase coilNeutral point of
Voltage(V _MN )To detect rotor position by using brush
A motor rotor position detection device, wherein the neutral point voltage(V _MN )Du of higher frequency than
Pulse output with 50% duty ratio(F _o )Generating pulse
Generation means and its pulse output(F _o )Clock signal as the clock signal.
Pulse with a pulse width between the rise and fall of the
Loose width signal(F _a , F _b1 )Generating pulse width signal
Means and the pulse width signal between its falling edges(F _b1 )Is the dataAnd
Pulse output of the pulse generating means(F _o )The clock signal
As an issue, The pulse width signal (f _b1 )
SignalPulse width signal between falling with one cycle delay(F _b2 )To
A generated first logic circuit, and the neutral voltage(V _MN )And the analog input signalThen
ToThe pulse width signal between rising edges of the pulse width signal generating means is
As a logic signal,When the logic signal is "1"Before
RecordDetects analog input signalAnd saidLogic signal
"0"The neutral point voltage (V _MN )Voltage value
Retentiondo it,The neutral point voltage(V _MN )Change step by stepLet
WasStep deformation neutral point voltage(V _MSN )Sampler
And hold circuit,Said Step deformation neutral point voltage(V _MSN )And the neutral voltage
(V _MN )WhenCompareAnd has an unstable part and a stable partUnfortunate
Constant stable pulse output(P _VSMN )Comparing means for generatingSaid Of comparison meansSaidUnstable pulse output(P _VSMN )The
One cycle delay created by the first logic circuit
Falling pulse width signal(F _b2 )Is the clock signal
hand, The unstable pulse output (P _VSMN )
“0”From“1”And "1" to "0"Changes toStanding
Going upandFallingSquare wave output with(P _SMN )Occurs
Characterized by a second logic circuit that performs
A rotor position detector for a motor. 2. A voltage output (V) according to the number of rotations of the brushless motor, which keeps the peak value of the neutral point voltage whose frequency and voltage value change with the number of rotations of the brushless motor instead of the pulse generation means. _2. A brushless motor according to claim 1, further comprising: peak hold means for generating _PH ) ; and voltage control oscillation means for oscillating a pulse output having a duty ratio of 50% at a frequency which varies according to a voltage output value of said peak hold means. Rotor position detector.