JP3361435B2 - Time counting circuit and PLL circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time counting circuit for measuring time such as pulse intervals of pulse signals.

[0002]

2. Description of the Related Art Time counting circuits for measuring time such as pulse intervals of pulse signals are used in various fields such as digital communication. Further, further improvement of accuracy and stabilization of operation are expected to be applied in the fields of demodulation of frequency modulation (FM) signals and LSI bus signals.

Conventionally, demodulation of FM signals has conventionally been carried out by an analog circuit composed of bipolar transistors. However, if a time counting circuit is used in the FM demodulating circuit, the time counting circuit can be constituted by CMOS transistors, so that FM The demodulation circuit can be placed on the same chip as other digital circuits. As a result, the cost of the semiconductor device can be significantly reduced.

Further, when a time counting circuit capable of accurately and stably measuring a minute time can be used for demodulating an LSI bus signal, the number of LSI buses can be significantly reduced.

FIG. 14 is a circuit diagram showing an example of the configuration of a conventional time counting circuit. In FIG. 14, 80 is a terminal to which a reference clock signal is input, 81 is a phase comparison circuit, and 82
Is an oscillation frequency control circuit, 83 is a power supply circuit, 84 is a counter circuit, 85 is a terminal to which a pulse signal to be measured is input, 86 is an inverter ring composed of an odd number of inverters connected in a ring shape, and 87 is a flip-flop. Columns,
Reference numeral 88 is an encoder, 89 is a signal processing circuit, and 90 is a terminal for outputting time data representing a pulse interval or the like of the pulse signal to be measured.

In FIG. 14, the inverter ring 86 oscillates because an odd number of inverters are connected in a ring shape, and as a result, signal transitions circulate with the passage of time. The output signal of the inverter ring 86 is held by the flip-flop train 87 at the transition timing of the pulse signal to be measured, which is input to the terminal 85. That is,
The output signal of the flip-flop train 87 indicates the position of the signal transition in the inverter ring 86 at the transition timing of the pulse signal to be measured. Therefore, the pulse interval or the like of the pulse signal to be measured can be obtained from the output signal of the flip-flop train 87. The output signal of the flip-flop train 87 is converted by the encoder 88 into binary data representing the position of the signal transition in the inverter ring 86. Further, the counter circuit 84 counts the number of turns of signal transition circulating in the inverter ring 86. The signal processing circuit 89 calculates and outputs time data representing the pulse interval or the like of the pulse signal to be measured based on the binary number data output from the encoder 88 and the count data output from the counter circuit 84 ( IEICE, IEICE Technical Report, ICD93-77 (1993-0)
8), "Time / numerical value conversion LSI").

[0007]

However, the conventional time counting circuit has the following problems.

In the conventional time counting circuit shown in FIG. 14, the inverter ring 86 is composed of an inverter whose delay time can be controlled by a voltage applied from the outside, and is called a voltage controlled oscillator (Voltage Controlled Osc).
illator, hereafter referred to as "VCO"). Then, in order to stabilize the transmission time of the signal transition in the inverter ring 86 (in order to stabilize the oscillation frequency of the VCO), the inverter ring 86 and the phase comparison circuit 8
1, the oscillation frequency control circuit 82 and the power supply circuit 83 constitute a phase locked loop (hereinafter referred to as “PLL”).

In this PLL, the delay time of each inverter constituting the inverter ring 86 is set so that the phase difference between the reference clock signal input to the terminal 80 and the output signal of the final stage inverter of the inverter ring 86 becomes small. Have control. In other words, this PLL controls the inverter ring 86 so that the oscillation frequency of the inverter ring 86 becomes equal to the frequency of the reference clock signal.
The oscillation frequency of the inverter ring 86 is stabilized by the control of this PLL, and the delay time of each inverter composing the inverter ring 86 is determined by setting the cycle of the reference clock signal to the total number of stages of the inverter even if there is a change in temperature or transistor parameters. It is controlled so that the value is divided by 2. Therefore, more accurate time measurement can be performed.

However, in the field in which we are considering the application of the time counting circuit, conventional PLL control is not always sufficient in terms of operating speed and operating accuracy.

FIG. 15 is a block diagram showing the structure of a conventional PLL circuit. In FIG. 15, 90 is an input terminal of a reference clock signal, 91 is a phase comparison circuit, 92 is a charge pump circuit, and 93 is a low pass filter.
r, hereinafter referred to as "LPF"), 94 is a control circuit, 95 is a power supply circuit, and 96 is a VCO. The operation of the PLL has already been energetically analyzed and has been described in many literatures, so a detailed description will not be given. Here, the problem will be described focusing on the case where the PLL is configured in the time counting circuit. When a PLL is formed in the time counting circuit, the VCO 96 in FIG. 15 corresponds to an inverter ring (delay circuit ring), and the charge pump circuit 9
2, the LPF 93 and the control circuit 94 correspond to the oscillation frequency control circuit.

FIG. 16A is a graph showing changes in the power supply voltage V _DD and the control voltage V _c input from the control circuit 94 to the VCO 96. In FIG. 16A, the vertical axis represents voltage and the horizontal axis represents time. Further, ΔV _I is a voltage that determines the oscillation frequency of the VCO 96, and ΔV _I = V _DD −V _c . Since the power supply circuit 95 has a low dependency on the supply voltage V _DD, the voltage [Delta] V _I even if the power supply voltage V _DD is changed to try to keep a constant value. However, due to the limit of the operating characteristics of the power supply circuit 95, the voltage ΔV _I fluctuates in response to a rapid change in the power supply voltage V _DD . As shown in FIG. 16A, in the actual PLL, the voltage ΔV _I does not change as much as the fluctuation of the power supply voltage V _DD , but slightly changes from the limit of the operating characteristics of the power supply circuit 95.

FIG. 16B shows the delay time of each inverter composing the inverter ring when the power supply voltage V _DD fluctuates when the time counting circuit is composed of a PLL, that is, when the VCO 96 is composed of an inverter ring. It is a graph which shows change. In FIG. 16B, the vertical axis represents delay time, the horizontal axis represents time, and the horizontal axis matches the horizontal axis in FIG. 16A. The time t _c is the delay time of each inverter when the oscillation frequency of the inverter ring matches the frequency of the reference clock signal. As shown in FIG. 16B, when the voltage ΔV _I changes due to fluctuations in the power supply voltage V _DD , the delay time of the inverters that form the inverter ring changes and deviates from the time t _c . The deviation of the delay time of the inverter is corrected by the control of the PLL.

FIG. 17A is a graph showing a change in the delay time of the inverter when the delay time of the inverter deviated from the time t _c is corrected by the control of the PLL. The time required for the delay time of the inverter to return to the time t _c and the way to return it are L, which is a component of the PLL that performs control.
It is determined by the characteristics of PF93. FIG. 17A shows L
The change in the delay time of the inverter when the PF 93 is a second-order LPF is shown. Further, FIG. 17B shows a circuit configuration of a typical secondary LPF.

As shown in FIG. 17A, first, time t
_The delay time is corrected at _{1 and} the delay time difference Δt ₀₁ before time t ₁ becomes smaller after time t ₁ and its value approaches 0 and becomes Δt _a . This correction is characterized by being performed in a short time, and the correction period is limited to a local time near the time t ₁ . Furthermore, time t
_The delay time is corrected at _{2 and} the delay time deviation Δt _a before time t ₂ becomes smaller after time t ₂ and becomes Δt _b . The correction period is limited to a local time near time t ₂ .

When the secondary LPF is used for the PLL, the correction period is short and the correction amount is large, so that it is suitable for matching the oscillation frequency of the VCO with the frequency of the reference clock signal. Therefore, in a general PLL used in a clock pulse reproducing circuit, a frequency multiplying circuit, etc. in the field of digital communication, a secondary LPF is used as its constituent element.
Is often used.

However, in this case, as can be seen from FIG. 17A, the delay time of the inverter greatly changes in the correction period. Therefore, when the PLL using the secondary LPF is configured in the time counting circuit, the delay time of each inverter forming the inverter ring is not uniform,
The problem arises that the linearity between real time and time count values is significantly degraded.

In the clock pulse regenerating circuit and the frequency multiplying circuit described above, the output signal of one inverter forming the inverter ring may be controlled (that is, the integral value of the delay time of all inverters is the object of control). The non-uniformity of the delay time of each inverter does not matter. However, since the time counting circuit uses the output signals of the plurality of inverters that form the inverter ring, it is necessary that the delay time of each inverter be uniform (the differential value of the delay time is small).

As described above, the conventional control by the PLL is not always sufficient in terms of operating speed and operating accuracy. Since it is desired to integrate the time counting circuit with other large-scale digital circuits, it will be necessary to mitigate the effects of power supply voltage fluctuations induced by digital circuits and realize highly accurate time measurement in the future. It becomes a very important issue.

In view of the above problems, it is an object of the present invention to alleviate the influence of fluctuations in power supply voltage and the like in a time counting circuit to realize highly accurate time measurement.

[0021]

[Means for Solving the Problems] Means for solving the above problems will be described.

First, the first means is to use a first-order LPF as the LPF in the PLL that constitutes the time counting circuit.

FIG. 18 (a) is a graph showing the change when the delay time of the inverter deviates from the time t _c and is corrected by the control of the PLL.
Shows the case of using. FIG. 18B is a circuit diagram showing the configuration of a typical first-order LPF.

As can be seen by comparing FIG. 18A with FIG. 17A, when the first-order LPF is used as the LPF, the delay time deviation is slightly corrected after the times t ₁ and t _2. However, the correction amount of the delay time per unit time is small. The primary LPF is the secondary LPF.
The output voltage changes more slowly than
Unlike the next LPF, it is not local but over the entire area, but the change in delay time during the correction period is small.

When the first-order LPF is used for the PLL, the clock jitter, which is an important figure of merit, is deteriorated. Therefore, the circuits using the first-order LPF were not so constructed in the circuits other than the time counting circuit. However, by using the first-order LPF as the LPF for the PLL included in the time counting circuit, the nonuniformity of the delay time of the inverter in the inverter ring is suppressed, and the period in which the local change is large is eliminated (the differential value is good. Become). Therefore, the accuracy of linearity is improved in the relationship between real time and time data.

The second means is that the current source for determining the delay time of the inverter is composed of a current source controlled by the PLL control circuit and a current source controlled by the constant voltage power supply circuit. With this configuration, it is possible to suppress variation in delay time due to variation in power supply voltage.

The PLL has a control circuit for controlling the delay time of the inverter, but the control voltage output from this control circuit is easily affected by fluctuations in the power supply voltage. With the above configuration, a part of the current for controlling the delay time of the inverter can be made to be the current controlled by the constant voltage power supply circuit, whereby the change of the delay time due to the fluctuation of the power supply voltage becomes small.

At this time, the control range of the delay time of the inverter is limited. This limitation becomes a problem in a clock signal regenerating circuit having a wide frequency band, but especially in the case of a time counting circuit. It doesn't matter. Second
By this means, the change of the delay time due to the fluctuation of the power supply voltage is reduced, and the accuracy of linearity in the relation between the real time and the time data is improved.

Both the first and second means are PLLs.
Was focused on. The third means is to find the deviation between the frequency of the reference clock signal and the oscillation frequency of the inverter ring, and correct the time data according to this deviation.

That is, the transition timing of the pulse signal to be measured is obtained from the inverter ring to calculate the time data, and the transition timing of the reference clock signal is obtained from the inverter ring to obtain the correction data. Since the correction data represents a deviation between the frequency of the reference clock signal and the frequency of the inverter ring, the accuracy of the time data is improved by correcting the time data using the correction data.

The solution means taken by the invention of claim 1 corresponds to the third means, and comprises a plurality of delay circuits connected in a ring shape, and a delay circuit in which a signal transition is circulated by oscillation. In a time counting circuit that includes a ring, and based on the output signal of each delay circuit of the delay circuit ring at the transition timing of the pulse signal to be measured, the time counting circuit that calculates time data representing the pulse interval of the pulse signal to be measured , A PLL (phase-locked loop) for stably controlling the oscillation frequency of the delay circuit ring with reference to a reference clock signal having a constant frequency,
The correction data used to correct the time data is calculated based on the output signal of each delay circuit of the delay circuit ring at the transition timing of the reference clock signal, and the time data is calculated using the calculated correction data. To correct.

According to the first aspect of the invention, the correction data has a deviation of the oscillation frequency of the delay circuit ring (a deviation of the delay time of each delay circuit forming the delay circuit ring) when the reference clock signal is used as a reference. Therefore, by correcting the time data using this correction data, even if the oscillation frequency of the delay circuit ring shifts due to power supply voltage fluctuations, etc.
The accuracy of time measurement does not deteriorate, and the linearity between real time and time data is compensated, and highly accurate time data can be stably obtained.

According to a second aspect of the present invention, a solution means is an implementation of the third means, which comprises a plurality of delay circuits connected in a ring shape as a time counting circuit and causes a signal transition by oscillation. And a first holding circuit array including a plurality of holding circuits for holding and outputting the output signals of the respective delay circuits forming the delay circuit ring at the transition timing of the pulse signal to be measured. A first arithmetic circuit for calculating time data representing a pulse interval of the pulse signal to be measured based on an output signal of the first holding circuit array, a reference clock signal having a constant frequency, and the delay A phase comparison circuit that compares the phase of the oscillation output signal of the circuit ring and outputs a phase difference detection signal that represents the phase difference between the reference clock signal and the oscillation output signal of the delay circuit ring; According to the phase difference detection signal output from the phase comparator circuit, and a oscillation frequency control circuit for controlling the oscillation frequency of the delay circuit ring, said phase comparator circuit, the oscillation frequency control circuit and the delay circuit ring,
A PLL (Phase Lock Loop) that stably controls the oscillation frequency of the delay circuit ring is configured based on the reference clock signal, and the output signals of the delay circuits that configure the delay circuit ring are used as the reference clock. A second holding circuit row composed of a plurality of holding circuits which holds and outputs at a signal transition timing, and a time calculated by the first arithmetic circuit based on an output signal of the second holding circuit row. A second arithmetic circuit that calculates correction data used for data correction and time data calculated by the first arithmetic circuit are corrected by using the correction data calculated by the second arithmetic circuit. And a correction circuit.

According to the second aspect of the present invention, the output signal of each delay circuit forming the delay circuit ring in which the signal transition is circulated due to the oscillation is generated by the first holding circuit array at the transition timing of the pulse signal to be measured. Based on the held signal, the first arithmetic circuit calculates time data representing the pulse interval of the pulse signal to be measured. Also, a phase comparison circuit that compares the phase of a reference clock signal having a constant frequency with the oscillation output signal of the delay circuit ring, and the delay circuit ring based on the phase difference comparison signal output from the phase comparison circuit And an oscillation frequency control circuit that controls the oscillation frequency of the delay circuit ring. The PLL controls the oscillation frequency of the delay circuit ring with the PLL as a reference. And further, the second
The holding circuit array holds the output signals of the respective delay circuits constituting the delay circuit ring at the transition timing of the reference clock signal, and the second arithmetic circuit calculates correction data used for correcting the time data. To be done.
This correction data represents a deviation of the oscillation frequency of the delay circuit ring (a deviation of the delay time of each delay circuit forming the delay circuit ring) when the reference clock signal is used as a reference. The correction circuit corrects the time data calculated by the first calculation circuit using the correction data. Therefore, even if the oscillation frequency of the delay circuit ring shifts due to fluctuations in the power supply voltage, the time measurement accuracy does not decrease, and the linearity between the actual time and the time data is compensated, so that highly accurate time data can be stabilized. You can get it.

Further, in the invention of claim 3, the correction circuit in the time counting circuit of claim 2 uses the data used for the calculation for correction with respect to the correction data obtained by the second arithmetic circuit. It is assumed that each has a storage means that is stored in advance.

According to the third aspect of the invention, the circuit configuration of the correction circuit is simplified and the circuit scale is reduced.

Further, a solution means taken by the invention of claim 4 is a concrete embodiment of the first means, and is composed of a plurality of delay circuits connected in a ring shape, and signal transition is circulated by oscillation. And a holding circuit array including a plurality of holding circuits that holds the output signals of the respective delay circuits forming the delay circuit ring at the transition timing of the pulse signal to be measured, wherein the holding circuit array is In a time counting circuit for calculating time data representing a pulse interval of the pulse signal to be measured based on the held output signal of each delay circuit, the delay circuit ring based on a reference clock signal having a constant frequency. (Phase-locked loop) for stably controlling the oscillation frequency of the low-pass filter is formed, and the low-pass filter that constitutes the PLL is a primary low-pass filter. It is a certain thing.

According to the fourth aspect of the invention, when the oscillation frequency of the delay circuit ring deviates from the frequency during normal operation, P
The frequency of the normal operation is restored by LL. At this time, since the low-pass filter forming the PLL is a first-order low-pass filter, the operation speed of the PLL is slower and the time required to return to the original frequency is longer than that in the case where a second-order low-pass filter is used. There is no local change in the delay time of each delay circuit constituting the delay circuit ring, and the delay circuits are averaged. In other words, the differential non-linearity of the delay time of each delay circuit is reduced, and the accuracy of time data is improved.

The means for solving the problems of the fifth aspect of the present invention is a concrete form of the second means, and is composed of a plurality of delay circuits connected in a ring shape, and signal transition is circulated by oscillation. The holding circuit array includes a delay circuit ring and a holding circuit array including a plurality of holding circuits that holds an output signal of each delay circuit forming the delay circuit ring at a transition timing of a pulse signal to be measured. In a time counting circuit for calculating time data representing the pulse interval of the pulse signal to be measured based on the output signals of the respective delay circuits, a reference clock signal having a constant frequency and an oscillation output signal of the delay circuit ring. And a phase comparison circuit that outputs a phase difference detection signal representing a phase difference between the reference clock signal and the oscillation output signal of the delay circuit ring, And a oscillation frequency control circuit for controlling the oscillation frequency of the delay circuit ring in accordance with the phase difference detection signal output from the comparison circuit, the phase comparison circuit, the oscillation frequency control circuit and the delay circuit ring,
A PLL (Phase Lock Loop) that stably controls the oscillation frequency of the delay circuit ring is configured based on the reference clock signal, and each delay circuit that configures the delay circuit ring has a first current and a second current. Has a source,
The delay time is determined by the sum of the current amounts of the first and second current sources, and the first current source is the P
The amount of current is controlled by the oscillation frequency control circuit that constitutes the LL, while the amount of current is controlled by the constant voltage power supply circuit in the second current source.

According to the fifth aspect of the present invention, the delay time of each delay circuit forming the delay circuit ring is such that the amount of current is controlled by the oscillation frequency control circuit forming the PLL. Is determined by the sum of the current amounts of the second current sources whose current amount is controlled by. Since the current amount of the second current source does not change even if the power supply voltage changes, it is possible to suppress the change in the oscillation frequency of the delay circuit ring caused by the change in the power supply voltage and the like. Therefore, the linearity between the real time and the time data is improved, and the accuracy of the time data is improved.

According to a sixth aspect of the invention, in the time counting circuit of the fifth aspect, each delay circuit constituting the delay circuit ring is a transistor whose gate voltage is an output voltage of the oscillation frequency control circuit. It is assumed that the differential inverter has a first current source and a transistor having the output voltage of the constant voltage power supply circuit as a gate voltage as the second current source.

The means for solving the problems of the seventh aspect of the present invention is to provide a delay circuit ring, which is composed of a plurality of delay circuits connected in a ring shape, in which signal transitions are circulated by oscillation, and each of the delay circuit rings. And a holding circuit array comprising a plurality of holding circuits for holding the output signal of the delay circuit at the transition timing of the pulse signal to be measured, based on the output signal of each delay circuit held by the holding circuit array, In a time counting circuit that calculates time data representing the pulse interval of a pulse signal to be measured, a PLL (phase lock loop) that stably controls the oscillation frequency of the delay circuit ring with a reference clock signal having a constant frequency as a reference is provided. Each of the delay circuits constituting the delay circuit ring includes a current source and a load resistance element serving as a resistance to an output current of the current source. The delay time is determined by the amount of current of the current source and the resistance value of the load resistance element, and the PLL has a phase between the reference clock signal and the oscillation output signal of the delay circuit ring. Based on the phase difference detection signal output from the phase comparison circuit, which outputs a phase difference detection signal representing the phase difference between the reference clock signal and the oscillation output signal of the delay circuit ring. A first control circuit that controls the amount of current of a current source included in each delay circuit that constitutes the delay circuit ring; and a variation in voltage applied to the delay circuit ring and the first control circuit, A second control unit that controls the resistance value of a load resistance element included in each delay circuit that constitutes the delay circuit ring so that a change in the oscillation frequency of the delay circuit ring due to this voltage fluctuation is suppressed. Assume that a control circuit.

According to the invention of claim 7, the delay time of each delay circuit constituting the delay circuit ring is the current amount of the current source controlled by the first control circuit and the load controlled by the second control circuit. It is determined by the resistance value of the resistance element. Here, the second control circuit detects a change in voltage applied to the delay circuit ring and the first control circuit, and suppresses a change in the oscillation frequency of the delay circuit ring due to the change in the voltage. Since the resistance value of the load resistance element is controlled, the change in the oscillation frequency of the delay circuit ring due to the fluctuation of the power supply voltage or the like can be suppressed small. Therefore, the linearity between the real time and the time data is improved, and the accuracy of the time data is improved.

Further, in the invention of claim 8, in the time counting circuit of claim 7, each delay circuit of the delay circuit ring has a transistor whose gate voltage is an output voltage of the first control circuit. As a source,
It is assumed that the differential inverter has a transistor having the gate voltage of the output voltage of the second control circuit as the load resistance element.

The solution of the invention of claim 9 is, as a time counting circuit, a delay circuit ring composed of a plurality of delay circuits connected in a ring shape, in which signal transitions are circulated by oscillation, and the delay circuit. A first holding circuit row composed of a plurality of holding circuits that holds and outputs the output signal of each delay circuit forming the ring at the transition timing of the pulse signal to be measured, and the output signal of the first holding circuit row Based on the first arithmetic circuit for calculating time data representing the pulse interval of the pulse signal to be measured, and the output signal of each delay circuit constituting the delay circuit ring A second holding circuit row composed of a plurality of holding circuits which holds and outputs at a transition timing, and an operation signal by the first arithmetic circuit based on an output signal of the second holding circuit row. A second arithmetic circuit that calculates correction data used for correcting the time data, and corrects the time data obtained by the first arithmetic circuit using the correction data obtained by the second arithmetic circuit. And a correction circuit.

The means for solving the problems of the tenth aspect of the invention is a PLL for stably controlling the oscillation frequency of the voltage controlled oscillator.
As a (phase-locked loop) circuit, the phase of a reference clock signal having a constant frequency and the oscillation output signal of the voltage controlled oscillator are compared, and the phase difference between the reference clock signal and the oscillation output signal of the voltage controlled oscillator is calculated. A phase comparison circuit that outputs a phase difference detection signal that represents, and an oscillation frequency control circuit that controls the frequency of the voltage controlled oscillator based on the phase difference detection signal output from the phase comparison circuit,
The voltage controlled oscillator has first and second current sources, and the delay time is determined by the sum of the current amounts of the first and second current sources. The source controls the amount of current by the oscillation frequency control circuit, while the second current source controls the amount of current by the constant voltage power supply circuit.

The means for solving the problems of the eleventh aspect of the present invention is a PLL for stably controlling the oscillation frequency of a voltage controlled oscillator.
As a (phase-locked loop) circuit, the voltage-controlled oscillator includes a current source and a load resistance element that serves as a resistance to an output current of the current source, and the current amount of the current source and the resistance of the load resistance element. The delay time is determined by a value, the phase of a reference clock signal having a constant frequency and the oscillation output signal of the voltage controlled oscillator are compared, and the reference clock signal and the oscillation output signal of the voltage controlled oscillator are compared. And a phase comparison circuit that outputs a phase difference detection signal that indicates the phase difference of the first phase control circuit, and a first amount control circuit that controls the current amount of the current source included in the voltage controlled oscillator based on the phase difference detection signal output from the phase comparison circuit. A change in the voltage applied to the control circuit, the voltage-controlled oscillator, and the first control circuit is detected, and a change in the oscillation frequency of the voltage-controlled oscillator due to the change in the voltage is detected. To be braking, in which and a second control circuit for controlling the resistance value of the load resistor element by the voltage controlled oscillator has.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a configuration diagram of a time counting circuit according to a first embodiment of the present invention. In FIG. 1, 1 is an input terminal of a pulse signal to be measured, 2 is a buffer circuit, 3 is an inverter ring as a delay circuit ring in which an odd number of inverters are connected in a ring shape, and 4 is an inverter that constitutes an inverter ring 3. The first buffer circuit row 5 composed of a plurality of buffer circuits each of which receives the output signal of the first input signal 5 is the first at the transition timing of the pulse signal of the measurement target input to the input terminal 1.
A first flip-flop string as a first holding circuit string for holding the output signal of the buffer circuit string 4, a counter circuit 6 for counting the number of turns of the signal in the inverter ring 3, and 7 for input to the input terminal 1. A holding circuit that holds the count data of the counter circuit 6 at the transition timing of the pulse signal to be measured, 8 is a first encoder that converts the output signal of the first flip-flop row 5 into data, and 9 is a first encoder.
It is a first signal processing circuit which receives the output data of the encoder 8 and the holding data of the holding circuit 7 and calculates time data representing the pulse interval and the like of the pulse signal to be measured. The first encoder 8 and the first signal processing circuit 9 form a first arithmetic circuit.

Reference numeral 11 is an input terminal for a reference clock signal serving as a reference for the oscillation frequency of the inverter ring 3, 12 is a buffer circuit, and 13 is a phase comparison for comparing the phases of the reference clock signal and the oscillation output signal of the inverter ring 3. The circuit, 14 is based on the phase difference detection signal that is output from the phase comparison circuit 13 and represents the phase difference between the reference clock signal and the oscillation output signal of the inverter ring 3.
An oscillation frequency control circuit for controlling the delay time of each of the inverters, 15 is a power supply circuit for supplying a constant voltage to the oscillation frequency control circuit 14, and a phase lock loop (PLL) using the inverter ring 3 as a voltage controlled oscillator is configured. ing.

Reference numeral 16 designates a second buffer circuit array composed of a plurality of buffer circuits each receiving the output signal of the inverter constituting the inverter ring 3, and 17 designates the transition timing of the reference clock signal input to the input terminal 11. Second
The second flip-flop string as a second holding circuit string holding the output signal of the buffer circuit string 16 of the counter circuit 18 and the count data of the counter circuit 6 at the transition timing of the reference clock signal input to the input terminal 11. A holding circuit for holding, 19 is a second encoder that converts the output signal of the second flip-flop string 17 into data, and 20 is input with the output data of the second encoder 19 and the holding data of the holding circuit 18, and the first 2 is a second signal processing circuit for calculating correction data used for correcting the time data calculated by the signal processing circuit 9. Second encoder 19
Also, the second signal processing circuit 20 constitutes a second arithmetic circuit.

Reference numeral 21 is a first synchronizing circuit for outputting the output data of the second signal processing circuit 20 input in synchronization with the reference clock signal in synchronization with the pulse signal to be measured.
Reference numeral 2 is a third signal processing circuit as a correction circuit for correcting the time data calculated by the first signal processing circuit 9 by using the output data of the first synchronizing circuit 21, 23 is an input terminal of an external clock, and 24 Is a buffer circuit, and 25 is the synchronized time data output from the third signal processing circuit 22 in synchronization with the pulse signal to be measured, and outputs the corrected time data at the edge timing of the external clock input to the input terminal 23. The second synchronizing circuit 26 is an output terminal for outputting the corrected time data.

The basic operation of the time counting circuit according to the present embodiment shown in FIG. 1 will be described first.

In the inverter ring 3, since an odd number of inverters are connected in a ring shape, oscillation occurs and signal transitions circulate.

[0054]

[Table 1]

Table 1 is a table showing the circulation of signal transitions in the inverter ring 3. In Table 1, the left column shows the quantized time, the middle column shows the output signal of the inverter ring 3 at each time, and the right column shows the first encoder 8 or the second encoder 8 obtained from the output signal of the inverter ring 3. The output data of the encoder 19 is shown. Although the time varies continuously, the time counting circuit quantizes the continuously varying time and divides it into predetermined gradations. As shown in Table 1, the time counting circuit shown in FIG. In, the time is divided into 9 gradations.

Here, in order to simplify the explanation,
It is assumed that the delay time of each inverter forming the inverter ring 3 is 1 ns. That is, the time step in Table 1 is 1 ns. Further, in the output signal of the inverter ring 3, "L" represents a low level in the logic circuit and "H" represents a high level in the logic circuit.

As shown in Table 1, at time 0, the output signal of the inverter ring 3 is "LHLHLHLHL". Since the output signals of the first-stage and ninth-stage inverters are both “L”, it can be said that the signal circulating in the inverter ring 3 reaches the first-stage inverter. Table 1
Then, the underline is added to the place where the output signals of the adjacent inverters have the same level. When 1 ns has passed from time 0, it becomes time 1, and the signal circulating in the inverter ring 3 is transmitted to the inverter of the next stage, and the output signals of both the first and second stage inverters become "H". 1 ns
When time elapses, time 2 is reached, and the output signals of the second-stage and third-stage inverters both become "L". In this way, the signal circulating in the inverter ring 3 is transmitted to the next-stage inverter every 1 ns. However, when the output signals of the adjacent inverters are both "H" and "L", they alternately appear in time. The first encoder 8 and the second encoder 19 convert the output signal of the inverter ring 3 into binary 4-bit data as shown in the right column.

In Table 1, the time is divided into 9 gradations, so if the time step is 1 ns, the maximum measurement time is 9
ns. Therefore, in order to measure a longer time, in the time counting circuit shown in FIG. 1, the counter circuit 6 that counts the number of turns of the signal transition in the inverter ring 3 is used.
Is provided.

[0059]

[Table 2]

Table 2 is a table showing time data calculated by the time counting circuit shown in FIG. As shown in Table 2,
By using the 3-bit counter circuit 6, time 0
It is possible to measure time data of 72 gradations from time to time 71.

The characteristics of the time counting circuit according to this embodiment are as follows.
The point is that the time data is corrected using the reference clock signal.

Here, the principle of time correction in this embodiment will be described with reference to FIG. FIG. 2 is a diagram conceptually showing the principle of time correction according to the present embodiment.

The reference clock signal input to the input terminal 11 is input to the second flip-flop string 17, and the second flip-flop string 17 holds the output signal of the inverter ring 3 at the transition timing of the reference clock signal. .
In FIG. 2, it is assumed that the output signal of the inverter ring 3 is held at the falling timing of the reference clock signal.

In FIG. 2, the circulation of signal transitions in the inverter ring 3 is shown in the form of clock signals. The number attached to the transition point of the clock signal is the inverter ring 3
Indicates the number of stages of the inverter where the signal transition has reached. For example, the transition point indicated by 4 indicates that the signal transition has reached the inverter of the fourth stage. Therefore,
The pulse width of the clock pulse signal corresponds to the delay time of each inverter in the inverter ring 3. The variation of the pulse width indicates the change of the delay time of each inverter due to the fluctuation of the power supply voltage.

As shown in FIG. 2, at the time t ₁ when the reference clock signal falls, the inverter ring 3
The signal transition at reaches the fifth stage inverter. At this time, the time τ _n-1 is quantized to "5" (quantized with the first-stage inverter as a reference). Further, at time t ₂ which is the next falling edge of the reference clock signal, the time τ _n is quantized to “8”. Letting T _{R be} the period of the reference clock signal and T _n be the period of the output signal of one inverter in the inverter ring 3 (hereinafter referred to as “the period of the inverter ring 3”), the time τ _n−1 , τ _n and the period T _n , T _R have the following relationship. _{T n = T R -τ n-} 1 + τ n ... (1) The time τ _n-1, τ _n the quantized values (here a "8" and "5") to M _n-1 , M _n . Also,
The quantized value of the period T _R of the reference clock signal is set by PLL
Under the premise that the inverter ring 3 is operating in a constant manner, the number of inverters constituting the inverter ring 3 is twice the number N (here, 9). Therefore, _if the quantized value of the period T _n of the inverter ring 3 is P _n , P _n is expressed by the following equation. When the _{P n = 2N-M n-} 1 + M n ... (2) uncorrected time data to D _n, the time data C _n after correction formula as follows. _{C n = D n + D n} · (M n -M n-1) / P n = D n + D n · (M n -M n-1) / (2N-M n + M n-1) ... (3) That is, the time data D _n can be corrected by obtaining the quantized values M _n−1 and M _n and calculating the equation (3). The value of N on the right side of the equation (3) may be optimized according to the operating characteristics of the PLL and the noise superimposed on the power supply, but if optimization is not particularly required, the connection of the inverters of the inverter ring 3 may be performed. The number of steps.

The quantized values M _n-1 and M _n are stored in the second flip-flop train 17 at the transition timing of the reference clock signal.
From the signal held by the second signal processing circuit 20
Required by. Further, the calculation of the equation (3) is mainly executed by the third signal processing circuit 22.

Description will be made taking specific numerical values as an example. Figure 2
In such a case, M _n-1 = 5, M _n = 8, N = 9, and the quantized value P _n of the period of the inverter ring 3 is P _n = 2 × 9−5 + 8 from the equation (2). = 21. Assuming that the time data before correction D _n = 25, the time data after correction C _n is C _n = 25 + 25 × (8-5) / 21 = 29 (rounded off after the decimal point) from the equation (3).

FIG. 3 is a circuit diagram showing the configuration of the first signal processing circuit 9. The first signal processing circuit 9 calculates time data before correction from the 4-bit data input from the first encoder 8 and the 3-bit data input from the counter circuit 6 via the holding circuit 7. .

In FIG. 3, the terminal a ₁ receives the 3-bit data output from the counter circuit 6 through the holding circuit 7, and the terminal a ₂ receives the first encoder 8
The 4-bit data output from is input. Also,
The pulse signal to be measured is input to terminal a ₃ and
_{From 4} , the calculated time data before correction is output.

Flip-flops 31a and 31b hold 3-bit data, and hold and output the data input to the terminal a ₁ . 32a and 32b are 4 bits
It is a flip-flop that holds data and has a terminal a ₂
Holds and outputs the data input to. Reference numeral 33 is a data conversion circuit, which converts 3-bit data input from the flip-flop 31b to the terminal D into 4-bit data by adding "0" to the higher order and outputs the 4-bit data from the terminal Q. For example, “011” is converted into “0011” by the data conversion circuit 33.

Reference numeral 34 denotes an addition circuit, which is the addition result by adding the 4-bit data input from the data conversion circuit 33 to the terminal A and the 4-bit data input from the flip-flop 32b to the terminal B. Of the 5-bit data, the upper 2 bits are output from the terminal Q ₁ and the lower 3 bits are output from the terminal Q ₂ . Reference numeral 35 denotes a data conversion circuit, which converts 2-bit data input from the terminal Q ₁ of the adder circuit 34 into terminal D into 3-bit data by adding “0” to the higher order, and then from the terminal Q. Output. For example, “01” is set to “0” by the data conversion circuit 35.
Is converted to 01 ".

An adder circuit 36 adds the 3-bit data input to the terminal A from the flip-flop 31b and the 3-bit data input to the terminal B from the data conversion circuit 35, and is the addition result. The 4-bit data is output from the terminal Q. Reference numeral 37 is a data conversion circuit, which sets the 4-bit data input from the adder circuit 36 to the terminal A as the higher-order bit, and also adds the terminal Q ₂ to the terminal B of the adder circuit 34.
The terminal Q outputs 7-bit data having the 3-bit data input to the lower bit as the lower bit. For example, if the data input to the terminal A is "0011" and the 3-bit data input to the terminal B is "001", the data output from the terminal Q is "0011001".

Reference numeral 38 is a flip-flop for holding 7-bit data, which holds and outputs the 7-bit data output from the data conversion circuit 37. A subtraction circuit 39 subtracts the 7-bit data input to the terminal B from the data conversion circuit 37 from the 7-bit data input to the terminal A from the flip-flop 38.

The operation of the first signal processing circuit 9 shown in FIG. 3 will be described by taking the case of time 11 as an example.

As shown in Table 2, at time 11, the output data of the counter circuit 6 input to the terminal a ₁ is "0".
01 ", and the output data of the first encoder 8 is" 0010 ". The data conversion circuit 33 converts the input output data" 001 "of the counter circuit 6 into" 000 ".
1 ". The addition circuit 34 includes the first encoder 8 input to the terminal B and" 0001 "input to the terminal A.
And the output data “0010” of 1 are added. Since the 5-bit data which is the addition result is "00011", the adder circuit 34 is, 5 bits from the terminal Q ₂ outputs the high-order 2 bits "00" of the 5-bit data from the terminal Q ₁
The lower 3 bits "011" of the data are output. The data conversion circuit 35 converts the data “00” input from the terminal Q ₁ of the addition circuit 34 into “000”. Adder circuit 36
Adds "001" input to the terminal A and "000" input to the terminal B, and adds "0001" as the addition result.
Is output. The data conversion circuit 37 has 7-bit data “000” in which “0001” input to the terminal A is an upper bit and “011” input to the terminal B is a lower bit.
1011 ”is output. This 7-bit data“ 0001
011 "is time data at time 11 as shown in Table 2.

The subtraction circuit 39 subtracts the 7-bit data input to the terminal B from the data conversion circuit 37 from the 7-bit data input to the terminal A from the flip-flop 38, and outputs the result. Since the flip-flop 38 temporarily holds the time data input from the data conversion circuit 37, the time data output from the subtraction circuit 39 represents the time between transition points of the pulse signal to be measured.
The above-mentioned data “00010101” is input to the terminal A,
If the next time data "0000011" is input to the terminal B, the output data of the subtraction circuit 39 is "00".
01000 ″. As a result of such an operation, the terminal a ₄
Outputs time data representing time such as the pulse interval of the pulse signal to be measured.

FIG. 4 is a circuit diagram showing the configuration of the second signal processing circuit 20. In FIG. 4, reference numeral 41 denotes a signal processing circuit for calculating data M _n and M _n-1 used for calculating the coefficient of the second term (hereinafter referred to as “correction term”) on the right side of the equation (3).
Reference numerals 2 and 43 are flip-flops for holding 7-bit data, 44 is a subtraction circuit for calculating the difference between the data input to the terminal D ₁ and the data input to the terminal D ₂ , and 45 is a 7-bit data It is a flip-flop.

The second encoder 19 operates similarly to the first encoder 8, and converts the output signal of the inverter ring 3 output from the second flip-flop string 17 into binary data and outputs it.

In FIG. 4, the terminal b ₁ receives the 3-bit data output from the counter circuit 6 via the holding circuit 18, and the terminal b ₂ outputs the 4 bits output from the second encoder 19. Bit data is input. Further, the reference clock signal is input to the terminal b ₃ .

The signal processing circuit 41 operates in substantially the same manner as the first signal processing circuit 9 and calculates correction time data from the data input to the terminals a ₁ and a ₂ and outputs it from the terminal a ₄ . . That is, at the timing of transition of the reference clock signal, the signal processing circuit 41 outputs 7-bit data corresponding to the quantized values M _n−1 and M _n in the equation (3).

The subtraction circuit 44 includes the data inputted from the flip-flop 42 at the terminal D ₁ and the flip-flop 43.
Is delayed by one clock (that is, one transition of the reference clock signal) to calculate the difference from the data input to the terminal D ₂ . That is, (M _n −M in equation (3)
_n-1 ) is calculated. The data of the calculation result is output from the terminal b ₄ via the flip-flop 45.

FIG. 5 is a circuit diagram showing the configuration of the third signal processing circuit 22. In FIG. 5, the correction data of 7-bit data (M _n −M _n−1 ) output from the second signal processing circuit 20 is corrected at the terminal C ₁ by the first synchronizing circuit 21. Is input (in synchronization with the pulse signal to be measured). The terminal C ₂ has a first signal processing circuit 9
The 7-bit pre-correction time data output from is input in synchronization with the pulse signal to be measured. Also, the terminal C ₃
A pulse signal to be measured is input to.

51a to 51e, 52, 54 and 55 are flip-flops, 53 is a multiplication circuit for calculating the correction term in the formula (3), and 56 is a calculation of the formula (3) using the output data of the multiplication circuit 53. Is an adder circuit for performing. The flip-flops 51a to 51d delay the data input to the terminal C ₁ in order to match the timing of the data calculated in the multiplication circuit 53.

The output data of the flip-flop 51e is
The data ( _Mn - _Mn-1 ) used for time correction, which is calculated by the second signal processing circuit 20. The output data of the flip-flop 52 is the time count data D _n before correction, which is calculated by the first signal processing circuit 9. Here, the output data of the flip-flop 51e is set to "0000011". In the output data of the flip-flop 51e, the most significant bit indicates whether the data is positive or negative. When the most significant bit is "0", the data is positive, and when the most significant bit is "1", the data is negative. Further, the output data of the flip-flop 52 is set to "0011001".

The multiplication circuit 53 includes a flip-flop 51e.
Output data and using the output data of the flip-flop 52 correction term _{D n · (M n -M n} -1) / (N-M n + M for
_n-1 ) is calculated. In the time counting circuit shown in FIG. 1, N = 1
Since it is 001 (binary number representation, “9” in decimal number), N−M _n + M _n−1 = 1100, and “1101” is output as the calculation result of the correction term. D _n · (M _n −M
_n-1 ) / (N- _Mn + _Mn-1 ) is 12.5 in decimal.
However, the value after the decimal point is rounded to 13 here.

The addition circuit 56 adds the data "0011001" input from the flip-flop 54 to the terminal A and the data "1101" input from the multiplication circuit 53 to the terminal B via the flip-flop 55, and adds the data. The result data “0100110” is output. The output data of the adder circuit 56 is used as corrected time count data at the terminal C ₄
Is output from.

Further, the first synchronizing circuit 21 outputs the 7-bit data output from the second signal processing circuit 20 at the transition timing of the reference clock signal to the third signal at the transition timing of the pulse signal to be measured. It has a function of changing the data output timing so that the data is input to the processing circuit 22.

FIG. 6A is a circuit diagram showing a detailed structure of the first synchronizing circuit 21. In FIG. 6A, n is a data input terminal, p is a data output terminal, o is an input terminal for the _first clock signal CLK ₁ , and q is an input terminal for the second clock signal CLK ₂ . In the first synchronizing circuit 21, the reference clock signal corresponds to the _first clock signal CLK ₁ and the pulse signal to be measured is the second clock signal C 2.
Equivalent to LK ₂ . Also, 61 and 65 are 7-bit flip-flops that operate according to the clock signal input to the terminal C, 62 and 66 operate according to the clock signal input to the terminal C, and a "H" signal is input to the terminal R. Then, reset type flip-flops that initialize the output signal to "L", 63 and 67 are logic circuits, and 64 and 68 are delay circuits. The flip-flop 61 and the reset flip-flop 62 operate in accordance with the _first clock signal CLK ₁ input to the terminal o, and the reset flip-flop 66 operates the second clock signal CL input to the terminal q.
Operates according to K ₂ .

The operation of the first synchronizing circuit 21 shown in FIG. 6A will be described with reference to the timing chart shown in FIG. 6B.

The reference clock signal (that is, the first clock signal C from the second signal processing circuit 20) is applied to the terminal n.
7-bit data is input at the transition timing of LK ₁ ). First clock signal CLK input to terminal o
_{When 1} rises, the flip-flop 61 holds the data input to the terminal n. Further, the reset flip-flop 62 outputs the signal of “H” from the terminal Q because the potential of the terminal D is always “H”. That is, the signal potential at the node A becomes "H". The signal potential of the terminal B is the signal potential of the terminal A delayed.

When the pulse signal to be measured (that is, the second clock signal CLK ₂ ) input to the terminal q rises, the reset flip-flop 66 holds the signal at the node A and outputs it from the terminal Q. As a result, the signal potential at the node D changes to "H", the output data of the flip-flop 61 is held by the flip-flop 65, and is output from the terminal p. At this time, since the signal potentials at the nodes B and D both become "H", the output signal of the logic circuit 63 becomes "H".
Then, the reset flip-flop 62 is initialized. Further, the reset flip-flop 66 is initialized at the falling edge of the _second clock signal CLK ₂ . Therefore, the first synchronizing circuit 21 returns to the initial state.

By such an operation, as shown in FIG. 6B, the first synchronizing circuit 20 changes the data input at the transition timing of the first clock signal CLK ₁ (reference clock signal) into the first data. Two clock signals CLK ₂ (pulse signal to be measured) can be output at the timing.

In the second synchronizing circuit 25, the corrected time count data output from the third signal processing circuit 22 at the transition timing of the pulse signal to be measured is input to the input terminal 23. It has a function of changing the data output timing so that the data is output from the terminal 26 at the timing of the external clock. The circuit configuration is the same as that of the first synchronizing circuit 21 shown in FIG. 6A, and a pulse signal to be measured is applied to the terminal o as the first clock signal CLK ₁ and the second clock signal CLK ₂ is supplied. Terminal q
An external clock is applied to.

FIG. 7 is a block diagram showing another example of the configuration of the third signal processing circuit. Wherein the third signal processing circuit 22A shown in FIG. 7, the second correction data inputted from the signal processing circuit 20 of the (M _n -M _n-1) table format the value of the correction term for the terminal c ₁ The point is that it is provided with the ROM 58 as a storage means, which is stored in 1. That is, the ROM 58
_Stores the value of 1 / Q _n shown in the following equation in a table format. _{1 / Q n = (M n} -M n-1) / (N-M n + M n-1) ... (4)

Table 3 is a table showing an example of data stored in the ROM 58.

[0096]

[Table 3]

In FIG. 7, the read circuit 57 reads the value of the correction term from the ROM 58 according to the correction data (M _n -M _n-1 ) input from the terminal c ₁ . Multiplication circuit 5
9 is the correction term 1 read by the read circuit 57.
/ Q _n and time data D before correction input from terminal c ₁
Multiplies with _n . The addition circuit 60 adds the value D _n / Q _n input from the multiplication circuit 59 and the pre-correction time data D _n and outputs the corrected time data from the terminal c ₄ .

The time counting circuit shown in FIG.
However, the present invention is not limited to the time counting circuit in which the PLL is configured, and can be applied to a time counting circuit in which the PLL is not configured. FIG. 8 is a circuit diagram showing the configuration of the time counting circuit according to the present embodiment in which the PLL is not configured, and the same components as those in FIG. 1 are designated by the same reference numerals. In the time counting circuit shown in FIG. 8, the reference clock signal is used only for correcting the time data representing the pulse interval or the like of the pulse signal to be measured.

Second Embodiment FIG. 9 shows a PLL (Phase Lo) according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a cked loop (phase locked loop) circuit. In FIG. 9, 70 is a VCO (Volt
age controlled oscillator, voltage controlled oscillator), 71
Is a terminal to which the reference clock signal is input, and 72 is a VCO 7
A phase comparison circuit that compares the phase of the oscillation output signal of 0 with the reference clock signal input to the terminal 71, 73 is a charge pump circuit, 74 is an LPF (Low Pass Filter), and 75 is from the charge pump circuit 73. A first control circuit that controls the oscillation frequency of the VCO 70 based on the voltage that is output and has the high frequency component removed by the LPF 74, a second control circuit that suppresses a change in the oscillation frequency of the VCO 70 due to fluctuations in the power supply voltage, 77 Is a first power supply circuit that supplies a constant voltage to the charge pump circuit 73,
Reference numeral 78 is a second power supply circuit as a constant voltage power supply circuit that supplies a constant voltage to the first control circuit 75 and the VCO 70. The charge pump circuit 73, the LPF 74, and the first control circuit 75 constitute an oscillation frequency control circuit.

FIG. 10 shows V in the PLL circuit shown in FIG.
It is a circuit diagram which shows the structure of CO70. In FIG.
Reference numeral 79 is a differential inverter, and the VCO 70 is composed of a differential inverter ring composed of an odd number (five in FIG. 10) of differential inverters 79 connected in a ring shape. In the differential inverter 79, D is a non-inverting input terminal, DB is an inverting input terminal, Q is a non-inverting output terminal, QB is an inverting output terminal, and each differential inverter 79, 79 ,.
, The normal output terminal Q is connected to the inverting input terminal DB of the next stage differential inverter, and the inverting output terminal QB is connected to the normal input terminal D of the next stage differential inverter. The control voltage V _c1 supplied from the first control circuit 75 is applied to the terminal F, the control voltage V _c2 supplied from the second control circuit 76 is applied to the terminal H, and the terminal C is further applied. Is applied with the voltage V _d2 supplied from the second power supply circuit 78.

P according to the present embodiment shown in FIGS. 9 and 10.
The LL circuit is suitable for the time counting circuit.
When the L circuit is used for the time counting circuit, the differential inverter ring forming the VCO 70 is used as the inverter ring of the time counting circuit.

The PLL circuit according to this embodiment is the same as the conventional P circuit.
There are four differences from the LL circuit.

First, two power supply circuits are provided, and a voltage is supplied to the charge pump circuit 73 by the first power supply circuit 77, while a voltage is supplied to the first control circuit 75 and the VCO 70 by the second power supply circuit 78. Is the point of supplying.

The second difference is that the current source in each differential inverter 79 constituting the VCO 70 is constituted by the PMOS transistors P1 and P2, and the gate of the PMOS transistor P1 as the second current source is connected to the second power supply circuit. The point is that the voltage V _d2 supplied from 78 is applied, while the control voltage V _c1 supplied from the first control circuit 75 is applied to the gate of the PMOS transistor P2 as the first current source.

The third difference is that the control supplied from the second control circuit 76 to the gates of the NMOS transistors N2, N3 as load resistance elements among the NMOS transistors N1, N2, N3, N4 as load transistors. This is the point at which the voltage V _c2 is applied.

The fourth difference is that the LPF 74 is a first-order LPF so as to be suitable for constituting a time counting circuit.
That is the point.

The operation of the PLL circuit according to this embodiment will be described below, focusing on the differences from the conventional PLL circuit. Since the phase comparison circuit 72, the charge pump circuit 73, and the first control circuit 75 operate in the same manner as the conventional PLL circuit, detailed description will be omitted here.

In each differential inverter 79 of the VCO 70 shown in FIG. 10, the gate voltage of the PMOS transistor P1 is the voltage V _d2 supplied from the second power supply circuit 78, while the gate voltage of the PMOS transistor P2 is the first voltage. It is the control voltage V _c1 supplied from the control circuit 75. Second
The supply voltage V _d2 of the power supply circuit 78 is hardly affected by the fluctuation of the power supply voltage, but the supply voltage V _c1 of the first control circuit 75 is relatively strongly affected by the fluctuation of the power supply voltage.
Therefore, the change in the drain current due to the change in the power supply voltage is larger in the PMOS transistor P2 than in the PMOS transistor P1, and the drain current of the PMOS transistor P1 is hardly affected by the change in the power supply voltage. Since the signal delay time of the differential inverter 79 is determined by the sum of the drain current amounts of the PMOS transistors P1 and P2, the change of the signal delay time of the differential inverter 79 due to the fluctuation of the power supply voltage becomes smaller than the conventional one, and the fluctuation of the power supply voltage. The impact of will be mitigated. However, in this case, the differential inverter 7
The control range of the delay time of 9 will be limited.

FIG. 11 shows the reason why the influence of the power supply voltage fluctuation is alleviated in the PLL circuit according to this embodiment as compared with the conventional case.
Will be used to explain in more detail.

FIG. 11A shows a part of the structure of a conventional PLL. The control circuit 94 is biased by the voltage V _d supplied from the power supply circuit 95, and the LPF 9
The control voltage V _c is changed according to the output signal of No. 3. Here, the VCO 96 is assumed to be configured by a differential inverter ring as shown in FIG. 10 like the PLL according to the present embodiment, and the gates of the P-type MOS transistors P ₁ and P _{2 serving} as current sources are connected to the VCO 96. The control voltage V _c output from the control circuit 94 is applied. At this time, VC
The variation amount Δτ _d1 of the delay time τ _d1 of the differential inverter forming O96 is Δτ _d1 = a ₁ · ΔV _c (11) when the variation amount of the control voltage V _c is ΔV _c . Here, a ₁ represents the rate of change.

On the other hand, FIG. 11B shows a part of the configuration of the PLL according to this embodiment. First control circuit 75
Is biased by the voltage V _d1 supplied from the second power supply circuit 78, and changes the control voltage V _c1 according to the output signal of the LPF 74. In this case, variation .DELTA..tau _d2 of delay time tau _d2 of inverters constituting the VCO70, the control voltage [Delta] V _c1 the variation of V _c1, [Delta] V _d2 the variation of the voltage V _d2 output from the second power supply circuit 78 Then, Δτ _d2 = a ₂ · ΔV _c1 + a ₃ · ΔV _d2 (12) Here, a ₂ and a ₃ represent change rates.

Next, consider the influence of fluctuations in the power supply voltage. Letting ΔV _cn be the change in the control voltage V _c due to the fluctuation ΔV _DD of the power supply voltage V _DD , ΔV _cn = a _n · ΔV _DD (13) Substituting [Delta] V _cn of formula (11) formula (13) [Delta] V _{c of, Δτ d1 = a 1 · a} n · ΔV DD ... (14) , and this equation (14), when the supply voltage fluctuates The variation amount of the delay time of the differential inverter that constitutes the VCO 96 in the conventional PLL is shown.

Further, when ΔV _cn of the equation (13) is substituted for ΔV _c of the equation (12), Δτ _d2 = a ₂ · a _n · ΔV _DD (15) and the equation (15) is obtained. Represents the amount of change in the delay time of the differential inverter that constitutes the VCO 70 in the PLL according to the present embodiment when f. In the equation (15), since the change of the voltage V _d2 supplied from the second power supply circuit 78 to the VCO 70 due to the fluctuation of the power supply voltage is sufficiently small, the second term on the right side is omitted.

Here, the change rates a ₁ and a ₂ depend on the ratio of the change of the drain current to the change of the gate-source voltage of the P-type MOS transistor forming the current source of the differential inverter. In the conventional PLL, the control voltage V _c is applied to both gates of the two P-type MOS transistors forming the current source of the differential inverter, while the PLL of the present embodiment forms the current source of the differential inverter. The control voltage V _c is applied to the gate of only one of the two P-type MOS transistors. Therefore, the following relationship holds. a ₁ >> a ₂ (16) From equations (14), (15) and (16), Δτ _d1 >> Δτ _d2 (17) holds. Therefore, according to the PLL of the present embodiment, the change in the delay time of the differential inverter due to the fluctuation of the power supply voltage becomes smaller than in the conventional case, and the influence of the fluctuation of the power supply voltage is mitigated.

Further, the PL according to the present embodiment shown in FIG.
In the L VCO 70, the N-type MOS transistor N
2 and N3 have a function of adjusting the load resistance value of the differential inverter 79 according to the gate voltage. Since the delay time of the differential inverter 79 can be adjusted by the change of the load resistance value, the change of the delay time of the differential inverter 79 due to the fluctuation of the power supply voltage is changed.
It can be suppressed by controlling the gate voltage of N2.

Specifically, the control voltage V _c2 output from the second control circuit 76 is the N-type MO of each differential inverter 79.
It is supplied to the gates of the S transistors N2 and N3,
The second control circuit 76 detects a change in the output voltage of the second power supply circuit 78 and suppresses the change in the delay time in the differential inverter 79 of the VCO 70 due to the change in the voltage so that the change in the control voltage V is suppressed. Change _c2 .

The suppression of the change in the delay time of the VCO 70 by the second control circuit 76 will be described in more detail with reference to FIG.

From the second power supply circuit 78 to the first control circuit 7
If the amount of change in the voltage V _d1 supplied to 5 due to power supply voltage fluctuation is ΔV _d1, and the amount of change in the voltage V _d2 supplied from the second power supply circuit 78 to VCO 70 due to power supply voltage fluctuation is ΔV _d2 , then VCO 70 is The amount of change Δτ _{d3 in} the delay time of the constituent differential inverter due to the power supply voltage fluctuation is Δτ _d3 = a ₄ · ΔV _d1 + a ₅ · ΔV _d2 (18) Here, a ₄ and a ₅ are change rates.

The second control circuit 76 receives the voltages V _d1 and V _d2 as inputs, and changes the control voltage V _c2 so as to change the delay time of the differential inverter forming the VCO 70 by Δτ _d4 . Here, Δτ _d4 becomes Δτ _d4 = a ₆ · ΔV _d1 + a ₇ · ΔV _d2 (19). a ₆ and a ₇ are the rates of change.

In order to suppress the change in the delay time of the VCO 70, Δτ _d3 = Δτ _d4 (20) should be established for arbitrary voltage change amounts ΔV ₁ and ΔV ₂ . Expressions (18) and (19) are added to Expression (20).
Is substituted, (a ₄ −a ₆ ) · ΔV ₁ + (a ₅ −a ₇ ) · ΔV ₂ = 0 (21), and the condition that Equation (21) holds for arbitrary ΔV ₁ and ΔV ₂ is a ₄ = a ₆ and a ₅ = a ₇ (22). Since the second control circuit 76 is configured so that the change rates a ₆ and a ₇ satisfy the equation (22), the VCO 7
It is possible to suppress the change in the delay time of the differential inverter forming 0 due to the power supply voltage fluctuation.

Furthermore, the PL according to the present embodiment shown in FIG.
In L, the LPF 74 uses a first-order low-pass filter. The PLL operates so as to reduce the phase difference between the reference clock signal and the oscillation output signal of the VCO 70, and the LPF 7 determines the characteristic of the control speed of the PLL.
It is 4. By using a first-order low-pass filter for the LPF 74, the control speed is reduced as described in the section of the problem, but on the other hand, the control range is expanded and the control amount is smoothed.

The LPF 74 is not limited to the structure having only passive elements, but may be a low-pass filter having a slow operating speed, which has a structure using active elements and a structure using both active elements and passive elements.

Of course, when the PLL circuit according to this embodiment is applied to the time counting circuit, since the VCO 70 corresponds to the inverter ring, it is necessary to set the number of stages of the differential inverter of the VCO 70 to the number required for the time counting circuit. is there.

FIG. 13 is a diagram showing an application example of the time counting circuit according to the present embodiment, which is a conceptual diagram showing a method of reading a signal recorded on a laser disk. As shown in FIG. 13, the laser oscillator 1 is attached to the laser disk 100.
The light emitted from 01 is reflected or non-reflected according to the bit recorded on the laser disk 101. The reflected or non-reflected light is converted into a sinusoidal signal 102,
The time t ₁ , t between the zero cross points of the sine wave signal 103
₂ , t ₃ , ... Correspond to the number of times the same bit in the signal of the laser disk 100 continues. Therefore, after the sine wave signal 102 is amplified and converted into the square wave signal 103, the time between each edge of the square wave signal 103 is counted by the time counting circuit, so that the same bit in the signal of the laser disk 100 is continuous. Calculate the number of times.

When the time counting circuit is used for the application as shown in FIG. 13, a time counting circuit having high time resolution and high coincidence accuracy between the count value and the real time is required. In order to reproduce the actual image data of the laser disk, a time counting circuit having a time resolution of 0.3 ns and an accuracy of coincidence between the count value and the real time within ± 10% is required. Such high time resolution and time measurement accuracy can be realized only by the time counting circuit according to the present embodiment.

[0126]

As described above, in the time counting circuit according to the present invention, even if the oscillation frequency of the delay circuit ring shifts due to fluctuations in the power supply voltage or the like, the time measurement accuracy does not decrease, and the real time and the time data are Since the linearity is compensated, highly accurate time data can be stably obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a time counting circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a time correction method according to the first embodiment of the present invention.

3 is a circuit diagram showing a detailed configuration of a first signal processing circuit 9 in the time counting circuit shown in FIG.

4 is a circuit diagram showing a detailed configuration of a second signal processing circuit 20 in the time counting circuit shown in FIG.

5 is a circuit diagram showing a detailed configuration of a third signal processing circuit 22 in the time counting circuit shown in FIG.

6A and 6B are diagrams for explaining a first synchronizing circuit 21 and a second synchronizing circuit 25 in the time counting circuit shown in FIG. 1, where FIG. 6A is a circuit diagram showing a detailed configuration, and FIG. FIG. 6 is a timing chart showing the operation.

7 is a circuit diagram showing another configuration of a third signal processing circuit 22 in the time counting circuit shown in FIG.

FIG. 8 is a circuit diagram showing a configuration of a modified example of the time counting circuit according to the first embodiment of the present invention, which is an example of the time counting circuit in which the PLL is not configured.

FIG. 9 shows a PLL (Phase) according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a (Locked Loop) circuit.

10 is a diagram showing a VCO (Volt in the PLL circuit shown in FIG. 9;
FIG. 3 is a circuit diagram showing a detailed configuration of an age controlled oscillator (voltage controlled oscillator) 70.

FIG. 11 is a diagram for explaining the characteristics of the PLL circuit shown in FIG.

FIG. 12 is a diagram for explaining the characteristics of the PLL circuit shown in FIG. 9.

FIG. 13 is a diagram showing an application example of the time counting circuit according to the present invention, and is a diagram for explaining a method of reading a signal recorded on an optical disc.

FIG. 14 is a circuit diagram showing a configuration of a conventional time counting circuit.

FIG. 15 is a block diagram showing a configuration of a conventional PLL circuit.

16A and 16B are diagrams for explaining a change in delay time due to a power supply voltage change, FIG. 16A is a graph showing a relationship between a power supply voltage change and a voltage applied to a current source, and FIG. 16B is a change in delay time. It is a graph which shows.

FIG. 17 is a diagram for explaining control of delay time by a PLL circuit using a secondary LPF.

FIG. 18 is a diagram for explaining control of delay time by a PLL circuit using a first-order LPF.

[Explanation of symbols]

3 Inverter ring (delay circuit ring) 5 First flip-flop string (first holding circuit string) 8 First encoder 9 First signal processing circuit 13 Phase comparison circuit 14 Oscillation frequency control circuit 17 Second Flip-Flop Sequence (Second Holding Circuit Sequence) 19 Second encoder 20 Second signal processing circuit 22, 22A Third signal processing circuit (correction circuit) 58 ROM (storage means) 70 VCO (voltage controlled oscillator) 72 Phase comparison circuit 73 Charge pump circuit 74 LPF (low pass filter) 75 First control circuit 76 Second control circuit 78 Second power supply circuit (constant voltage power supply circuit) 79 differential inverter P1 PMOS transistor (second current source) P2 PMOS transistor (first current source) N2, N3 NMOS transistor (load resistance element)

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-9-64742 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G04F 10/06 G01R 29/02 H03K 3 / 03 H03L 1/00

Claims (11)

(57) [Claims] 1. A delay circuit ring comprising a plurality of delay circuits connected in a ring shape, wherein signal transitions circulate due to oscillation, each delay circuit of the delay circuit ring at a transition timing of a pulse signal to be measured. In a time counting circuit that calculates time data representing the pulse interval of the pulse signal to be measured based on the output signal of, the oscillation frequency of the delay circuit ring is stabilized with reference to a reference clock signal whose frequency is constant. A controlling PLL (Phase Lock Loop) is configured, and correction data used for correcting the time data is calculated based on the output signals of the delay circuits of the delay circuit ring at the transition timing of the reference clock signal. Then, the time counting circuit is characterized in that the time data is corrected using the calculated correction data. 2. A delay circuit ring composed of a plurality of delay circuits connected in a ring shape, in which signal transitions are circulated by oscillation, and a pulse signal to be measured as an output signal of each delay circuit constituting the delay circuit ring. Represents a pulse interval of the pulse signal to be measured, based on a first holding circuit row composed of a plurality of holding circuits which holds and outputs at the timing of the transition, and an output signal of the first holding circuit row. A phase of a reference clock signal having a constant frequency and an oscillation output signal of the delay circuit ring is compared with a first arithmetic circuit for calculating time data, and the reference clock signal and the oscillation output signal of the delay circuit ring are compared with each other. And a phase comparison circuit that outputs a phase difference detection signal that represents the phase difference of the delay circuit ring, and controls the oscillation frequency of the delay circuit ring according to the phase difference detection signal output from the phase comparison circuit An oscillation frequency control circuit for controlling the oscillation frequency of the delay circuit ring based on the reference clock signal by the phase comparison circuit, the oscillation frequency control circuit, and the delay circuit ring. A second holding circuit array including a plurality of holding circuits for holding and outputting the output signals of the respective delay circuits forming the delay circuit ring at the transition timing of the reference clock signal; On the basis of the output signal of the second holding circuit array, the first
A second arithmetic circuit for calculating correction data used for correcting the time data calculated by the second arithmetic circuit; and the time data calculated by the first arithmetic circuit, calculated by the second arithmetic circuit. A time counting circuit, comprising: a correction circuit that performs correction using correction data. 3. The time counting circuit according to claim 2, wherein the correction circuit stores in advance data to be used for calculation for correction in correction data obtained by the second calculation circuit. A time counting circuit comprising: 4. A delay circuit ring comprising a plurality of delay circuits connected in a ring shape, in which signal transitions are circulated by oscillation, and a pulse signal to be measured is an output signal of each delay circuit constituting the delay circuit ring. And a holding circuit string consisting of a plurality of holding circuits that hold at a transition timing, the time representing the pulse interval of the pulse signal of the measurement target based on the output signal of each delay circuit held by the holding circuit string In a time counting circuit for calculating data, a PLL (phase-locked loop) that stably controls the oscillation frequency of the delay circuit ring is configured with reference to a reference clock signal whose frequency is constant, and a low-pass that configures the PLL. The time counting circuit, wherein the filter is a first-order low-pass filter. 5. A delay circuit ring comprising a plurality of delay circuits connected in a ring shape, in which signal transitions are circulated by oscillation, and a pulse signal to be measured is an output signal of each delay circuit forming the delay circuit ring. And a holding circuit string consisting of a plurality of holding circuits that hold at a transition timing, the time representing the pulse interval of the pulse signal of the measurement target based on the output signal of each delay circuit held by the holding circuit string In a time counting circuit for calculating data, the phase of a reference clock signal having a constant frequency and the oscillation output signal of the delay circuit ring are compared, and the phase difference between the reference clock signal and the oscillation output signal of the delay circuit ring is compared. And a phase comparison circuit that outputs a phase difference detection signal that represents the phase difference detection signal output from the phase comparison circuit. An oscillation frequency control circuit that controls the number of oscillations, and a PLL (phase lock) that stably controls the oscillation frequency of the delay circuit ring with the reference clock signal as a reference by the phase comparison circuit, the oscillation frequency control circuit, and the delay circuit ring. Loop) is configured, and each delay circuit that constitutes the delay circuit ring has a first current source and a second current source, and is delayed by the sum of the current amounts of the first current source and the second current source. The time is determined, and the first current source controls the amount of current by the oscillation frequency control circuit that constitutes the PLL, while the second current source controls the amount of current by the constant voltage power supply circuit. A time counting circuit characterized in that 6. The time counting circuit according to claim 5, wherein each delay circuit forming the delay circuit ring uses a transistor whose gate voltage is an output voltage of the oscillation frequency control circuit as the first current source. A time counting circuit, which is a differential inverter having a transistor having a gate voltage that is an output voltage of the constant voltage power supply circuit as the second current source. 7. A delay circuit ring composed of a plurality of delay circuits connected in a ring shape, in which signal transitions are circulated by oscillation, and a pulse signal to be measured as an output signal of each delay circuit constituting the delay circuit ring. And a holding circuit string consisting of a plurality of holding circuits that hold at a transition timing, the time representing the pulse interval of the pulse signal of the measurement target based on the output signal of each delay circuit held by the holding circuit string In a time counting circuit for calculating data, a PLL (Phase Lock Loop) for stably controlling the oscillation frequency of the delay circuit ring is configured based on a reference clock signal having a constant frequency, and the delay circuit ring is configured. Each delay circuit that has a current source and a load resistance element that serves as a resistance to the output current of the current source, the current amount of the current source and The delay time is determined by the resistance value of the load resistance element, and the PLL compares the phases of the reference clock signal and the oscillation output signal of the delay circuit ring to obtain the reference clock signal and the delay circuit. A phase comparison circuit that outputs a phase difference detection signal that represents a phase difference from the oscillation output signal of the ring, and each delay circuit that constitutes the delay circuit ring based on the phase difference detection signal output from the phase comparison circuit A first control circuit for controlling the amount of current of a current source included in the delay circuit ring, the fluctuation of voltage applied to the delay circuit ring and the first control circuit, and the oscillation frequency of the delay circuit ring due to the fluctuation of the voltage. And a second control circuit for controlling the resistance value of the load resistance element included in each delay circuit constituting the delay circuit ring so that the change of Time counting circuit to be. 8. The time counting circuit according to claim 7, wherein each delay circuit of the delay circuit ring has a transistor whose gate voltage is an output voltage of the first control circuit as the current source, and 2. A time counting circuit, which is a differential inverter having a transistor having the gate voltage of the output voltage of the control circuit 2 as the load resistance element. 9. A delay circuit ring composed of a plurality of delay circuits connected in a ring shape, in which signal transitions are circulated by oscillation, and a pulse signal to be measured as an output signal of each delay circuit constituting the delay circuit ring. Represents a pulse interval of the pulse signal to be measured, based on a first holding circuit row composed of a plurality of holding circuits which holds and outputs at the timing of the transition, and an output signal of the first holding circuit row. It comprises a first arithmetic circuit for calculating time data, and a plurality of holding circuits for holding and outputting the output signals of the respective delay circuits constituting the delay circuit ring at the transition timing of the reference clock signal whose frequency is constant. A second holding circuit array, and the first holding circuit array based on an output signal of the second holding circuit array
A second arithmetic circuit for calculating correction data used for correcting the time data calculated by the second arithmetic circuit; and the time data obtained by the first arithmetic circuit, obtained by the second arithmetic circuit. A time counting circuit, comprising: a correction circuit that performs correction using correction data. 10. A PLL (phase-locked loop) circuit for stably controlling an oscillation frequency of a voltage controlled oscillator, wherein a phase of a reference clock signal having a constant frequency and an oscillation output signal of the voltage controlled oscillator are compared, A phase comparison circuit that outputs a phase difference detection signal representing a phase difference between the reference clock signal and the oscillation output signal of the voltage controlled oscillator, and the voltage based on the phase difference detection signal output from the phase comparison circuit. An oscillation frequency control circuit for controlling the frequency of a controlled oscillator, wherein the voltage controlled oscillator has first and second current sources, and the voltage controlled oscillator has a sum of current amounts of the first and second current sources. The delay time is determined, and the first current source has a current amount controlled by the oscillation frequency control circuit, while the second current source has a constant voltage power supply circuit. PLL circuit, characterized in that the flow rate is controlled. 11. A PLL (phase-locked loop) circuit for stably controlling an oscillation frequency of a voltage controlled oscillator, wherein the voltage controlled oscillator includes a current source and a load resistance element serving as a resistance to an output current of the current source. The delay time is determined by the current amount of the current source and the resistance value of the load resistance element, and the phase of the reference clock signal having a constant frequency and the oscillation output signal of the voltage controlled oscillator. And a phase comparison circuit that outputs a phase difference detection signal indicating a phase difference between the reference clock signal and the oscillation output signal of the voltage controlled oscillator, based on the phase difference detection signal output from the phase comparison circuit. And a first control circuit for controlling the amount of current of a current source included in the voltage controlled oscillator, and fluctuations in voltage applied to the voltage controlled oscillator and the first control circuit. A second control circuit for detecting and controlling the resistance value of the load resistance element of the voltage controlled oscillator so that the change of the oscillation frequency of the voltage controlled oscillator due to the fluctuation of the voltage is suppressed. Characteristic PL
L circuit.