JP2013247609A - Clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generation circuit that minimizes an offset value from 180 degrees of a phase difference between two clock signals.SOLUTION: The clock generation circuit includes: an oscillator 1 in which an offset value from 180 degrees of a phase difference between clock signals φP, φN depends on the value of a data code Dcnt; a phase difference detector 2 for outputting a value of data code Perr depending on the offset value; and a calibrator 11 for setting the value of the data code Dcnt such that the value of the data code Perr becomes a minimum value. The phase difference detector 2 includes a time-digital converter 6 for outputting a value of data code Ddc depending on a phase difference between the clock signal φP or φN and a clock signal /φN or /φP.

Description

  The present invention relates to a clock generation circuit and can be suitably used for, for example, a clock generation circuit that generates a differential clock signal.

  Conventionally, an oscillator that outputs a differential clock signal is mounted on a mobile terminal such as a mobile phone. The differential clock signal includes two clock signals complementary to each other (see, for example, Patent Document 1).

  Patent Document 2 discloses a voltage controlled oscillator that outputs two clock signals that are 90 degrees out of phase with each other. In this voltage controlled oscillator, a phase shifter is provided for setting the phase difference between two clock signals to about 90 degrees. A voltage of a level corresponding to an offset value from 90 degrees of the phase difference between the two clock signals is generated by the phase detector, and the output voltage of the phase detector is smoothed and amplified to become the control voltage of the phase shifter. .

  Patent Document 3 discloses a phase-locked loop circuit that generates a clock signal synchronized with a reference clock signal. In this phase-locked loop circuit, the clock signal generated by the digitally controlled oscillator is divided by a frequency divider. The time difference between the clock signal divided by the frequency divider and the reference clock signal is converted into a data code by the time-digital converter. The value of the data code generated by the time-to-digital converter is integrated by the decoder to become a control signal for the digitally controlled oscillator.

JP 2010-4112 A JP-A-3-35605 JP 2010-206679 A

  In Patent Document 1, when the phase difference between the two clock signals included in the differential clock signal deviates from 180 degrees, there is a problem in that the characteristics of the subsequent circuit of the oscillator deteriorate.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, in the clock generation circuit of the present application, an offset value from 180 degrees of the phase difference between two clock signals is detected by a phase difference detector including a time-digital converter, and the detected offset value is Calibrate the oscillator to the minimum value.

  According to one embodiment, the offset value from 180 degrees of the phase difference between the two clock signals can be minimized.

It is a circuit block diagram which shows the structure of the clock generation circuit by Embodiment 1 of this application. FIG. 2 is a circuit block diagram illustrating a configuration of the oscillator illustrated in FIG. 1. It is a circuit block diagram which shows the structure of the time-digital converter shown in FIG. It is a time chart which shows operation | movement of the time-digital converter shown in FIG. It is a time chart which shows operation | movement of the phase difference detector shown in FIG. It is a circuit block diagram which shows the structure of the calibrator shown in FIG. It is a time chart which shows operation | movement of the calibrator shown in FIG. It is a circuit diagram which shows the principal part of the clock generation circuit by Embodiment 2 of this application. It is a circuit diagram which shows the principal part of the clock generation circuit by Embodiment 3 of this application.

[Embodiment 1]
The clock generation circuit according to the first embodiment of the present application includes an oscillator 1, a phase difference detector 2, and a calibrator 11, as shown in FIG. The oscillator 1 outputs a differential clock signal including two clock signals CLKP and CLKN complementary to each other. The clock signals CLKP and CLKN are used for signal modulation and demodulation in a mobile phone, for example. The offset value from 180 degrees of the phase difference between the clock signals CLKP and CLKN changes according to the value of the data code Dcnt.

  The oscillator 1 outputs two clock signals φP and φN that are complementary to each other. Clock signals φP and φN have the same phase as clock signals CLKP and CLKN, respectively. The clock signals φP and φN are used to set the offset value from 180 degrees of the phase difference between the clock signals CLKP and CLKN to the minimum value.

  As shown in FIG. 2, the oscillator 1 includes an inductor 20, a tracking capacitor 21, an offset compensation capacitor 22, N-channel MOS transistors 23 and 24, a resistance element 25, and buffers 26 to 29.

  One terminal 20a of the inductor 20 is connected to the output node N1, its intermediate terminal 20b is connected to the line of the power supply voltage VDD, and the other terminal 20c is connected to the output node N2. The inductance between the terminals 20a and 20b and the inductance between the terminals 20b and 20c are substantially equal. The tracking capacitor 21 is a variable capacitor and is connected between the output nodes N1 and N2. By adjusting the capacitance value of the tracking capacitor 21, the oscillation frequency of the oscillator 1 can be adjusted.

  The offset compensation capacitor 22 is a variable capacitor, and is connected between the output node N1 and the ground voltage VSS line. The capacitance value of the offset compensation capacitor 22 changes according to the value of the data code Dcnt. By adjusting the capacitance value of the offset compensation capacitor 22, the offset value from 180 degrees of the phase difference between the clock signals φP and φN can be adjusted.

  N channel MOS transistors 23 and 24 have their drains connected to output nodes N1 and N2, respectively, their gates connected to output nodes N2 and N1, respectively, and their sources connected to each other. Resistance element 25 is connected between the sources of N-channel MOS transistors 23 and 24 and the line of ground voltage VSS.

  When the power supply voltage VDD is turned on, the oscillator 1 oscillates at a frequency determined by the inductance of the inductor 20 and the capacitance value of the tracking capacitor 21. A clock signal having an oscillation frequency appears at the output node N1, and a clock signal complementary to the clock signal appearing at the output node N1 appears at the output node N2. The clock signal appearing at the output node N1 is buffered by the buffer 28 to become the clock signal CLKN, and is buffered by the buffer 29 to become the clock signal φN. The clock signal appearing at output node N2 is buffered by buffer 26 to become clock signal CLKP, and buffered by buffer 27 to become clock signal φP.

  Therefore, the clock signals CLKP and CLKN are complementary signals. Clock signals φP and φN have the same phase as clock signals CLKP and CLKN, respectively. The phase difference between the clock signals φP and φN changes according to the capacitance value of the offset compensation capacitor 22. For example, when the capacitance value of the offset compensation capacitor 22 is increased, the level changes of the clock signals CLKN and φN are delayed, and the phases of the clock signals CLKN and φN are delayed.

  The offset compensation capacitor 22 may be connected to the node N2 instead of the node N1. In this case, for example, when the capacitance value of the offset compensation capacitor 22 is increased, the level changes of the clock signals CLKP and φP are delayed, and the phases of the clock signals CLKP and φP are delayed.

  Returning to FIG. 1, the phase difference detector 2 detects an offset value from 180 degrees of the phase difference between the clock signals φP and φN, and outputs a data code Perr having a value corresponding to the detected offset value. That is, the phase difference detector 2 includes inverters 3 and 4, switching circuits 5 and 7, a time-to-digital converter (TDC) 6, registers 8 and 9, and a subtractor 10. Inverter 3 inverts clock signal φN to generate clock signal / φN. Inverter 4 inverts clock signal φP to generate clock signal / φP.

  Four input terminals 5a to 5d of switching circuit 5 receive clock signals φP, / φN, φN and / φP, respectively. The two output terminals 5e and 5f of the switching circuit 5 are connected to the start terminal 6a and the stop terminal 6b of the time-digital converter 6, respectively.

  When switching signal SW is at “H” level, terminals 5a and 5e are conductive and terminals 5b and 5f are conductive, and clock signals φP and / φN are applied to start terminal 6a and stop terminal 6b, respectively. When switching signal SW is at "L" level, terminals 5c and 5e are conducted, terminals 5d and 5f are conducted, and clock signals φN and / φP are applied to start terminal 6a and stop terminal 6b, respectively. The switching signal SW is given to the reset terminal 6 c of the time-digital converter 6.

  The time-digital converter 6 is reset in response to each of the rising edge and the falling edge of the switching signal SW. The time-digital converter 6 has a value corresponding to the time difference between the rising edge of the clock signal φP or φN applied to the start terminal 6a and the rising edge of the clock signal / φN or / φP applied to the stop terminal 6b. The data code Ddc is output.

  As shown in FIG. 3, the time-digital converter 6 includes (n−1) buffers 30, n flip-flops 31, and a decoder 32 connected in series. However, n is an integer of 2 or more. FIG. 3 shows a state in which clock signals φP and / φN are applied to the start terminal 6a and the stop terminal 6b, respectively.

  The buffer 30 at the first stage delays the clock signal a0 (φP in FIG. 3) given through the start terminal 6a by a predetermined time and outputs the clock signal a1. The second-stage buffer 30 delays the clock signal a1 by a predetermined time and outputs the clock signal a2. Similarly, the final stage buffer 30 delays the clock signal an-2 by a predetermined time and outputs the clock signal an-1.

  Data input terminals (D) of the n flip-flops 31 receive clock signals a0 to an-1. Both of the clock terminals (C) of the n flip-flops 31 receive the clock signal s0 (/ φN in FIG. 3) supplied via the stop terminal 6b. Data output terminals (Q) of the n flip-flops 31 are connected to the decoder 32. The decoder 32 generates a data code Ddc based on the output signals b0 to bn-1 of the n flip-flops 31. Each buffer 30, each flip-flop 31, and decoder 32 are reset in response to the rising edge and the falling edge of switching signal SW.

  4A to 4F are time charts showing the operation of the time-digital converter 6. 4A to 4F, when the clock signal a0 rises from the “L” level (0) to the “H” level (1) at a certain time t0, the delay time Td of the buffer 30 from that time t0. After the elapse of time, the clock signal a1 is raised from the “L” level (0) to the “H” level (1). Similarly, the clock signals a2 to an-1 are sequentially raised from the “L” level (0) to the “H” level (1) one by one. The time from when the clock signal a0 is raised to the “H” level to when the clock signal an−1 is raised to the “H” level is n × Td. This time n × Td is set to a time shorter than the half cycle of the clock signal a0. The delay time Td of the buffer 30 is set to a time sufficiently longer than the absolute value of the difference between the delay time of the inverter 3 and the delay time of the inverter 4.

  When the clock signal s0 rises from the “L” level to the “H” level, the n flip-flops 31 hold and output the logic levels of the clock signals a0 to an−1, respectively. As a result, the output signals b0 to bn-1 of the n flip-flops 31 are, for example, 11 ... 11000 ... 0. The decoder 32 generates a data code Ddc based on the signals b0 to bn-1. FIG. 4F shows a case where the value of the data code Ddc is “18”.

  Returning to FIG. 1, the input terminal 7a of the switching circuit 7 receives the data code Ddc, and the output terminals 7b and 7c are connected to the registers 8 and 9, respectively. When switching signal SW is at “H” level, terminals 7 a and 7 b are brought into conduction, and data code Ddc generated by time-digital converter 6 is applied to register 8. When switching signal SW is at “L” level, terminals 7 a and 7 c are brought into conduction, and data code Ddc generated by time-digital converter 6 is applied to register 9.

  Each of the registers 8 and 9 holds and outputs the data code Ddc supplied from the time-to-digital converter 6. The value of the output code PHa of the register 8 indicates the sum Ti + dt of the delay time Ti of the inverter 3 and the time dt between the rising edge of the clock signal φP and the falling edge of the clock signal φN. The value of the output code PHb of the register 9 indicates the difference Ti−dt between the delay time Ti of the inverter 4 and the time dt between the rising edge of the clock signal φP and the falling edge of the clock signal φN.

  The subtractor 10 obtains a difference Perr = PHa−PHb between the output code PHa of the register 8 and the output code PHb of the register 9. The value of the output code Perr of the subtracter 10 indicates Ti + dt− (Ti−dt) = 2dt.

  5A to 5I are time charts showing the operation of the phase difference detector 2. FIG. 5A to 5I, when the switching signal SW is at the “L” level, the clock signal φN, / φP is given to the time-digital converter 6 by the switching circuit 5. In this case, the value of the output code Ddc of the time-digital converter 6 is a value corresponding to the time Ti-dt between the rising edges of the clock signals φN and / φP. Register 9 holds and outputs data code Ddc supplied through switching circuit 7. The value of the output code PHb of the register 9 is Ti-dt.

  When the switching signal SW rises from the “L” level to the “H” level, the time-digital converter 6 is reset and the value of the data code Ddc becomes zero. In response to the rising edge of the switching signal SW, the register 9 holds the data code PHb. In response to the rising edge of the switching signal SW, the data code Ddc is supplied to the register 8 via the switching circuit 7. Register 8 holds and outputs data code Ddc provided through switching circuit 7. At this time, the value of the output code PHa of the register 8 is 0. Therefore, the output code Perr of the phase difference detector 2 is -PHb.

  When the switching signal SW rises from the “L” level to the “H” level, the clock signals φP and / φN are supplied to the time-digital converter 6 by the switching circuit 5. In this case, the value of the output code Ddc of the time-digital converter 6 is a value corresponding to the time Ti + dt between the rising edges of the clock signals φP, / φN. Register 8 holds and outputs data code Ddc provided through switching circuit 7. The value of the output code PHa of the register 8 is Ti + dt. As a result, the output code Perr of the phase difference detector 2 becomes PHa−PHb = (Ti + dt) − (Ti−dt) = 2dt.

  The calibrator 11 obtains a data code Ddc that minimizes the absolute value of the data code Perr, and supplies the obtained data code Ddc to the oscillator 1 to offset the phase difference between the clock signals CLKP and CLKN from 180 degrees. To the minimum value. That is, the calibrator 11 includes switching circuits 35 and 37, registers R0 to Rn-1, and a minimum value detector 36 as shown in FIG. The minimum value detector 36 detects a value having the minimum absolute value among the data code values of the registers R0 to Rn-1.

  One terminal 35a of the switching circuit 35 receives the data code Perr from the phase difference detector 2, and the other terminal 35b is connected to the registers R0 to Rn-1. When the calibration instruction signal EN is at the “H” level of the activation level, the terminals 35a and 35b are electrically connected. When the calibration instruction signal EN is at the “L” level of the inactivation level, the terminals 35a and 35b are not connected.

  During the calibration period in which the calibration instruction signal EN is at the “H” level, the value of the data code DA is incremented (+1) from 0 to n−1 at a predetermined cycle. When the value of the data code DA becomes 0, 1, 2,..., N−1, the registers R0, R1, R2,. The activated register R takes in the data code Perr given from the phase difference detector 2 via the switching circuit 35, and holds and outputs the fetched data code Perr. The minimum value detector 36 detects a value having the minimum absolute value among the data code values of the registers R0 to Rn-1, and outputs a register (for example, R2) that outputs the data code of the minimum value. A data code DAm having a value (in this case, 2) corresponding to the selected register is output.

  The input terminal 37 a of the switching circuit 37 receives the data code DA, the input terminal 37 b receives the output code DAm of the minimum value detector 36, and the output terminal 37 c is connected to the oscillator 1. When the calibration instruction signal EN is at the “H” level of the activation level, the terminals 37a and 37c are electrically connected. When the calibration instruction signal EN is at the “L” level of the inactivation level, between the terminals 37b and 37c. Conduct.

  FIGS. 7A to 7E are time charts showing the operation of the calibrator 11. 7A to 7E, at a certain time t0, the calibration instruction signal EN is raised from the “L” level of the non-activation level to the “H” level of the activation level. In response to this, the terminals 35a and 35b of the switching circuit 35 become conductive, and the output code Perr of the phase difference detector 2 is given to the registers R0 to Rn-1. Further, the terminals 37a and 37c of the switching circuit 37 become conductive, and the data code DA is given to the oscillator 1 as the data code Dcnt.

  Further, the value of the data code DA is incremented (+1) from 0 to n−1 at a predetermined cycle. When the value of the data code DA changes from 0 to n-1, the offset value from 180 degrees of the phase difference between the clock signals φP and φN changes in n stages, and the data code Perr having a value corresponding to the n offset values. Are stored in the registers R0 to Rn-1, respectively. The data code DA of the number (in this case, 2) of the register (for example, R2) storing the data code Perr having the minimum absolute value (for example, +1) is the data code DAm from the minimum value detector 36. Is output.

  At time t1, when the value of the data code DA is increased to n−1 and the calibration instruction signal EN is set to the “L” level of the inactivation level, the terminals 35a and 35b of the switching circuit 35 are made non-conductive. In addition, the terminals 37b and 37c of the switching circuit 37 are electrically connected. Thereby, the output code DAm of the minimum value detector 36 is given to the oscillator 1 as the data code Dcnt, and the offset value from 180 degrees of the phase difference between the clock signals φP and φN becomes the minimum value.

  In the first embodiment, since the phase difference detector 2 is configured using the time-digital converter 6, the phase difference between the clock signals φP and φN can be detected accurately and quickly. Further, since the entire phase difference detector 2 can be constituted by a digital circuit, the power supply voltage can be reduced as compared with the case where the phase difference detector is constituted by an analog circuit such as an analog-digital converter or a comparator. be able to.

[Embodiment 2]
FIG. 8 is a circuit diagram showing a main part of the clock generation circuit according to the second embodiment of the present application, and is a diagram to be compared with FIG. Referring to FIG. 8, the clock generation circuit of the second embodiment is different from the clock generation circuit of the first embodiment in that oscillator 1 is replaced with oscillator 40. The oscillator 40 is obtained by replacing the inductor 20 of the oscillator 1 with inductors 41 and 42 and replacing the offset compensation capacitor 22 with an inductor 43 and an offset compensation capacitor 44.

  One terminals of inductors 41 and 42 are both connected to the line of power supply voltage VDD, and the other terminals thereof are connected to output nodes N1 and N2, respectively. The inductor 43 is electromagnetically coupled to the inductor 41. The offset compensation capacitor 44 is a variable capacitor and is connected between the terminals of the inductor 43. The capacitance value of the offset compensation capacitor 44 changes according to the value of the data code Dcnt.

  The phase difference between the clock signals φP and φN changes according to the capacitance value of the offset compensation capacitor 44. For example, when the capacitance value of the offset compensation capacitor 44 is increased, the level changes of the clock signals CLKN and φN are delayed, and the phases of the clock signals CLKN and φN are delayed.

  Also in this second embodiment, the same effect as in the first embodiment can be obtained. Instead of electromagnetically coupling the inductor 43 to the inductor 41, the inductor 43 may be electromagnetically coupled to the inductor. In this case, for example, when the capacitance value of the offset compensation capacitor 44 is increased, the level changes of the clock signals CLKP and φP are delayed, and the phases of the clock signals CLKP and φP are delayed.

[Embodiment 3]
FIG. 9 is a circuit diagram showing a main part of the clock generation circuit according to the third embodiment of the present application, and is a diagram to be compared with FIG. Referring to FIG. 9, the clock generation circuit of the third embodiment is different from the clock generation circuit of the first embodiment in that oscillator 1 is replaced with oscillator 50. The oscillator 50 is obtained by replacing the offset compensation capacitor 22 of the oscillator 1 with capacitors 51 and 52, a variable current source 53, a constant current source 54, N-channel MOS transistors 55 and 56, and resistance elements 57 and 58.

  Capacitor 51 is connected between the gate of N channel MOS transistor 23 and output node N2. Capacitor 52 is connected between the gate of N channel MOS transistor 24 and output node N1. Variable current source 53 and N-channel MOS transistor 55 are connected in series between a power supply voltage VDD line and a ground voltage VSS line. The gate of N channel MOS transistor 55 is connected to its drain. Resistance element 57 is connected between the gates of N channel MOS transistors 23 and 55.

  The variable current source 53 causes a direct current of a level corresponding to the value of the data code Dcnt to flow through the transistor 55. A DC bias voltage V 1 having a value corresponding to the output current of the variable current source 53 is generated at the gate of the transistor 55. The DC bias voltage V <b> 1 is applied to the gate of the transistor 23 through the resistance element 57.

  Constant current source 54 and N-channel MOS transistor 56 are connected in series between a power supply voltage VDD line and a ground voltage VSS line. The gate of N channel MOS transistor 56 is connected to its drain. Resistance element 58 is connected between the gates of N channel MOS transistors 24 and 56.

  The constant current source 54 causes a constant direct current to flow through the transistor 56. A constant DC bias voltage V 2 having a value corresponding to the output current of the constant current source 54 is generated at the gate of the transistor 56. The DC bias voltage V <b> 2 is applied to the gate of the transistor 24 through the resistance element 58.

  When V1> V2, the current drive capability of the transistor 23 is higher than the current drive capability of the transistor 24, and the phase of the clock signal φN advances. When V1 <V2, the current drive capability of the transistor 24 is higher than the current drive capability of the transistor 23, and the phase of the clock signal φP advances. Therefore, by adjusting the value of the data code Dcnt, the offset value from 180 degrees of the phase difference between the clock signals φP and φN can be adjusted.

  In the third embodiment, the same effect as in the first embodiment can be obtained. Needless to say, the variable current source 53 and the constant current source 54 may be interchanged.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  1, 40, 50 oscillator, 2 phase difference detector, 3, 4 inverter, 5, 7, 35, 37 switching circuit, 6 time-digital converter, 8, 9, R register, 10 subtractor, 11 calibrator, 20, 41-43 Inductor, 21 Tracking capacitor, 22, 44 Offset compensation capacitor, 23, 24, 55, 56 N-channel MOS transistor, 25, 57, 58 Resistive element, 26-30 Buffer, 31 Flip-flop, 32 Decoder, 36 Minimum value detector, 51, 52 capacitor, 53 variable current source, 54 constant current source.

Claims (6)

An oscillator that outputs first and second clock signals complementary to each other, and an offset value from 180 degrees of a phase difference between the first and second clock signals varies according to a value of a first data code;
A phase difference detector that receives the first and second clock signals and outputs a second data code having a value corresponding to the offset value;
A calibrator that sets the value of the first data code such that the value of the second data code is a minimum value;
The phase difference detector detects a time between a leading edge of the first clock signal and a leading edge of an inverted signal of the second clock signal, and third data having a value corresponding to the detected time A clock generation circuit including a time-to-digital converter for outputting a code. The phase difference detector is
A first inverter that inverts the first clock signal to generate a third clock signal;
A second inverter that inverts the second clock signal to generate a fourth clock signal;
A switching circuit that receives the first to fourth clock signals and alternately supplies the first and fourth clock signals and the second and third clock signals to the time-digital converter;
The time-to-digital converter is configured to connect the third data code having a value according to the time between leading edges of the first and fourth clock signals and the leading edges of the second and third clock signals. Alternately output a fourth data code of a value according to time,
The phase difference detector is
A first register for holding and outputting the third data code;
A second register for holding and outputting the fourth data code;
The clock generation circuit according to claim 1, further comprising: a subtractor that subtracts the output code of the second register from the output code of the first register and outputs the second data code. The calibrator is
Sequentially changing the value of the first data code from a minimum value to a maximum value in a plurality of stages, and sequentially storing the value of the second data code;
Detecting a value having a minimum absolute value among a plurality of values of the stored second data code;
3. The clock generation according to claim 2, wherein a value of the first data code when the absolute value of the second data code is minimized is obtained, and the first data code having the obtained value is supplied to the oscillator. circuit. The oscillator is
First and second output nodes for outputting the first and second clock signals, respectively;
First and second inductors having one terminal receiving the power supply voltage and the other terminal connected to the first and second output nodes, respectively;
A first capacitor connected between the first and second output nodes;
First and second transistors having their drains connected to the first and second output nodes, respectively, and their gates connected to the second and first output nodes, respectively;
A resistive element connected between the source of the first and second transistors and a reference voltage line;
And a second capacitor connected between the first or second output node and the reference voltage line and having a capacitance value that changes in accordance with a value of the first data code. The clock generation circuit described. The oscillator is
First and second output nodes for outputting the first and second clock signals, respectively;
First and second inductors having one terminal receiving the power supply voltage and the other terminal connected to the first and second output nodes, respectively;
A first capacitor connected between the first and second output nodes;
First and second transistors having their drains connected to the first and second output nodes, respectively, and their gates connected to the second and first output nodes, respectively;
A resistive element connected between the source of the first and second transistors and a reference voltage line;
A third inductor electromagnetically coupled to the first or second inductor;
2. The clock generation circuit according to claim 1, further comprising: a second capacitor connected between terminals of the third inductor and having a capacitance value that changes in accordance with a value of the first data code. The oscillator is
First and second output nodes for outputting the first and second clock signals, respectively;
First and second inductors having one terminal receiving the power supply voltage and the other terminal connected to the first and second output nodes, respectively;
A first capacitor connected between the first and second output nodes;
First and second transistors having their drains connected to the first and second output nodes, respectively;
A resistive element connected between the source of the first and second transistors and a reference voltage line;
Second and third capacitors having one terminal connected to the gates of the first and second transistors, respectively, and the other terminal connected to the second and first output nodes, respectively;
A bias voltage generating circuit that applies a first bias voltage to the gate of the first transistor and applies a second bias voltage to the gate of the second transistor;
The clock generation circuit according to claim 1, wherein the level of the first or second bias voltage changes according to a value of the first data code.

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