JP3359850B2 - Capacitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a mobile phone,
In the circuit section of wireless devices such as car phones, MMIC
(Monolithic Microwave Integrated Circuit) and the like.

[0002]

2. Description of the Related Art A conventional capacitor formed on an MMIC is disclosed, for example, in "Basics and Applications of Microwave Circuits" (1).
176 pages, February 1, 992, published by Sogo Electronic Publishing Co.)
As shown in the diagram on page 177, the first example is the MIM (Metal Insulator Meta) shown in FIG.
l) There is a capacitor, and a second example is an interdigital capacitor shown in FIG.

The MIM capacitor shown in FIG. 8A has a structure in which two conductors 1 and 2 are laminated and opposed on a substrate 4 with a dielectric layer 3 interposed therebetween, and a large capacitance can be obtained with a relatively small pattern area. There is a feature that is. Since the MIM capacitor used in the MMIC generally uses a thin film process, the dielectric layer may be a dielectric layer (eg, SiO ₂ ) grown by vapor deposition or a polyimide resin paste may be formed on a substrate. The dielectric layer 3 is formed of resin by coating on the conductor thus formed, or a dielectric paste is coated on the conductor formed on the substrate using a sol-gel method or the like, and then the ceramic dielectric layer is formed by a firing step. Can be formed. Since the dielectric layer connected by the above-described method can be formed with a thickness of about several μm, it is easy to obtain a large capacitance with a small area.

On the other hand, an interdigital capacitor according to a second conventional example shown in FIG. 8B has a structure in which comb-shaped electrodes 5 and 6 are opposed on the same surface of a substrate 4. That is, the comb-shaped electrodes 5 and 6 have a plurality of element electrodes 7 and 8, respectively, and the plurality of element electrodes 7 and 8 face each other on the surface of the substrate 4 in the plane direction to form a capacitance. . Normally, the interdigital capacitor used for the MMIC is such that a conductor film on one surface is formed on the surface of the substrate 4 by sputtering or the like, and a photoresist is applied to the conductor film.
A pattern to be formed is exposed and developed on a photoresist, and a portion from which a conductor is removed is etched and formed. Therefore,
Since the interdigital electrodes 5 and 6 of the interdigital capacitor are formed in the same process, the interdigital capacitor has a structure in which variation in capacitance value formed by mass production is small.

[0005]

[Problems to be solved by the invention]

(1) In the MIM capacitor shown in FIG. 8A as the first example, the capacitance value varies depending on the thickness of the dielectric layer 3 formed between the capacitor electrodes 1 and 2. For example, in the case of an MIM capacitor formed of the dielectric layer 3 having a thickness of 5 μm,
Even if the thickness of the dielectric layer 3 can be formed with an accuracy of ± 0.5 μm, the formed capacitance value will vary by ± 10%. The accuracy of a capacitor used in a filter circuit or the like depends on the accuracy of the filter, but it is usually necessary to keep the capacitance within a range of about ± 5% of a target value, and a higher accuracy is required. In some cases. Therefore, in order to realize the above accuracy, it is necessary to set the film thickness of the dielectric layer 3 to ± 0.25 μm or less. However, in order to form the dielectric layer 3 within the above-mentioned accuracy during mass production, the film thickness tends to fluctuate in any of the above-described methods of forming the dielectric layer 3, and in particular, as the thickness of the dielectric layer 3 becomes thinner, However, there is a problem that the capacitance value to be changed easily changes. (2) The interdigital capacitor shown in FIG. 8B as the second example has a structure in which a stable capacitance value can be obtained during mass production as described above, but a large capacitance value is difficult to obtain.
In order to obtain a large capacitance, it is necessary to enlarge the pattern of the comb-shaped electrodes 5 and 6, and this structure is not suitable in a narrow pattern area. Also, as a method of increasing the capacitance value,
It is necessary to design the gap between the element electrodes 7 and 8 of the comb electrodes 5 and 6 facing each other on the surface of the substrate 4 to be narrow.

However, since the gap between the element electrodes 7 and 8 is formed by etching as described above, if the gap is made extremely narrow, the etching conditions become severe. Since the conductor cannot be sufficiently etched, each of the element electrodes 7, 8
There is a problem in that the electrode electrodes 7 and 8 are too thin due to a short circuit between them, and conversely, the etching is too thin, and the element electrodes 7 and 8 are lost depending on the location, resulting in variations in electrode formation.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a structure of a MMIC capacitor in which the capacitance in the area occupied by the capacitor pattern can be increased and the variation in capacitance value during mass production can be reduced. The purpose of the present invention is to provide a capacitor.

[0008]

In order to achieve this object, a capacitor according to the present invention comprises a lower electrode having a substantially comb shape formed on a substrate, a dielectric layer formed on the lower electrode, and a dielectric layer formed on the lower electrode. it forms a upper layer electrode having a substantially comb on the body layer, the lower electrode and one of the region of the margin between the elements electrodes of the upper electrode, it is disposed the other of each element electrodes, each The element electrode is located at the corner of the cross section.
And facing each other via the dielectric layer (claim 1).

Further, the capacitor of the present invention comprises a lower electrode formed on a substrate, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer. Either one of the upper layer electrodes has a ladder shape in which frame-shaped element electrodes are continuous, and the other electrode has a comb shape,
Each element electrodes of said other of the comb-shaped electrode is on the margin of the region in one of the frame-shaped element electrodes, each d
The element electrode is formed at the corner of the cross section by the dielectric layer.
Wherein the opposed through (claim 2).

The capacitor according to the present invention comprises a lower electrode formed on a substrate, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer. One of the upper-layer electrodes has a plurality of annular portions, and the element electrode of the other electrode is disposed in a blank area in the annular portion of the one electrode , and each element electrode
The poles are paired through the dielectric layer at the corners of the cross section.
Characterized by direction (claim 3).

In the capacitor according to the present invention, the width of the margin of the one electrode is W1, the width of the other element electrode disposed in the margin is W2, and the width of the other electrode from the design position of the pattern of the other electrode. The assumed maximum deviation is ± W3, and W1
The relationship of ≧ W2 + 2 · W3 is established (claim 4).

Further, in the capacitor according to the present invention, the substrate is made of a ceramic dielectric, and the substrate has an external connection electrode connected to an electrode on a motherboard (claim 5).

In the capacitor according to the present invention, the external connection electrode is formed on a surface of the substrate on which the lower electrode and the upper electrode are formed (claim 6).

In the capacitor according to the present invention, a solder precoat or a solder bump is formed on the external connection electrode.

Further, the capacitor of the present invention is characterized in that the lower layer electrode and the upper layer electrode are each formed by using a photolithography technique.

Further, the capacitor of the present invention is characterized in that the dielectric layer is formed of a resin material.

Further, the capacitor of the present invention is characterized in that a high dielectric constant material composed of at least one of ceramic powder, glass powder and high dielectric constant resin powder is dispersed and mixed in the resin material. (Claim 10).

In the capacitor according to the present invention, the dielectric layer is formed by applying and firing a dielectric paste.

[0019]

According to the first aspect of the present invention, the space between the element electrodes of one of the comb-shaped electrodes (lower-layer electrodes or upper-layer electrodes) or in a space within the element electrodes is reduced by the other comb-shaped electrode (upper-layer electrode or lower-layer electrode). In the configuration in which the element electrodes are arranged, even if the opposing comb-shaped electrode is shifted, one side of the element electrode of one comb-shaped electrode is close to the corresponding element electrode of the other comb-shaped electrode. The capacitance value increases, but the other side moves away from the element electrode of the other comb-shaped electrode corresponding to the other comb-shaped electrode and decreases the capacitance value. Variations in the capacitance value due to the displacement are reduced, and a capacitor with a small variation in the capacitance value can be provided.

Further, since a dielectric layer is interposed between the lower electrode and the upper electrode, there is no danger of short-circuiting even if both electrodes are brought close to each other. Is obtained.

[0021] Claims 2 and 3 exhibit the same function as that of claim 1.

[0022]

FIG. 1A is a perspective view showing an embodiment of a capacitor according to the present invention, FIG. 1B is a perspective view showing an electrode pattern of the capacitor, and FIG. FIG. 2B is a sectional view of the capacitor according to the embodiment, and FIG.

As shown in FIGS. 1A, 1B and 2A, the capacitor of this embodiment has a comb-shaped lower electrode 11 serving as one electrode of a capacitor on a substrate 14. A dielectric layer 13 is formed thereon, and a comb-shaped upper electrode 12 serving as the other electrode is further formed thereon.

The lower electrode 11 and the upper electrode 12 have a plurality of element electrodes 15 and 16, respectively.
Are formed in the area of each blank formed between the element electrodes 15 of the lower electrode 11, and each element electrode 15 of the lower electrode 11 is formed between the element electrodes 16 of the upper electrode 12. The structure is formed below the area of each margin formed at the bottom. Soshi
The element electrodes of the lower electrode 11 and the upper electrode 12 are disconnected.
Opposed at the corner of the surface via the dielectric layer 13
I do.

As described above, the lower electrode 11 and the upper electrode 1
In the margin of one of the two element electrodes, the other element
The electrodes are opposed to each other with the dielectric layer 13 interposed therebetween.
By making the corners of the cross section of the element electrode face each other with the dielectric layer 13 interposed therebetween, as shown in FIG. 2B, the distances Wa and Wb between the element electrodes 15 and 16 are designed to be extremely small (Wa = Wb), and the obtained capacitance of the formed capacitor can be increased. In addition, if the dielectric layer 13 is made of a material having a high dielectric constant, the acquired capacity can be naturally increased. On the other hand, structurally, since the electrodes 11 and 12 do not face each other in the stacking direction, the capacitance value of the formed capacitor is smaller than that when the electrodes are directly opposed in the stacking direction. Not affected by variations in thickness.

However, in the capacitor according to the present invention, since the lower electrode 11 and the upper electrode 12 are not formed at the same time, the element electrode 15 on the lower side of the dielectric layer 13 and the element electrode 16 May vary. Then, there is a possibility that the capacitance value formed due to the shift varies. In this case, regarding the relationship between the width W1 of the blank portion between the element electrodes 15 of the lower layer electrode 11 and the width W2 of each element electrode 16 of the upper layer electrode 12, the maximum positional relationship between the lower layer electrode 11 and the upper layer electrode 12 which occurs during the mass production described above. If the deviation (variation amount) is ± W3 with respect to the design position, W1 ≧ W2 + 2 · W3 may be satisfied.

According to such a relationship, in FIG. 2B, for example, when the element electrode 16 approaches the left element electrode 15 in the drawing due to a pattern shift between the element electrodes 15 Becomes smaller. At this time, the distance Wb between the element electrode 16 and the element electrode 15 on the right side in the drawing increases as Wa decreases. Therefore, the change amount of the capacitance value formed as a whole does not occur or is extremely small. Thus, even if the positional relationship between the lower electrode 11 and the upper electrode 12 fluctuates, the capacitance value formed hardly fluctuates. In addition, the above equation shows that the electrodes 1 forming the capacitor 1
When designing the elements 1 and 12, the distance between the element electrodes 15 and 16 (W
a, Wb) as a variation W3 (Wa = Wb = W3). As a matter of course, in the case of a manufacturing facility with high alignment accuracy, the variation W3 is extremely small, a larger capacitance can be obtained, and a capacitor having a desired capacitance can be formed with a small occupied area. it can.

The width W1 between the element electrodes 15, 15 and the width W2 of the element electrode 16 are set according to the capacity of the manufacturing equipment, the strength of the signal to be handled, and the like. In the present embodiment, the element electrodes 15 on both sides of the lower electrode 11 are located outside the element electrodes 16 of the upper electrode 12, and the lower electrode 11 substantially surrounds the upper electrode 12. A pattern structure may be used.

The capacitor of this embodiment is manufactured by the following steps. In order to form the lower electrode 11 on the substrate 14, a conductive film is formed on the substrate 14. This conductor film is preferably formed of copper having good high-frequency characteristics and less likely to cause electromigration that lowers insulation between insulated conductors. The conductor film is a substrate 14
It is formed by sputtering or the like, but when a ceramic substrate is used as the substrate 14, a conductor paste for a thick film can be applied or printed on the substrate 14 and then fired to form a conductor film. It is.

The comb-shaped lower electrode 11 is formed on the conductive film formed on the substrate 14 by using the photolithography technique. That is, a photoresist is applied to the conductor film, the photoresist is exposed through a photomask formed in a substantially comb shape, the photoresist is developed and fixed, and the portion to be etched of the conductor film is exposed. Is used to etch the conductor. Thus, the lower electrode 11 is formed.

Next, a dielectric layer 13 is formed. The dielectric layer 13 may be resin-based or ceramic-based.
Is applied over the entire surface of the substrate 14 on which is formed, and is cured as it is at a high temperature in the case of a resin system, and then formed into a target pattern by photolithography. In the case of a ceramic material, a dielectric paste is applied to the substrate 14 in the same manner as described above, dried, a target pattern is formed by photolithography, and then fired to obtain the dielectric layer 13. In the case where a ceramic dielectric layer is used and copper is used as the conductor on the substrate 14, the ceramic dielectric layer 13 needs to be fired in a nitrogen atmosphere.

With respect to the surface on which the dielectric layer 13 is formed,
A conductor film for forming the upper electrode 12 is formed. The formation of the upper electrode 12 is performed using the above-described photolithography technique. Also, the material of the upper electrode 12 is preferably copper for the above-described reason, and a conductor film is formed by sputtering or the like. When the ceramic dielectric layer 13 is used, a conductive film can be formed by applying or printing a thick film paste on the surface on which the dielectric layer 13 is formed, and then firing. is there.

FIG. 3A is a perspective view showing another embodiment of the present invention, and FIG. 3B is a perspective view showing an electrode pattern thereof. In this embodiment, the lower electrode 21 formed on the substrate 24 is used.
Is formed in a shape having two sets of comb-shaped electrodes by forming a plurality of element electrodes 25 inwardly from the extraction electrodes 27 on both sides, respectively. The dielectric layer 23 connects the lower electrode 21 to its terminal 28
Cover except for. The upper electrode 22 is formed in a shape in which a plurality of element electrodes 26 are formed in a comb shape on both sides of a central extraction electrode 29 connected to the terminal portion 30. In the same manner as in the above-described embodiment, the element electrode 26 of the upper electrode 22 is disposed in the margin between the element electrodes 25 of the lower electrode 21, and the element electrode 26 of the lower electrode 21 is disposed in the margin between the element electrodes 26 of the upper electrode 22. 25 are arranged.

According to the embodiment shown in FIG. 3, compared with the case where a comb-shaped electrode having an element electrode protruding only on one side is used,
The length of each of the element electrodes 25 and 26 can be shortened. As a result, the inductance value of the element electrode of the comb-shaped electrode decreases, and the self-resonant frequency can be shifted to a higher frequency side.

FIGS. 4A and 4B show FIGS. 3A and 3B, respectively.
In this embodiment, the lower electrode 31 is formed in a ladder-like shape in which the extraction electrodes 27 on both sides are connected by a plurality of element electrodes 35 and the frame portion is continuous. Is formed. On the other hand, the upper electrode 22 is shown in FIG.
Similarly to the embodiment, a plurality of element electrodes 26 are formed in a comb shape on both sides of the central extraction electrode 29. Then, the element electrode 35 of the lower electrode 31
The element electrode 26 of the upper electrode 22 is arranged in a space between them, and the element electrode 35 of the lower electrode 31 is arranged in a space between the element electrodes 26 of the upper electrode 22. However, the extraction electrode 29 at the center of the upper electrode 22 opposes the element electrode 35 of the lower electrode 31 in the vertical direction via the dielectric layer 23.

The structure shown in FIG. 4 can be applied when the capacitance value is relatively large or when the accuracy of the capacitance value is not strictly required. In the embodiment of FIG. 4, the inductance value of the element electrode 35 is further reduced as compared with the case of FIG.
As a result, the resonance frequency increases, so that the restriction on the operating frequency due to the resonance frequency is relaxed.

FIG. 5A is a perspective view showing another embodiment of the present invention, and FIG. 5B is a perspective view showing an electrode pattern thereof. In this embodiment, the lower electrode 4 is formed on the substrate 24 in such a manner that a plurality of open or closed annular portions 44 are continuous as shown.
The lower electrode 41 is covered with the dielectric layer 23 except for the terminal portion 48 on the lower electrode 41, and a rectangular element electrode 46 of the upper electrode 42 is formed in a margin 45 in the annular portion 44 of the lower electrode 41.
Are arranged, and each element electrode 46 and the extraction electrode 47 of the upper layer electrode 42 are connected by a connecting portion 49 that straddles a part of the lower layer electrode 41. The annular portion 44 can be not only a square but also another polygon or a circle.

In the embodiment shown in FIG. 5, even when the pattern of the upper electrode 42 is shifted with respect to the lower electrode 41, the variation of the capacitance value is small as in the above embodiment. The capacitor of this embodiment can also be used as a capacitor for fine adjustment by selectively cutting off the connection portion 49 between the element electrode 46 and the extraction electrode 47 connected to the terminal portion 50.

FIG. 6A is a plan view showing another embodiment of the capacitor of the present invention, and FIG.
FIG. 7 is a perspective view showing an electrode pattern of the present embodiment.

In the embodiments shown in FIGS. 6 and 7, external connection electrodes 61 and 62 are provided on the ceramic dielectric substrate 24 so that the capacitors can be mounted on the motherboard 70 as individual components having a single function. Things. As shown in FIG. 7, in this embodiment, at the same time as the substantially comb-shaped lower electrode 51 disposed on the surface of the substrate 24, the first layer 57 of the external connection electrode of the lower electrode 51 and the outer layer of the upper electrode 52 are formed. A first layer 58 of a connection electrode is formed, and thereafter, a dielectric layer 53 is applied to the element electrode 55 of the lower electrode 51 and a peripheral portion thereof,
Thereafter, a comb-shaped upper electrode 52 is formed. When the upper electrode 52 is formed, the second layer 6 of the external connection electrode is used.
0 on the first layer 58, the element electrode 56 on the dielectric layer 53, and the second layer 59 of the external connection electrode of the lower electrode 51 with the first layer 5 of the lower electrode 51.
7, and external connection electrodes 61 and 62 are provided on the surface on which the lower electrode 51 and the upper electrode 52 are formed.

More specifically, the lower electrode 51 and the first layers 57 and 58 of the external connection electrodes are formed on the ceramic dielectric substrate 2.
It is preferable to apply a conductor paste on the entire surface of the substrate 4 and then bake to form a conductor film, and then to form the conductor film using a photolithography technique. At this time, the conductor used is
Copper having a low electromigration property, a low solder erosion property, and a low conductor resistance in a high frequency band is suitable.

Next, a heat-resistant resin film such as a polyimide resin or an epoxy resin to be the dielectric layer 53 is formed on the entire surface of the substrate 24, and then the first layer of the external connection electrode is formed by photolithography. The dielectric layer 53 on 57 and 58 is removed.

Next, a conductor film formed integrally with the second layer 59 of the external connection electrode of the lower electrode 51, the upper electrode 52, and the portion to be the second layer 60 of the external connection electrode is preferably formed. It is formed by copper sputtering. Then, as in the case of the lower electrode 51, the second layers 59 and 60 and the upper electrode 52 are formed using a photolithography technique. As described in the above embodiment, the pattern formation of the upper electrode 52 is performed by the element electrode 55 (5) of the lower electrode 51 (upper electrode 52) as shown in FIG.
6) The element electrode 56 (55) of the upper layer electrode 52 (lower layer electrode 51) is arranged in the blank space between them. Although not shown, the external connection electrode 6 is formed on the uppermost layer.
A protective film is formed of a resin or the like for the purpose of protecting the electrodes of the portions forming the capacitors except for the upper portions 1 and 62.

On the other hand, it is preferable to form solder bumps on the external connection electrodes 61 and 62. In forming the solder bumps, a solder cream may be printed on the external connection electrodes 61 and 62 using a solder mask, and then passed through a solder reflow furnace. Alternatively, a solder bump may be formed by depositing metal solder on the external connection electrodes 61 and 62 by using a vapor deposition method or the like, and then passing the solder through a solder reflow furnace.

As described above, the capacitor of this embodiment can be mounted on the motherboard 70 alone by providing the external connection electrodes 61 and 62 on the substrate 24. Further, by providing the external connection electrodes 61 and 62 on the same surface as the formation surface of the lower electrode 51 and the upper electrode 52 constituting the capacitor, as shown in FIG. 62 and the solder 6
3 enables surface mounting by a flip-chip mounting structure that is fixed to the conductor pattern 72 on the motherboard 70. The external connection electrodes 61 and 62 are connected to the substrate 24.
Since the electrodes 57 and 58 are formed by baking the conductive paste thereon, the adhesive strength of the electrodes 57 and 58 to the substrate 24 is sufficient, so that the adhesive strength of the capacitor of the present embodiment to the motherboard 70 is high.

Further, as described in the above embodiment, the capacitor of this embodiment is arranged such that a space between the element electrodes 55 (56) of one electrode 51 (52)
The element electrode 56 (55) of (51) is arranged, and the electrodes 51 and 52 are opposed to each other with the dielectric layer 53 interposed therebetween.
Since the pattern 52 is formed, the precision of the pattern formation is high, and the displacement of the capacitance value due to the displacement caused when the upper and lower electrodes 51 and 52 are formed is avoided.
It becomes possible to mass-produce capacitors with extremely high-precision capacitance values.

Further, a capacitor used in a high frequency band exceeding 1 GHz has a low capacitance and has a high accuracy (for example, 0.
When used at 5 pF ± 5%, the capacitance deviation is ± 0.02
5 pF) is required. For example, in the conventional surface mounting method, even when the amount of the solder 63 for attaching the component is changed,
The impedance developed by the low-capacitance capacitor after mounting changes. However, in this embodiment, the solder amount is adjusted in advance by providing solder bumps on the external connection electrodes 61 and 62, and the capacitor is attached to the motherboard 70 with the solder amount. It is possible to mount the capacitor on the motherboard 70 without changing the impedance value after mounting the capacitor with the capacity.

In the above embodiment, when the dielectric layer is formed of ceramic, the dielectric layer is applied in a liquid state by using a dielectric paste or a sol-gel method, so that the dielectric layer can be formed with high precision. Is easy. However, when a resin material is used for the dielectric layer, there is an advantage that a high-temperature baking step in the case of using a ceramic is not required and the treatment may be performed at a curing temperature of 300 ° C. or less at most. In this case, a high dielectric constant material can be used for the purpose of increasing the capacitance value. In addition, if a high dielectric constant material composed of one or more of ceramic powder, glass powder and high dielectric constant resin powder is used by being dispersed and mixed in a resin material, the purpose is changed by changing the material and the mixing ratio. A capacitor having a capacitance value can be easily obtained.

The present invention may be applied to a component having a single function as described above, or may be applied to a part of a composite component such as a filter circuit.

[0050]

According to claims 1 to 4, the lower layer
Area of the margin of one element electrode of the electrode and the upper electrode
With the other element electrode facing through a dielectric layer
In addition, the cross-section corner of each element electrode is
With a structure in which the electrodes are opposed to each other with the body layer interposed therebetween, even if the electrode pattern is displaced, the capacitance value on both sides of the element electrode is canceled out, so that the capacitance value fluctuation is reduced, and the capacitance value variation is small and high accuracy. Can be provided. In addition, since a dielectric layer is interposed between the lower electrode and the upper electrode, the element electrodes can be arranged close to each other without a risk of a short circuit. It is possible to provide a capacitor having a larger capacitance value.

According to the fifth aspect, the substrate is made of a ceramic dielectric, and the substrate has external connection electrodes connected to the electrodes on the motherboard. The effect of being able to be mounted on a motherboard as a component is obtained.

According to the sixth aspect, the external connection electrode is formed on the surface of the substrate on which the lower layer electrode and the upper layer electrode are formed. Surface mounting is possible, and an effect is obtained that a capacitor having a small mounting area and a high bonding strength to a motherboard can be provided.

According to the seventh aspect, since a solder precoat or a solder bump is formed on the external connection electrode, in addition to the effect of the fifth or sixth aspect, a capacitor which can be easily soldered is obtained. When solder bumps are used, the amount of solder can be set in advance, so that a capacitor having a small variation in impedance due to soldering can be obtained.

According to the eighth aspect, since the lower layer electrode and the upper layer electrode are each formed by using a photolithography technique, in addition to the effects of the first to seventh aspects, a high-precision capacitance value is further improved. The effect that a capacitor is obtained is obtained.

According to the ninth aspect, since the dielectric layer is formed of a resin material, in addition to the effects of the first to eighth aspects, there is an advantage that a high-temperature firing step when using ceramic is not required. Is obtained.

According to a tenth aspect of the present invention, a resin material is used for the dielectric layer, and a high dielectric constant material comprising at least one of ceramic powder, glass powder and high dielectric constant resin powder is contained in the resin material. Since the particles are dispersed and mixed, in addition to the effects of claims 1 to 9, a dielectric layer higher than the resin material can be obtained, and a dielectric layer having a desired dielectric constant can be easily obtained, and a desired capacitance can be obtained. The effect is obtained that the value can be easily obtained.

According to the eleventh aspect, the dielectric layer is formed by firing a dielectric paste.
In addition to the effects of Nos. To 8, an effect is obtained that the dielectric layer can be formed easily and accurately.

[Brief description of the drawings]

FIG. 1A is a perspective view showing an embodiment of a capacitor according to the present invention, and FIG. 1B is a perspective view showing an electrode pattern of the capacitor.

FIG. 2A is a sectional view of the capacitor of the embodiment of FIG. 1,
(B) is a diagram illustrating the operation.

FIG. 3A is a sectional view of a capacitor according to another embodiment of the present invention, and FIG. 3B is a perspective view showing a pattern of electrodes of the capacitor.

FIG. 4A is a sectional view of a capacitor according to another embodiment of the present invention, and FIG. 4B is a perspective view showing a pattern of electrodes of the capacitor.

FIG. 5A is a sectional view of a capacitor according to another embodiment of the present invention, and FIG. 5B is a perspective view showing a pattern of electrodes of the capacitor.

FIG. 6A is a plan view of a capacitor according to another embodiment of the present invention, and FIG. 6B is a side view showing a mounting structure thereof.

FIG. 7 is a perspective view showing a pattern of an electrode of the embodiment of FIG. 6;

FIGS. 8A and 8B are a cross-sectional view and a perspective view showing a first example and a second example of a conventional capacitor, respectively.

[Explanation of symbols]

11: lower electrode, 12: upper electrode, 13: dielectric layer, 1
4: substrate, 15, 16: element electrode, 21: lower electrode, 22: upper electrode, 23: dielectric layer, 24: substrate, 2
5, 26: element electrode, 27, 29: extraction electrode, 28, 30: terminal portion, 31: lower electrode, 35: element electrode, 41: lower electrode, 42: upper electrode, 44:
Annular part, 46: element electrode, 47: extraction electrode,
48, 50: terminal portion, 49: connection portion, 51: lower layer electrode,
52: upper electrode, 53: dielectric layer, 55, 56: element electrode, 57: first layer of external connection electrode 61, 58:
First layer of external connection electrode 62, 59: external connection electrode 6
1 second layer, 60: second layer of external connection electrode 62, 6
1, 62: external connection electrode, 63: solder, 70: motherboard, 72: conductor pattern

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-85424 (JP, A) JP-A-8-288790 (JP, A) JP-A-5-47586 (JP, A) JP-A-9-98 45580 (JP, A) JP-A-8-330182 (JP, A) JP-A-63-121611 (JP, A) JP-A-58-66632 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01G 4/00-4/42

Claims (11)

(57) [Claims] 1. A substantially comb-shaped lower electrode is formed on a substrate.
Forming a dielectric layer on the lower electrode, and forming a dielectric layer on the dielectric layer.
An upper electrode having a substantially comb shape is formed, and each element of one of the lower electrode and the upper electrode is formed.
Space between contact electrodesIn the area ofTo each other element
Poles arrangedAnd Each element electrode has the dielectric at the corner of the cross section.
Facing through body layer A capacitor characterized in that: 2. A method for forming a lower electrode on a substrate, comprising the steps of:
Forming a dielectric layer, and forming an upper electrode on the dielectric layer
And either one of the lower electrode and the upper electrode is a ladder.
And the other electrode is in the form of a comb, and the other electrode is in the form of a comb.
Each element electrode of the pole is connected to the one frame-shaped element electrode.
Margins in the poleIn the area ofset onAnd Each element electrode has the dielectric at the corner of the cross section.
Facing through body layer A capacitor characterized in that: 3. A method for forming a lower electrode on a substrate, comprising the steps of:
Forming a dielectric layer, and forming an upper electrode on the dielectric layer
One of the lower electrode and the upper electrode is
Element electrode of the other electrode
Margin in the annular part of one electrodeArea ofPlaced inAnd Each element electrode has the dielectric at the corner of the cross section.
Facing through body layer A capacitor characterized in that: 4. The pattern according to claim 1, wherein a width of a margin of said one electrode is W1, a width of another element electrode disposed in said margin is W2, and a pattern of said other electrode is W1. A capacitor characterized by the following relationship: W1 ≧ W2 + 2 · W3, where W3 is the maximum possible deviation from the design position of the capacitor. 5. The method according to claim 1, wherein
The capacitor according to claim 1, wherein the substrate is made of a ceramic dielectric, and the substrate has external connection electrodes connected to electrodes on a motherboard. 6. The capacitor according to claim 5, wherein the external connection electrode is formed on a surface of the substrate on which the lower electrode and the upper electrode are formed. 7. The capacitor according to claim 5, wherein a solder precoat or a solder bump is formed on the external connection electrode. 8. The method according to claim 1, wherein
The capacitor, wherein the lower electrode and the upper electrode are each formed using a photolithography technique. 9. In any one of claims 1 to 8,
The capacitor, wherein the dielectric layer is formed of a resin material. 10. The method according to claim 9, wherein:
A capacitor comprising a high dielectric constant material made of at least one of ceramic powder, glass powder and high dielectric constant resin powder dispersedly mixed therein. 11. A capacitor according to claim 1, wherein said dielectric layer is formed by applying and firing a dielectric paste.