JP3358710B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device comprising a one-chip microcomputer.

[0002]

2. Description of the Related Art A one-chip microcomputer in which a control unit, a calculation unit, a storage unit, and an input / output unit are mounted on the same semiconductor substrate is disclosed in, for example, Hayakawa published on April 1, 1984 by CQ Publishing Co. As described in Masaharu's book "Basics of One-Chip Microcomputers and Their Applied Technologies", they are widely used in industrial and home appliances as inexpensive and high-performance control elements. The storage unit of the one-chip microcomputer includes a ROM (Read Only Memory) in which programs for various types of information processing, dictionary data, and the like are stored, and a RAM in which a program currently being executed and data in the middle of calculation are temporarily stored.
(Random Access Memory).

As the ROM, a mask ROM for writing data during a manufacturing process is usually used. However, in order to facilitate system debugging and the like, an EPROM (Erasable and ROM) capable of writing data after manufacturing is used.
Programmable ROM) is also widely used. EPROM
Since the data can be erased by irradiating ultraviolet rays, the information can be rewritten any number of times, and a one-chip microcomputer with a high degree of freedom can be obtained.

[0004]

SUMMARY OF THE INVENTION The present inventor has proposed an electric
As a result of studying a one-chip microcomputer having a built-in and erasable nonvolatile memory , the following problems were found.

[0005] In the I / O of a one-chip microcomputer
MISFETs are required to have a high breakdown voltage. Also electrical
Writable and erasable nonvolatile memory cell and its write
The circuit that generates the voltage for programming or erasing is one chip
If it is built into a microcomputer,
Voltage system and higher level voltage system
MISF in the peripheral circuit
The withstand voltage of ET must be considered.

[0006]

[0007]

An object of the present invention is to be improved the function of the one-chip micro semiconductor integrated circuit device comprising a computer that are provided by semi-conductor integrated circuit device to provide a technique capable.

[0009]

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in a semiconductor integrated circuit device constituting a microcomputer having a central processing unit on one semiconductor chip and a nonvolatile memory for storing program data and dictionary data of the central processing unit, A first nonvolatile memory for electrically writing information and erasing the written information by irradiating ultraviolet light, and a first nonvolatile memory for electrically writing information and electrically writing the written information. And a second nonvolatile memory to be erased.

An EPROM is provided in a first region of the semiconductor substrate.
Forming a memory MISFET in a memory cell of an EEPROM in a second region different from the first region of the semiconductor substrate;
A method of manufacturing a semiconductor integrated circuit device comprising a microcomputer including a step of forming a switch MISFET in a memory cell of the EEPROM in a third region adjacent to a region, the method comprising: Forming a first gate insulating film on a surface of each of the first and third regions; forming a source and a drain on predetermined portions of the second and third regions below the first gate insulating film; Forming a floating gate electrode on the first gate insulating film in the first and second regions and forming a gate electrode on the first gate insulating film in the third region;
Forming a second gate insulating film on the surface of the floating gate electrode in the region and the second region;
Forming a control gate electrode on the second gate insulating film in the region; and forming a source and a drain in a predetermined portion below the first gate insulating film in the first region. This is done in the order described above.

According to the above means, program data and dictionary data requiring a large storage capacity are stored in the EPROM
The control data that needs to be stored even when the content of the data changes with time and the power is cut off, such as control data for feedback control, is stored in the EEPR.
Since the data is stored in the OM, the function of the semiconductor integrated circuit device including the one-chip microcomputer can be improved.

Further, since a part of a step of forming an EPROM memory cell on a semiconductor integrated circuit device comprising a one-chip microcomputer and a part of a step of forming an EEPROM memory cell are shared, the semiconductor integrated circuit device is provided. Manufacturing process can be reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit device comprising a one-chip microcomputer according to one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a semiconductor chip on which a microcomputer is constructed, which includes a CPU (microprocessor) 100, an OSC (transmitter) 101,
O (input / output port) 102, SI (serial interface) 103, TIMER (timer) 104, EP
ROM (erasable & programmable read only memory) 105, V _CX C (voltage control circuit) 10
6. EEPROM (Electrically Eraseable &
Programmable read only memory) 107,
SRAM (static random access memory) 108, DRAM (dynamic random access memory) 109, I / OBUS (input / output bus) 1
10 is provided. The CPU 100 includes a control unit, a calculation unit, and various registers. OSC 101
Although not limited, a high-precision reference frequency signal is formed by using a crystal oscillator Xtal provided outside the semiconductor chip 1. To form a clock pulse. The I / O 102 includes a data transfer direction register therein. EPROM10
5, EEPROM 107, SRAM 108, DRAM1
Reference numeral 09 includes a control circuit necessary for reading, writing, or erasing information from the storage element. V _CX C10
Reference numeral 6 denotes a write operation of the EPROM 105 or an EEPROM.
The word line voltage or the data line voltage required for the write / erase operation 107 is controlled. The SI 103 is composed of three terminals, a serial clock, a serial in, and a serial out, and a register of predetermined bits. Used as a port. The TIMER 104 is used to set the time required for multiplex processing such as interrupt processing. These CPU 100, I / O 10
2, SI103, TIMER104, EPROM10
5, V _CX C106, EEPROM 107, SRAM10
8. The DRAM 109 has an I / OB centered on the CPU 100.
They are interconnected by US110. In addition, I /
The OBUS 110 is composed of a data bus, an address bus, and a control bus.

The EPROM 105 stores various information processing programs, dictionary data, and the like. The EPROM 105 is used for storing the programs, dictionary data, etc., which have relatively few data rewrites and require a large capacity. EEPROM
Reference numeral 107 denotes a power supply among control data of feedback control that changes with time, a program being executed, data in the middle of calculation, and data in a register of the CPU 100, together with storage of programs and dictionary data for various information processing. It is also used to store data that needs to be stored at the time of shutdown. Also, the EEPROM 107
Is used for frequently rewriting data among data which can be stored in the EPROM 105 such as programs for various information processing and dictionary data, and is used for storing data having a small data capacity.

The writing operation of the EPROM 105 is as follows.
The following steps are performed.

That is, the EPROM 105 is brought into a writable operating state and a voltage control circuit (V _CX C) 106 is operated by various control signals output from the CPU 100.
To generate a predetermined word line voltage or data line voltage by a write voltage applied from the outside or a voltage applied for normal operation of the microcomputer.

Next, the CPU 100 outputs the data directly input from the outside to the EPROM 105 via the I / O 102 or the RAM once (SRAM 108, DRAM 109).
EPROM 105 based on the data input through
Write predetermined data to a predetermined address. EPRO
After writing of various data to M105 is completed, CP
U100 terminates the write operation of EPROM 105 and the operation of voltage control circuit 106.

Next, the write and erase operations of the EEPROM 107 will be described.

The writing and erasing operations of the EEPROM 107 are performed by various control signals output from the CPU 100 to set the EEPROM 106 to an operation state in which writing or erasing is possible, and to operate the voltage control circuit 106 to write a voltage applied from the outside. A predetermined word line voltage or data line voltage is generated by an erase voltage or a voltage for normal operation of the microcomputer. Next, the CPU 100 writes or erases or deletes predetermined data at a predetermined address of the EEPROM 107 based on data directly input to the EEPROM 107 from the outside via the I / O 102 or data once input via the SRAM 108 or the DRAM 109. Rewrite the data. After the writing, erasing, or rewriting of various data to the EEPROM 107 is completed, the CPU 100 ends the writing or erasing operation of the EEPROM 107.

The normal operation of the microcomputer according to the present embodiment includes various control signals, EPROM 105 and EE
After subjecting various data input to the I / O 102 to predetermined processing based on programs and dictionary data stored in the PROM 107, the data is output from the I / O 102 to the outside. Here, various data input to the I / O 102, data subjected to predetermined processing, or the CPU 10
Among the data in the register of 0, the data that needs to be stored even when the power is turned off, that is, the data that is required at the time of restarting after the power is turned off, is the EEP described above.
It is stored at a predetermined address according to the operation procedure of the ROM 107. The storage in the EEPROM 107 may be performed while the intermediate data is stored in the EEPROM 107 for each process, or the final data after the predetermined process is completed may be stored in the EEPROM 107.

On the other hand, the microcomputer according to the present embodiment, when an abnormal power interruption occurs due to an accident, various data necessary for restarting the operation,
That is, various data input to the I / O 102, data subjected to predetermined processing, or predetermined data in data in a register of the CPU 100 is stored in the above-described EEPROM.
It is stored at a predetermined address according to the operation procedure of 107. As described above, the microcomputer according to the present embodiment includes the power supply voltage backup circuit that supplies a voltage necessary for the operation of the EEPROM 107 in order to normally operate the EEPROM 107 even when the power is shut off. The power supply voltage backup circuit is not particularly limited, but may be composed of a capacitor and a control circuit and configured on the same semiconductor chip as the microcomputer of the present embodiment, or may be a microcomputer of the present embodiment. It may be configured on an electronic device including a computer and having the same power supply.

Next, referring to FIG. 1 and FIG.
The circuit operation of M105 will be described.

FIG. 3 is an equivalent circuit diagram showing a schematic configuration of a circuit of the EPROM 105 mounted on the microcomputer of the present embodiment.

E of the microcomputer of the present embodiment
The PROM 105 includes a logic voltage system such as a power supply voltage Vcc, for example, 5 V, and a writing voltage system including a writing voltage Vpp or a high voltage V _CX of more than ten volts obtained by increasing or decreasing the writing voltage Vpp by the voltage control circuit 106. Is the operating power supply. During a normal read operation, the operation is performed by a logic voltage system.

The EPROM 105 has an address input terminal Xo
Xi and Yo to Yj, the operation of which is controlled by an address signal supplied via the control terminals CE, OE, and PGM, and a chip enable signal, an output enable signal, and a program signal. These control signals are relayed or formed by a control circuit in the EPROM 105 (not shown) under the control of the CPU 100.

The EPROM 105 of this embodiment performs a read or write operation of a memory cell in units of 8 bits. The memory cell array M-ARY includes a plurality of memory cells M1 to which data is electrically written and erased by irradiation with ultraviolet rays.
It comprises ISFETs Q _{EP1 to} Q _EP4 , a plurality of word lines including word lines W0 to W1, and a plurality of data lines including data lines D0 to D1. Memory cell array M-
In the ARY, the MISFETs Q arranged in the same row
The drains of _EP1 , _QEP2 through _QEP3 , _QEP4 are connected to corresponding data lines D0, D1, respectively. Address terminal X
The X address signal and the Y address signal supplied from the CPU 100 through O to Xi and Yo to Yj are X
Address buffer XADB and Y address buffer Y
Input to ADB. Address buffer XADB, YA
The DB operates by a timing signal ce formed by the control circuit CONT, takes in an address signal supplied from the CPU 100, forms a complementary address signal composed of an internal address signal having the same phase and a reverse phase with the address signal, and outputs X address decoders XDCR and YDCR. Address decoder YD
Supply to CR.

The X address decoder XDCR supplies a selection signal for selecting a word line of the memory cell array M-ARY according to a complementary address signal supplied from the X address buffer XADB. The voltage level of the word line selection signal formed by X address decoder XDCR is determined by voltage V _CX supplied from voltage control circuit 106. During a normal read operation, it is set to the power supply voltage Vcc level which is a logic voltage system, and during a write operation, it is set to V _CX level which is a write voltage system.

The Y address decoder YDCR forms a selection signal for selecting a data line of the memory cell array M-ARY based on the complementary address signal supplied from the address buffer YADB. Y address decoder YD
The selection signal output from the CR is a Y gate circuit YGATE.
Is supplied to the gate electrodes of the MISFETs Y ₁₁ , Y ₁₂ , Y ₂₁ , and Y ₂₂ . The selection of the data line is performed by the Y gate circuit YGAT.
After a first selection of a plurality of data line groups is performed by the MISFETs Y ₁₁ and Y ₁₂ , the MISFETs Y ₂₁ and Y 12
_{This is} performed by a second selection of selecting a predetermined data line from the data line group according to ₂₂ . Here, the Y gate circuit YGAT
By configuring E with two MISFETs connected in series, the load capacitance of each MISFET can be reduced, and a high-speed read operation can be performed. In addition, the voltage level of the data line in the normal read operation is set to the power supply voltage V supplied to the word line in order to prevent the _MISFETs Q _{EP1 to} Q _{EP4 from} being erroneously written during the read operation.
It is set to a level lower than the cc level. More specifically, it is set to a level of 20 to 40% of Vcc.
During a write operation, the voltage is set to a predetermined voltage corresponding to the V _CX level which is a write voltage system. Further, each data line D0, D1 is coupled to a common data line CD.

Data output circuit DOB is coupled to a common data line via sense amplifier circuit SA. Although the sense amplifier is not particularly limited, a current mirror type sense amplifier circuit is used in the present embodiment. The data output circuit DOB has an input / output terminal DI
0 to DI7. Data input circuit DI
B is composed of an input buffer coupled to input / output terminals DI0 to DI7.

Data is stored in the EPROM 105 by using MISFETs Q _EP1 to Q _{EP1 to} Q
The threshold voltage of _EP4 is set to a normal relatively low voltage (logic "1") or a relatively high voltage (logic "0") by writing by charge injection into the floating gate electrode.
It depends on what you do.

Next, referring to FIG. 1 and FIG.
The circuit operation of the OM 107 will be described.

FIG. 4 is an equivalent circuit diagram showing a schematic configuration of a circuit of the EEPROM 107 mounted on the microcomputer of the present embodiment.

The EEPROM 107 mounted on the microcomputer according to the present embodiment includes a power supply voltage Vcc, a logic voltage system such as 5 V, a write / erase voltage Vcc.
A high-level writing or erasing voltage V _CX system such as tens of volts obtained by raising or lowering the voltage Vpp or the voltage Vcc by the pp or the voltage control circuit 106 is used as an operation power supply. Normal read operation is performed by a logic voltage system. The EEPROM 107 is controlled by an address signal supplied via address input terminals Xo to Xi and Yo to Yi, and by a memory control circuit (not shown) in the EEPROM 107 under the control of the CPU 100, or various control signals formed. , The operation of which is controlled.

The EEPROM 107 in the present embodiment
Performs a read, write or erase operation of the memory in units of 8 bits. The memory array M-ARY includes a plurality of memory MISFETs Q for electrically writing and erasing.
And _EEP1 to Q _EEP4, reading of the memory MISFET Q _EEP1 to Q _EEP4, a switch MISFET Q _S1 to Q _S4 for controlling the operation of write and erase, the word line W _E0
To W _E1 and W _{S0 to} W _S1 , and a plurality of data lines including data lines D _{0 to} D ₁ . In the memory array M-ARY, the memory _MISFETs Q _EEP1 , Q _{EEP2 to} Q _EEP3 ,
The control gate electrodes of _EEP4 are connected to corresponding word lines W _{E0 to} W _E1 , respectively.
_S1, the gate electrode of Q _S2 to Q _S3, Q _S4 is connected to a word line W _S0 to W _S1 respectively corresponding switch MISFET Q _S1 arranged in the same column, Q _S3 to Q _S2, the drain of Q _S4, respectively are connected to corresponding data lines D ₀ to D _1. Also, the sources of the switches _MISFETs Q _{S1 to} Q _S4 are connected to the memory _MISFETs Q _EEP1 to Q _EEP4 ,
The sources of the memory _MISFETs Q _EEP1 to Q _EEP4 are grounded.

The X address signal and the Y address signal supplied from the CPU 100 via the address terminals Xo to Xi and Yo to Yj are input to the X and Y address buffers XYADB. Address buffer XYAD
B operates in accordance with a timing signal formed by the control circuit CONT, takes in an address signal supplied from the CPU 100, forms a complementary address signal composed of an internal address signal having the same phase as that of the address signal, and forms a complementary address signal with X.
Address decoder XDCR and Y address decoder Y
Supply to DCR. In addition, the address buffer XYADB
Has a latch circuit therein, and can temporarily store an address signal in the latch circuit.

The X address decoder XDCR forms a selection signal for selecting two types of word lines of the memory array M-ARY according to the complementary address signal supplied from the address buffer XYADB.

The Y address decoder YDCR forms a selection signal for selecting the data lines D _{0 to} D ₁ of the memory array M-ARY according to the complementary address signal supplied from the address buffer YADB. The selection signal output from the Y address decoder YDCR is a Y gate circuit YG
Supplied to the ATE. Although the Y gate circuit YGATE is not particularly limited, the Y gate circuit YG in FIG.
This is the same system as GATE.

The data input / output circuit IOB is connected to the data line and input / output terminals DI0 to DI7. The data input / output circuit IOB includes a sense amplifier circuit, an input / output buffer circuit, and a latch circuit for temporarily storing input data.

Data latch circuit and program circuit DL
Temporarily stores write or erase data supplied from the input / output terminals DI0 to DI7, and based on the write or erase data, the memory cell MISFET Q
_{This is} for performing the operation of writing or erasing the information of _{EEP1 to QEEP4} .

E of the microcomputer of the present embodiment
Since the EPROM 107 includes the various latch circuits as described above, erroneous writing or erasing at the time of a writing or erasing operation can be prevented.

The memory MISF of the EEPROM 107
Each of the ETQ _{EEP1 to} Q _EEP4 includes a floating gate electrode, a tunnel insulating film below which a tunnel current can flow, and a semiconductor region therebelow. Then, the writing operation is performed by discharging electrons from the floating gate electrode so that the memory MIS is released.
FETs Q _EEP1 to say that the threshold voltage of Q _EEP4 lower than the source voltage and the memory MI by injecting electrons into the floating gate electrode and the erasing operation
This _means that the threshold values of the _SFETs QEEP1 to _QEEP4 are set higher than the source voltage. The emission of electrons in writing and the injection of electrons in erasing are performed through a tunnel insulating film.

Next, a description will be given of a circuit operation when writing information in the EEPROM 107.

First, the EEPROM 107 is set to a writable operation state by various control signals output from the CPU 100, and an address to be written is temporarily stored in a latch circuit of the address buffer XYADB. The write data is temporarily stored in the data latch circuit and the latch circuit of the program circuit DL. Next, in the memory MISFET Q _EEP1 to the word line W _S0 to high voltage can be written the potential of W _S1 of Q _EEP4 is combined switch MISFET Q _S1 to Q _S4 performs a write operation switch MISFET Q _S1 to Q _S4 State. At this time, all the word lines W _{E0 to} W _E1 coupled to the memory _MISFETs Q _EEP1 to Q _EEP4 are set to a low voltage of almost 0V. After that, the memory MISFETQ to which writing is performed
_EEP1 to Q _{EE P4} to apply a writable high voltage to the data lines D ₀ to D ₁ is coupled via a switch MISFET Q _S1 to Q _S4.

With the above circuit operation, the memory MISFE
Since the potential of the semiconductor region below the tunnel insulating film provided below the floating gate electrodes of TQ _{EEP1 to} Q _EEP4 is higher than the potential applied to the control gate electrode, it is even lower than this control gate electrode. Electrons in the floating gate electrode at a potential are released through the tunnel insulating film into the semiconductor region thereunder, and writing is performed.

Next, the operation of a circuit for erasing information will be described.

In this embodiment, although not controlled, an erase operation is performed for each word line.
In the erasing operation, first, the EEPROM 107 is set to an erasable operating state by various control signals output from the CPU 100, and the word lines W _E0 , W _{E1 to} W _S0 , and W _S1 are set to a low voltage level close to the ground voltage. At this time, although not limited, the voltages of the data lines D ₀ and D ₁ are also set to a low voltage level close to the ground voltage. next,
Of the memory MISFET Q _EEP1 to Q word line coupled to _EEP4 W _E0, W _E1, erase the word line W _E0 to W _E1 to be erased and high voltage levels available. When these operations are performed, the voltage of the control gate electrodes of the memory _MISFETs Q _EEP1 to Q _EEP4 becomes higher than the voltage of the semiconductor region below the tunnel insulating film, so that the electrons in the semiconductor region pass through the tunnel insulating film. Erasing is performed by being injected into the floating gate electrode.

Next, the operation of a circuit for reading information will be described.

In the read operation, first, the memory MISFET
Always Q _EEP1 to word lines coupled to Q _EEP4 W _E0 to W _E1 in the unselected state close to the ground voltage, the switch MIS
Word lines W _{S0 to} W _S1 coupled to FETs Q _{S1 to} Q _S4
By selecting the data lines D ₀ to D ₁ and to select a particular memory cell from the plurality of memory cells.

The memory MIS of the selected memory cell
Either FET (Q _EEP1 to Q _EEP4, hereinafter simply Q
_If electrons have been written in the floating gate electrodes of _{EEP1 to QEEP4} ), the word line W
_{Since E0 to} W _E1 are at a low potential, the memory M
ISFETQ _EEP1 to Q _EEP4 becomes nonconductive, this logic "0" corresponding to the read data lines D ₀ to D _1.

On the other hand, wherein when no electrons are injected into the floating gate electrode of a selected memory cell of the memory MISFET Q _EEP1 to Q _EEP4 was, the memory MISFET Q _EEP1 to Q _EEP4 becomes conductive, corresponding to logic "1" is read to the data lines D ₀ to D ₁ Te.

Next, the SRAM 108 and the DRAM 109 provided in the microcomputer shown in FIG. 1 will be described.

The SRAM 108 is mainly used as a temporary storage circuit for data that needs to be transferred at a high speed between the CPU 100 and the I / O 102 in a program being executed or data being calculated.

The memory cell of the SRAM 108 provided in the microcomputer of the present embodiment has two P-channel MISFETs 205 and 206 as shown in FIG.
And four N-channel MISFETs 203, 204, 2
07, 208.

FIG. 2 shows an SRAM provided in the microcomputer according to the embodiment of the present invention shown in FIG.
108 is an equivalent circuit of the memory cell 108.

The memory cell of the SRAM 108 has 2
It may be composed of a plurality of high resistance elements and four MISFETs. The DRAM 109 mainly stores the CPU 1 in the program being executed or the data being calculated.
It is not necessary to perform high-speed data transfer to or from the I / O 102 and is used as a temporary storage circuit for data requiring a large-capacity memory. D of the present embodiment
The memory cell of the RAM 109 is composed of a capacitor for storing electric charges and a switch MISFET for controlling the capacitor. As described above, in the microcomputer of the present embodiment, the RAM is constituted by the SRAM 108 and the DRAM 109. Although it is not necessary to perform the transfer at a high speed, the DRAM 109 is used for storing a large amount of data. The SRAM 10
8 operates as a so-called cache memory and has a CPU
High-speed data transfer with the H.100.

The DRAM 109 in the present embodiment is
The substrate 1 is not operated by applying a potential serving as a reference for electrical operation of the circuit, that is, a ground potential Vss, for example, a negative potential lower than 0 V. This is because when a negative potential lower than the ground potential Vss is applied to the substrate 1 as described above, the EPROM 105 or the E-ROM that normally operates without setting the substrate 1 to a negative potential is used.
This is because the characteristics of the MISFET forming the EPROM 107 and the like change. However, the DRAM 1 on the substrate 1
09 is composed of the EPROM 105 and the EE
In the case where the MISFET and other regions such as the PROM 107 are electrically separated from each other, the substrate 1 may be operated by applying the negative potential to the substrate 1. That is, as described later, the DRAM 109 and other EEP
The ROM 107, the EPROM 105, and the like may be provided in separate P-type well regions, and the P-type well regions may be electrically separated.

The refresh operation of the DRAM 109 is performed by C
This is performed under the control of the PU 100. The DRAM 109 is operated with the word line potential set to a potential higher than the logic system voltage Vcc. This voltage is generated by the voltage control circuit 106.

Next, the structure of each of the MISFETs constituting the microcomputer of the present embodiment will be described with reference to FIGS.

FIG. 5 shows a MISFET constituting the EPROM 105 provided in the microcomputer of FIG.
FIG. 6 is a MISFET constituting the EEPROM 107 provided in the microcomputer of FIG.
FIG. 7 is a cross-sectional view of the microcomputer 100 shown in FIG.
It is sectional drawing of FET.

In FIG. 5, Q1 is a MISFET forming a memory cell of the EPROM 105, Q2 is an N-channel MISFET forming a peripheral circuit such as an address buffer and a decoder of the EPROM 105, and Q3 is an address buffer and a decoder of the EPROM 105. Is a P-channel MISFET constituting the peripheral circuit of FIG. EP
MISFET Q1 constituting the memory cell of the ROM 105
A first gate insulating film 6 formed of a thin silicon oxide film, provided on a p-type well region 3 of a main surface portion of a semiconductor substrate 1 formed of p-type single crystal silicon, and a floating gate formed of, for example, a polycrystalline silicon film An electrode 7A, a second gate insulating film 8A made of a thin silicon oxide film, and a tungsten silicide film (W
A control gate electrode 9A formed of a two-layer film of Si ₂ ), an n-type semiconductor region 11A forming a source and a drain on the channel region side, and a portion other than the n-type semiconductor region 11A of the source and the drain. and an n + type semiconductor region 13A. The thickness of the first gate insulating film 6 is, for example, about 500 ° and the second gate insulating film 8
A is, for example, about 350 °. The n-type semiconductor region 1
1A is for increasing the generation of hot carriers to improve the information writing characteristics. Note that the control gate electrode 9A is also a word line. The side surface of the floating gate electrode 7A and the side surface and the upper surface of the control gate electrode 9A are covered with a thin silicon oxide film 10. A side wall 12 made of a silicon oxide film is provided on the side of the floating gate electrode 7A and the control gate electrode (word electrode) 9A. Between the memory cells Q1 in the direction in which the word lines extend, a field insulating film 4 made of a silicon oxide film and a p-type channel stopper region 5 thereunder.
And separated by. The data line 16 is connected to the n + -type semiconductor region 13 which is a part of the drain when reading information.
D is connected. The data line 16D includes, for example, an aluminum film, aluminum as a main component, silicon,
Copper, palladium or the like added, or a silicide film (MoSi ₂ ,
TaSi ₂ , TiSi ₂ , WSi _2, etc.). Reference numeral 14 denotes a first passivation film, for example, a silicon oxide film, a phosphosilicate glass (PSG) film, a boron-doped P film formed by CVD.
It is formed of an SG (BPSG) film, a silicon oxide film formed by a plasma CVD method, or a laminated film thereof. Fifteen
Is a connection hole. Reference numeral 17 denotes a second passivation film, which is a silicon oxide film formed by a plasma CVD method,
It consists of a spin-on-glass film formed by spin coating. N-channel MISF constituting the peripheral circuit
The ETQ2 includes a gate insulating film 6, a gate electrode 7B made of, for example, a polycrystalline silicon film, an n.sup.- type semiconductor region 11B on the channel region side of the source and the drain,
An n + -type semiconductor region 13B constituting a portion of the drain other than the n − -type semiconductor region 11B. N ~
The type semiconductor region 11B is for controlling the generation of hot carriers at the end of the drain to prevent the electrical characteristics of the MISFET Q2 from changing. The side and top surfaces of the gate electrode 7B are covered with a thin silicon oxide film 10. A wiring 16 made of an aluminum film passes through the connection hole 15 in the n + -type semiconductor region 13B on the drain side.
Is connected. The n + type semiconductor region 13
Is provided at a predetermined distance from the sidewall 12 in order to improve the breakdown voltage of the drain. A P-channel MISFET Q3 constituting the peripheral circuit is provided in the n-type well region 2 on the main surface of the semiconductor substrate 1,
A gate insulating film 6, a gate electrode 7B made of, for example, a polycrystalline silicon film, a p-type semiconductor region 11C forming a source and a drain on the channel side, and a portion of the source and drain other than the p-type semiconductor region 11C. And a p + type semiconductor region 13C. A wiring 19 is connected to the wiring 17 through a connection hole 18. This wiring 19
Is made of the same material as the wiring 17. Although not shown, a final passivation film made of a PSG film, a silicon nitride film formed by a plasma CVD method, or the like is provided on the wiring 19.

The floating gate electrode 7A of the memory cell Q1, the gate electrode 7B of the N-channel MISFET Q2, and the gate electrode 7 of the P-channel MISFET Q3
B is made of the same first conductive film. The gate electrode 9A of the memory cell Q2 is made of a second conductive film. In addition, the memory cell Q1 and the N-channel MISFET
The gate insulating films 6 of the Q2 and P-channel MISFETs Q3 have the same thickness.

In FIG. 6, Q4 is the EEPROM 107
_MISFETs Q _{EEP1 to} Q _EEP
The N-channel MISFET and Q5 constituting _EEP4
Switch MISF in memory cell of EPROM 107
ETQ _S1 to N-channel MISFET, Q6 constituting a peripheral circuit of the address buffer and decoder, and the like of the Q _S4 or EEPROM 107 is a P-channel MISFET constituting the peripheral circuit of the EEPROM 107.

The N-channel MISFET Q4 has a capacity of 50
A first gate insulating film 6 made of a thin silicon oxide film of about 0 °, an insulating film 21 made of a silicon oxide film of about 1000 to 2000 ° thick, and a tunnel insulating film 22 made of an extremely thin silicon oxide film of about 100 ° Floating gate electrode 7 made of, for example, a polycrystalline silicon film.
C and a second silicon oxide film of about 350 °
It comprises a gate insulating film 8C, a control gate electrode 9C formed integrally with the word line, and an n-type semiconductor region 20 serving as a source and a drain. A thin silicon oxide film 10 covers the side surface of the floating gate electrode 7C and the side surface and upper surface of the control gate electrode (word line) 9C. The insulating film 21 is for relaxing the electric field at the end of the floating gate electrode 7C and improving the breakdown voltage. The memory cell switch MISFE
T or N-channel MISF for configuring peripheral circuits
The ETQ 5 includes a gate insulating film 6, an insulating film 21, a gate electrode 7B made of, for example, a polycrystalline silicon film, a source,
And an n-type semiconductor region 20 serving as a drain. The side and top surfaces of the gate electrode 7B are covered with the insulating film 10. A wiring 16D is connected to the n-type semiconductor region 20 serving as the drain of the N-channel MISFET Q5 through the connection hole 15. The wiring 16D is a data line in a memory cell, and a MIS in a peripheral circuit.
This is a signal wiring connected between FETs. The P-channel MISFET Q6 constituting the peripheral circuit includes a gate insulating film 6,
The gate electrode 7B, the p-type semiconductor region 11C forming the source and drain on the channel region side, and the p + forming the source and drain other than the p-type semiconductor region 11C.
And the semiconductor region 13C. Gate electrode 7
The insulating film 10 covers the side and top surfaces of B. A connection hole 15 is formed in the p + -type semiconductor region 13C forming a part of the source region.
The wiring 16 is connected through the connection. And this p +
The type semiconductor region 13C is provided at a predetermined distance from the sidewall 12 in order to improve the breakdown voltage of the source region.

The N channel MISFE of the memory cell
N-channel MISFET forming TQ4 and switch element
A wiring 19 made of a second-layer aluminum film is formed on Q5.
Is covering. That is, the entire memory cell array region is covered with the wiring 19. This is the EPROM 105
This is to prevent the data stored in the EEPROM 107 from being erased by the ultraviolet rays when the data stored in the EEPROM 107 is erased by irradiating the ultraviolet rays.

The floating gate electrode 7C of the storage element Q4 and the gate electrodes 7 of the MISFETs Q5 and Q6
B is formed of the same first-layer conductive film as the floating gate electrode 7A of the memory cell Q1 of the EPROM 105 and the gate electrodes 7B of the MISFETs Q2 and Q3. The control gate electrode 9C of the memory MISFET Q4 of the EEPROM 107 is made of the same second conductive film as the control gate electrode 9A of the EPROM 105.

In FIG. 7, Q7 is an N-channel MISFET for forming the CPU 100, and Q8 is an I / O 10
2 and an N-channel MISFET constituting an SI (serial interface) 103, and Q 9 is a P-channel MISFET constituting a CPU 100. The N-channel MISFET Q7 has a gate insulating film 8D made of a thin silicon oxide film of about 250 ° and a gate electrode 9D.
And n forming the source and drain portions on the channel region side.
-Type semiconductor region 11B and n + -type semiconductor region 1 forming a portion other than the n-type semiconductor region 11B of source and drain.
3B. The N-channel MISFET
Q8 is a gate insulating film 8D, a gate electrode 9D, an n-type semiconductor region 11A forming the source and drain on the channel region side, and an n + -type forming the source and drain other than the n-type semiconductor region 11A. And a semiconductor region 13B. The n-type semiconductor region 11A is for preventing the MISFET Q8 from being destroyed when an abnormally high voltage is applied to the drain region. The P-channel MISFET Q9 includes a gate insulating film 8D, a gate electrode 9D, a p-type semiconductor region 11C forming a portion of the source and drain on the channel region side, and a portion of the source and drain other than the p-type semiconductor region 11C. And a p + type semiconductor region 13C.

The gate electrodes 9D of the MISFETs Q7, Q8 and Q9 are made of the same second-layer conductive film as the control gate electrode 9A of the EPROM 105 and the control gate electrode 9C of the EEPROM 107.

The N-channel MISFET and the P-channel MISFET constituting the memory cell of the SRAM 108 shown in FIG. 2 are the same as the CPU (logic unit) 10 shown in FIG.
0 has the same structure as the N-channel MISFET Q7 and the P-channel MISFET Q9.

Next, the MISFETs Q1, Q2, Q
3, Q4, Q5, Q6, Q7, Q8, and Q9 will be described with reference to FIGS. 5, 6, 7 to 56, 57, and 58.

FIGS. 5, 6, 7 to 56, 57, and 58 show an EPROM 105, an EEPROM 107, and a CPU 1 of a microcomputer according to an embodiment of the present invention.
FIGS. 5 to 56 are cross-sectional views of a region where a memory cell of the EPROM 105 and MISFETs forming a peripheral circuit thereof are provided, and FIGS.
7 constituting the memory cell 7 and its peripheral circuits
7 to 58 are sectional views of a region where T is provided.
FIG. 2 is a cross-sectional view of a region where a MISFET constituting the I / O 102 is provided.

The P-channel MISFET and the N-channel MIFET constituting the memory cell of the SRAM shown in FIG.
The SFET is formed by the same manufacturing method as the N-channel MISFET Q7 and the P-channel MISFET Q9 constituting the logic section shown in FIG.

E of the microcomputer of the present embodiment
The method of manufacturing the MISFETs constituting the PROM 105, the EEPROM 107, the CPU 100, and the I / O 102 is as follows.
As shown in FIGS. 8 to 10, ion implantation and annealing are performed on each predetermined region of the main surface of the p − type semiconductor substrate (chip) 1 to form the n − type well region 2 or the p − type well region 3. Form. Reference numeral 50 denotes a thin silicon oxide film used as a buffer film when performing the ion implantation.

Next, as shown in FIGS. 11 to 13, predetermined regions of the n-type well region 2 and the p-type well region 3 are thermally oxidized by using a well-known technique. Is formed, and a p-channel stopper region 5 is formed in the p ~ type well region 3. 51 is a field insulating film 4
Is a silicon nitride film used as a mask for thermal oxidation when forming a film. Next, the silicon nitride film 51 is removed, and the silicon oxide film 50 used as a base film is further removed to expose portions of the nｎ-type well region 2 and the p ~ -type well region 3 which are not covered with the field insulating film 4. After that, the exposed surface is thermally oxidized again to form the gate insulating film 6 as shown in FIGS.

Next, the EEPROM 107 shown in FIG.
MISFE of memory cell and its peripheral circuit
A resist film 52 is formed on the n ~ -type well region 2 and the p ~ -type well region 3 as a mask for ion implantation when forming the n-type semiconductor region 20 serving as the source and drain of T. Next, an n-type impurity, for example, arsenic (As) ions is introduced at about 10 ¹⁴ to 10 ¹⁶ atoms / cm ² to form the n-type semiconductor region 20. After that, the resist film 52 is removed.

Next, as shown in FIGS. 17 to 19, an insulating film (Si) is formed on the n-type semiconductor region 20 by thermal oxidation.
O ₂ ) 21 are formed. Since the insulating film 21 has the n-type semiconductor region 20 of the high concentration layer below, a thick insulating film can be obtained. At this time, the oxide film thickness is set so that the thickness of the gate insulating film 6 is about 500 °. The thickness of the insulating film 21 is about 1000 to 2000 °. Alternatively, after the gate insulating film 6 is removed, 5
A gate insulating film of about 00 ° and an insulating film on the n-type semiconductor region 20 of about 1000 to 2000 ° may be simultaneously formed. Next, the memory MISFE of the EEPROM 107
In order to etch the insulating film 21 in the portion where the tunnel insulating film 22 of TQ4 is provided, a resist film 54 is formed as a mask as shown in FIGS.

Next, as shown in FIG.
Is etched to expose the surface of the n-type semiconductor region 20. After that, the resist film 54 is removed. Next, in the previous step, the insulating film 21 is formed.
N-type semiconductor region 20 exposed by removal of
Is thermally oxidized to form a tunnel insulating film 22 made of a silicon oxide film. The thickness of the tunnel insulating film 22 is
It is about 100 °.

Next, the memory cell Q1 of the EPROM 105
Floating gate electrode 7A and peripheral circuit MISF
Gate electrodes 7B of ETQ2 and Q3 and EEPROM 10
7, the floating gate electrode 7C of the memory MISFET Q4 of the memory cell, and the switch MIS of the memory cell.
Gate electrode 7 of MISFET Q5 of FET and peripheral circuit
To form B, as shown in FIGS.
For example, a polycrystalline silicon film 7 is formed on the n ~ -type well region 2 and the p ~ -type well region 3 by CVD. The polycrystalline silicon film 7 has n-type impurities by thermal diffusion, ion implantation, or the like.
For example, phosphorus (P) is introduced to reduce the resistance.

Next, as shown in FIGS. 26 to 28, the polycrystalline silicon film 7 is patterned
105 floating gate electrode 7 of memory cell Q1
A, the gate electrode 7B of the peripheral circuit, the floating gate electrode 7 of the memory MISFET Q4 of the EEPROM 107
C, switch MIS of memory cell of EEPROM 107
The gate electrodes 7B of the MISFETs Q5 and Q6 of the FET and the peripheral circuit are formed respectively. CPU 100 and I / O
Since the gate electrodes of the MISFETs Q7, Q8, and Q9 that form the MISFET 102 are formed of a second-layer conductive film to be formed later, the first-layer polycrystalline silicon film is formed in a region for forming the MISFETs Q7 to Q9. 7 is removed and does not remain.

Here, the EPROM 105 shown in FIG.
Of the floating gate electrode 7A of the memory cell Q1
In the direction in which the data line extends, the pattern is extended without being divided for each floating gate electrode 7A of each memory cell. However, in the direction in which the word line extends, the pattern is separated for each floating gate electrode 7A of an adjacent memory cell. This is because when a control gate electrode (word line) 9A is formed thereon later, a second patterning is performed on the floating gate electrode 7A extending long in the direction in which the data line extends. This is to make a predetermined pattern.

On the other hand, the floating gate electrode 7 of the memory MISFET Q4 of the memory cell of the EEPROM 107
C is a pattern separated for each memory cell. Next, as shown in FIGS.
Floating gate electrodes 7A and EE of ROM 105
The surface of floating gate electrode 7C of PROM 107 is thermally oxidized to form second gate insulating films 8A and 8C.
When the second gate insulating films 8A and 8C are formed, the surface of the other gate electrode 7B is also thermally oxidized to form a thin silicon oxide film 8. Next, after a portion other than the CPU 100 region and the I / O 102 region is covered with the resist film 55, the thin silicon oxide film (gate insulating film) 6 formed in the CPU 100 region and the I / O 102 region is removed by etching.

Next, as shown in FIGS. 32 to 34, the CPU 100 and the I / O 102 are thermally oxidized to expose the CPU 100 region and the I / O 102 region which are exposed by etching the silicon oxide film 6 first. M for
An ISFET gate insulating film 8D is formed. When the gate insulating film 8D is formed, the surfaces of the floating gate electrodes 7A and 7C and the gate electrode 7B are oxidized, and the thicknesses of the second gate insulating films 8A and 8C and the silicon oxide film 8 increase.

Here, the thickness of the second gate insulating films 8A and 8C is finally set to about 350 °. Also,
The thickness of the gate insulating film 8D is determined by the CPU 100 or the I / O 10
The film thickness is optimized for the MISFETs Q7 to Q9 forming the second element. Note that the EPROM 105 and the EEPROM 10
7 constituting memory cells and their peripheral circuits
The gate insulating film 6 of the FET, the CPU 100 and the I / O 10
Since the gate insulating film 8D of the MISFETs constituting the MISFET 2 has an optimum value for those MISFETs, the gate insulating film 6 may be formed thicker, and the gate insulating film 8D may be formed thicker. is there. Further, the gate insulating film 6 and the gate insulating film 8D may be formed to have the same thickness.

After forming the gate insulating film 8D, a second conductive film 9 is formed on the entire surface of the semiconductor chip 1. The conductive film 9 is formed of a two-layer film in which a polycrystalline silicon film is formed by, for example, CVD, and a silicide film is further laminated thereon by sputtering. An n-type impurity such as phosphorus (P) is introduced into the polycrystalline silicon film by ion implantation or thermal diffusion to reduce the resistance.

Next, as shown in FIGS. 35 and 36, the conductive film 9 is patterned using the resist film 72 as a mask.
The control gate electrode (word line) 9C of the memory MISFET Q4 of the EEPROM 107 and the MISFET Q
The gate electrodes 9D of 7, Q8 and Q9 are formed.

Next, as shown in FIGS. 38 to 40, a resist film 73 is formed. In this state, the EPROM 10
The control gate electrode 9A, the second gate insulating film 8A, and the floating gate electrode 7A of the memory cell Q1 of No. 5 are etched to obtain individual memory cells in the direction in which the data line extends, as shown in FIGS. The floating gate electrode 7A divided for each is formed.
Thereafter, the resist film 73 is removed.

Next, as shown in FIGS.
The surfaces of the control gate electrodes (word lines) 9A and 9D of the PROM 105 and the EEPROM 107 are thermally oxidized to form a thin silicon oxide film 10. At this time, the other MISFETs Q2, Q3, Q5, Q6, Q7,
The surfaces of gate electrodes 7B and 9D of Q8 and Q9 are also oxidized to form silicon oxide film 10. The area of the memory cell Q1 of the EPROM 105 and the MISFET of the I / O 102
Forming a resist film 56 having an opening in the region of Q8;
An n-type impurity such as arsenic (As) is introduced into the p-type well region 3 by ion implantation to form the memory cell Q1 and the n-type semiconductor region 11A serving as a part of the source and drain of the N-channel MISFET Q8. The dose of the impurity ions introduced at this time is, for example, 10 ¹⁵ atoms / cm ² .

Thereafter, the resist film 56 is removed, and FIG.
As shown in FIG. 49 to FIG. 49, a resist film 57 having an opening in a region where an N-channel MISFET Q2 for forming a peripheral circuit of the EPROM 105 and a region where an N-channel MISFET Q7 for forming the CPU 100 is formed is formed. Then, an n-type impurity such as phosphorus (P) is introduced by ion implantation, and the N-channel M
An n.sup.- type semiconductor region 11B to be a part of the source and drain of the ISFETs Q2 and Q7 is formed. The dose of the impurity ions introduced at this time is, for example, 10 ¹³ atoms / cm ^2.
It is. After that, the resist film 57 is removed.

Next, as shown in FIG. 50 to FIG.
P-channel MISFETs Q3 and Q for configuring respective peripheral circuits of PROM 105 and EEPROM 107
6 is formed, and a resist film 58 having an opening in a region where the P-channel MISFET Q9 for forming the CPU 100 is formed is formed. Then, a p-type impurity such as boron (B) is introduced by ion implantation to form a p-type semiconductor region 11C which is a part of the source and drain of the P-channel MISFETs Q3, Q6, and Q9. The dose of the impurity ions at this time is, for example, 10
It is about ¹³ atoms / cm ² . After that, the resist film 58 is removed.

Next, as shown in FIGS. 53 to 55, a silicon oxide film is formed on the side portions of the respective gate electrodes 7A, 9A, 7B, 7C, 9C and 9D by using, for example, CVD and reactive ion etching. Is formed. Next, the P-channel MISFETs Q3 and Q9
Then, the region where the N-channel MISFET for forming the memory cells of the EEPROM 107 and their peripheral circuits is provided is covered with the resist film 59. Also, EPROM1
In order to increase the withstand voltage of the drain of the N-channel MISFET Q2 of the peripheral circuit 05, a resist film 59 is formed in order to keep a high-concentration portion at a predetermined distance from the sidewall 12 and the field insulating film 4. Then, n-type impurities such as arsenic (As) are introduced by ion implantation to form n + -type semiconductor regions 13A and 13B. After that, the resist film 59 is removed.

Next, as shown in FIGS. 56 to 58, respective N-channel MISFETs Q1, Q2, Q4, Q
5, Q7 and Q8 are covered with a resist film 60, and EE
P-channel MISFETQ of peripheral circuit of PROM107
In order to increase the withstand voltage of the drain 6, a resist film 60 is formed to separate the high concentration portion from the side wall 12 and the field insulating film 4 by a predetermined distance. Then, p-type impurities, for example, boron (B) are introduced by ion implantation to form respective p + -type semiconductor regions 13. After that, the resist film 60 is removed. Thereafter, as shown in FIGS. 5 to 7, the passivation film 14 is
It is formed by using a silicon oxide film by D, a PSG film, a silicon oxide film by BPSG film sputtering, or a laminated film of these.

Next, the connection hole 15 is formed by selectively removing the passivation film 14, and thereafter annealing is performed at a temperature of, for example, about 900 ° C. to reduce the step in the connection hole 15. Perform a glass flow. Next, an aluminum film is formed on the passivation film 14 by, for example, a sputtering method, a CVD method, or a vapor deposition method, and an aluminum alloy film containing aluminum as a main component and silicon, copper, or palladium added thereto, or On top of these films is a silicide film (MoSi
₂ , TaSi ₂ , TiSi ₂ , WSi ₂ ), and then pattern these films to form wirings 16 and data lines 16D.
To form The silicide film may be formed on the passivation film 14 before forming the aluminum film or the aluminum alloy film, and the aluminum film or the like may be formed thereon. After forming the wirings 16 and 16D, for example, a silicon oxide film by plasma CVD, a spin-on-glass film by spin coating,
A passivation film 17 is formed by stacking silicon oxide films by plasma CVD. Next, the connection holes 18 are formed by selectively removing the passivation film 17. Since the connection hole 18 has wiring layers 16 and 16D made of an aluminum film or the like having a low melting point at the lower portion, the step cannot be reduced by glass flow. Etching is performed to about half of the film thickness, and then the other half is formed by anisotropic dry etching. Next, a wiring 19 is formed on the passivation film 17 by the method of forming the wirings 16 and 16D.
Next, although not shown, a PSG film and a silicon nitride film are formed as final passivation.

FIGS. 29 to 31 and FIGS. 32 to 3
As shown in FIG.
M for configuring I / O 102 with SFETs Q7, Q9
The gate insulating film 8D of the ISFET Q8 is
105 second gate insulating film 8A and EEPROM 107
After forming the second gate insulating film 8C, the MISFE
The thin silicon oxide film 6 previously formed in the regions of TQ7, Q8 and Q9 is removed by etching, and then formed by a dedicated thermal oxidation process. Before forming the two-gate insulating film 8C, the MISFETs Q7, Q8,
The thin silicon oxide film 6 in the region of Q9 is etched.
The ETQ7, Q8, Q9 regions are oxidized to form a gate insulating film 8D.
May be formed.

The manufacturing method of this embodiment is similar to that of FIG.
To the memory cell Q1 of the EPROM 105 shown in FIG.
Is formed simultaneously with the first gate insulating film 6 of the memory MISFET Q4 of the memory cell of the EEPROM 107, but these are formed in separate steps so that It may be slightly different.

Next, a method of manufacturing a memory cell of a DRAM provided in the microcomputer of the present embodiment shown in FIG. 1 will be described.

FIGS. 59 to 62 show the DRA provided in the microcomputer of this embodiment shown in FIG.
FIG. 32 is a cross-sectional view in a manufacturing step of the M memory cell.

First, the sectional structure of the memory cell of the RAM will be described with reference to FIG. As shown in FIG.
The AM memory cell is provided in the p ~ type well region 3. And Q is the switch MISFET of the memory cell
And C is a capacitance element of the memory cell. Switch M
The ISFET Q has a gate insulating film 8D composed of a silicon oxide film and a gate electrode composed of a two-layer film formed by stacking a silicide film (MoSi ₂ , TaSi ₂ , TiSi ₂ , WSi ₂ ) on a polycrystalline silicon film, for example. (Word line) 9
D, n forming the source and drain portions on the channel region side
-Type semiconductor region 11B, n + -type semiconductor region 13 constituting a part of source and drain other than the n-type semiconductor region 11B
B. The capacitive element C includes an n-type semiconductor region 20 serving as one electrode, a dielectric film 22 formed of a thin silicon oxide film, and a conductive plate 7E formed of a different electrode, for example, a polycrystalline silicon film. It is configured. Switch MISFE of conductive plate 7E
An insulating film 21 made of a silicon oxide film thicker than the dielectric film 22 is provided at the end on the TQ side, so as to reduce the electric field at the end of the conductive plate 7E. An insulating film 23 made of a silicon oxide film is provided on the surface of the conductive plate 7E. A data line 16D is connected to the drain n + type semiconductor region 13B at the time of reading information.

Next, a method for manufacturing the memory cell of the DRAM will be described with reference to FIGS.

As shown in FIG. 60, the p ~ type semiconductor substrate 1
The p-type well region 3, the field insulating film 4, p
After forming the mold channel stopper region 5, the EPROM 1
14 and the step of forming the gate insulating film 6 of the memory cells Q1, Q4 and Q5 of the EEPROM 107 (FIGS.
In 6), a silicon oxide film 6 having a thickness of about 500 ° is formed in the memory cell region of the DRAM. However, the silicon oxide film 6 is not used as a gate insulating film of the switch MISFETQ. At this point, n shown in FIG.
The type semiconductor region 20 and the insulating films 21 and 22 are not formed. Thereafter, in the step of forming the n-type semiconductor regions 20 as the sources and drains of the memory cells Q4 and Q5 of the EEPROM 107, the n-type semiconductor region 20 as one electrode of the capacitor C is formed.

Next, in the step of forming the insulating film 21 of the memory cell of the EEPROM 107 (FIGS. 17 to 19), the insulating film 21 is formed in a region where the capacitor C is provided.
At this time, the region where the dielectric film 22 is provided is also the insulating film 2.
It is 1. The thickness of the insulating film 21 is 1000 to 20
It is about 00 °. Next, in the step of etching the insulating film 21 of the portion of the EEPROM 107 where the tunnel insulating film 22 is formed (FIGS. 20 to 22), the insulating film 21 of the portion of the capacitive element C where the dielectric film 22 is provided is selectively formed. To be removed. Next, the tunnel insulating film 22 of the EEPROM 107 is
Is formed, the dielectric film 22 of the capacitive element C is formed. Next, the floating gate electrodes 7A and 7C of the EPROM 105 and the EEPROM 107 and the gate electrodes 7B of the MISFETs Q2, Q3 and Q6 of the peripheral circuits, respectively.
In the step of forming (FIGS. 23 to 28), a plate electrode 7E of the capacitor C is formed as shown in FIG. Next, the surface of the conductive plate 7E is thermally oxidized to form an insulating film 23 made of a silicon oxide film. The insulating film 23
May be formed of a silicon oxide film by a CVD method,
Alternatively, a stack of a silicon oxide film formed by thermal oxidation and a silicon oxide film formed by CVD may be used. The insulating film 23
Is formed, the area where the switch MISFETQ is provided, the CPU 100, the I / O 102, the EPROM 105
And MISF constituting peripheral circuit of EEPROM 107
The silicon oxide film 6 in the region where the ET is provided becomes an insulating film 74 having a large thickness. In addition, EPROM 105 and EEP
A thick insulating film 23 is formed on the surfaces of the floating gate electrodes of the memory cells Q1 and Q4 of the ROM 107 and the gate electrode 7B of their peripheral circuits. Therefore, after the insulating film 23 is formed on the surface of the conductive plate 7E, for example, D
A portion of the capacitance element C of the RAM 109 is covered with a resist film,
The area where the switch MISFETQ is provided and the CPU 10
0, I / O 102, EPROM 105 and EEPROM
A thick insulating film 74 in a region where a MISFET constituting a peripheral circuit 107 is provided;
The thick insulating film 23 formed on the surfaces of the floating gate electrodes of the memory cells Q1 and Q4 of the OM 107 and the gate electrode 7B of their peripheral circuits is removed by etching. After removing the resist film, the EPROM
The surfaces of the floating gate electrodes 7A and 7C of the EEPROM 105 and the EEPROM 107 are thermally oxidized to form the second gate insulating film 8.
A and 8C are formed.

Next, as shown in FIG.
In the step of forming the gate insulating film 8D in the region of the I / O 102 (FIGS. 32 to 34), the gate insulating film 8D made of a silicon oxide film is formed in the region where the switch MISFETQ is provided. The gate insulating film 8D is made of EP
The second gate insulating films 8A, 8A on the surfaces of the floating gate electrodes 7A, 7C of the ROM 105 and the EEPROM 107
It may be formed simultaneously with the step of forming 8C. Next, in the step of forming the control gate electrodes 9A and 9C of the EPROM 105 and the EEPROM 107, the gate electrode 9D of the CPU 100 and the I / O 102 region (FIGS. 32 to 43), the gate electrode 9D of the switch MISFETQ is formed. Next, the EPROM 105 and the EE
When the insulating film 10 is formed on the surfaces of the control gate electrodes 9A and 9C of the PROM 107, the switch MISF
An insulating film 10 is formed on the surface of the gate electrode 9D of the ETQ. Thereafter, a sidewall 12 made of a silicon oxide film is formed. Next, the n-type semiconductor region 11B of the N-channel MISFET Q2 of the peripheral circuit of the EPROM 105 and the N-channel MISFET Q7 of the CPU 100 region
In the step of forming (FIGS. 47 to 49), the switch MI
N ~ forming the channel side of the source and drain of SFETQ
The type semiconductor region 11B is formed. Next, the EPROM 10
5 and the memory cells Q1 and Q4 of the EEPROM 107 and the MISFETs Q2 and Q5
00 and N-channel MISFETQ in I / O102 area
Steps of forming n + -type semiconductor regions 13A and 13B which are part of the source and drain of Q7 and Q8 (FIGS. 53 to 5).
In 5), the n + -type semiconductor region 13B of the source and drain of the switch MISFETQ is formed. Thereafter, a passivation film 14, a connection hole 15, a data line 16D, a passivation film 17, a wiring 19, and a final passivation film (not shown) are formed.

As described above, the EPROM 10
5. In the process of forming the EEPROM 107, the DRAM 10
9 can be formed.

Next, the operational amplifier, analog / digital converter,
The structure of the capacitance element and the resistance element in the digital / analog converter will be described. The resistance element and the capacitance element are used when the microcomputer performs an analog amount process.

FIG. 63 is a sectional view of the operational amplifier, the analog / digital converter, and the capacitance element and the resistance element included in the digital / analog converter in the microcomputer shown in FIG.

In FIG. 63, R is a resistive element used when processing an analog quantity, and C is a capacitive element used when processing an analog quantity.

The resistance element R includes a resistance layer 7G made of a first-layer conductor (polycrystalline silicon film) on the field insulating film 4, and connection terminals 7H provided on both ends of the resistance layer 7G. . Impurities are implanted into the connection terminal 7H at a high concentration so that an ohmic connection can be made with the wiring 16 made of aluminum or the like. Further, a wiring 16 to which a fixed potential Vcc or Vss is applied is provided above the resistance layer 7G. The potential of the n ~ -type well region 2 is fixed at Vcc or Vss. The capacitive element C includes a first electrode 7F made of a first-layer polycrystalline silicon film on the field insulating film 4, and a dielectric film 8F on the surface of the first electrode 7F.
And a second electrode 9F made of a second-layer conductive film provided on the first electrode 7F. The second conductive film is, for example, a silicide film (MoSi ₂ , TaSi ₂ , TiSi ₂ , WS) on a polycrystalline silicon film.
i ₂ ). First electrode 7F
The second electrode 9F has a low resistance by being doped with impurities at a high concentration. The wiring 16 is connected to each of the first electrode 7F and the second electrode 9F.

Next, a method for forming the resistance element R and the capacitance element C will be described. FIG. 64 to FIG. 66 are cross-sectional views in the manufacturing process of the resistance element and the capacitance element shown in FIG.

In the method of forming the resistance element R and the capacitance element C, as shown in FIG. 64, a first-layer polycrystalline silicon film 7 is formed on the field insulating film 4 by, for example, CVD. At this time, no impurity for lowering the resistance has been introduced into the polycrystalline silicon film 7. Next, as a buffer film when impurities are introduced into the polycrystalline silicon film 7 by ion implantation, for example, the surface of the polycrystalline silicon film 7 is thermally oxidized to form a silicon oxide film 61. Next, one or more of phosphorus (P), boron (B), arsenic (As), etc. are added to the polycrystalline silicon film 7 by ion implantation, for example, from 10 ¹² to 10 ¹² .
Implant about 10 ¹⁶ atoms / cm ² . When performing this ion implantation by thermal diffusion, the silicon oxide film 61 on the surface of the polycrystalline silicon film 7 is removed. Next, an impurity implantation mask 62 is formed above a predetermined region to be the resistance layer 7G.
The impurity implantation mask 62 may be formed of a resist film when the subsequent impurity implantation is performed by ion implantation, and may be formed of a silicon oxide film by CVD when the impurity implantation is performed by thermal diffusion. Then, the polycrystalline silicon film 7 is transferred to the memory cells Q of the EPROM 105 and the EEPROM 107.
1, 7 used as floating gate electrodes 7A, 7C, their peripheral circuits as gate electrodes 7B of MISFETs Q2, Q3, Q5, Q6. Therefore, after forming the impurity implantation mask 62, a second impurity implantation is performed to reduce the resistance of the polycrystalline silicon film 7. When the second impurity implantation is performed by thermal diffusion, the portion of the insulating film 61 not covered with the impurity implantation mask 62 is removed to expose the polycrystalline silicon film 7, and then the thermal diffusion is performed. I do.

Next, as shown in FIG.
The resistive layer 7G, the connection terminal 7H, and the first electrode 7F of the capacitive element C are formed by patterning the polycrystalline silicon film 7 using 3. At this time, the EPROM 105, the EEPROM
107, the floating gate electrodes 7A and 7C of the memory cells Q1 and Q4, and the MISFET Q of their peripheral circuits.
2, Q3, Q5 and Q6 gate electrodes 7B are also formed.
Next, FIG. 29, FIG. 30, FIG. 31 to FIG.
5, by the same process as FIG. 46, as shown in FIG.
Dielectric film 8F of capacitor C, second electrode 9F, resistor R
Then, a thin insulating film 10 covering the surfaces of the first electrode 7F and the second electrode 9F of the capacitor C is formed.

As a method of providing the resistance layer 7G with a predetermined resistance value, the second impurity implantation is performed in place of the low impurity implantation in the first impurity implantation as described above. Before or after the impurity implantation, an impurity of the opposite conductivity type to the impurity introduced in the second impurity implantation may be implanted, or a predetermined amount of an insulator such as oxygen or nitrogen may be implanted to form the resistance layer 7G. May be adjusted. Furthermore, the resistive layer 7G may be a polycrystalline silicon film 7 into which impurities are not implanted (however, the connection terminals 7H are implanted with impurities to reduce the resistance), or a conductive layer other than the resistive layer 7G. 7A, 7B, 7C, 7
Like H and 7F, a high concentration impurity may be introduced.

As described above, the resistance element R and the capacitance element C can be formed using the steps for forming the EPROM 105 and the EEPROM 107.

Next, FIG. 67 shows one I / O cell in the I / O 102 of the microcomputer shown in FIG.

The I / O cell shown in FIG. 67 is used to drive a fluorescent display tube and the like. The fluorescent display tube is driven in a large voltage range of, for example, about -40 to 0 V, and there is a large difference between 0 V and 5 V which is a normal operation range of the microcomputer. Therefore, for example, the voltage of about −40 V is converted to the normal operating voltage Vcc level of the microcomputer by the depletion type P-channel MISFET T _D1 ,
Channel MISFETT _P1 and N-channel MISFETT
The signal is input to the inverter consisting of _N1 , and thereafter various processing is performed. The N-channel MISFET shown in FIG.
Q8 corresponds to the N-channel MISFET T _N1 .
On the other hand, data output from the microcomputer to the fluorescent display tube is supplied to a depletion-type P-channel MISFET T _D2 via an inverter circuit including a P-channel MISFET T _P2 and an N-channel MISFET T _N2.
And an enhancement-type P-channel MISFET T _P3
Are output after voltage conversion by an inverter circuit consisting of

Next, the P channel MI shown in FIG.
FIG. 68 shows a cross-sectional structure of SFET _P3 . As shown in FIG. 68, the P-channel MISFET T _P3 is formed in the n − type well region 2I. This n-type well region 2I
Has a lower impurity concentration than the n − type well region 2 and a junction depth deeper than the n − type well region 2. The MISFET T _P3 includes a gate insulating film 6 made of a silicon oxide film, a gate electrode 7I made of, for example, a polycrystalline silicon film, a p-type semiconductor region 11I serving as a part of a source and a drain, and and a p + -type semiconductor region 13C forming a portion other than the p − -type semiconductor region 11I. The p ~ type semiconductor region 11I is provided below the field insulating film 4 without the gate electrode 7I,
Further, it is provided so as to surround the periphery of the p + type semiconductor region 13C. The end of the gate electrode 7I extends on the field insulating film 4. Under the field insulating film 4 in the n-type well region 2I, the p-type semiconductor region 1 is formed.
An n-type channel stopper region 5I is provided apart from 1I.

Next, a method of manufacturing the P-channel MISFET T _P3 will be described with reference to FIGS.

FIGS. 69 to 70 are cross-sectional views in the manufacturing process of the P-channel MISFET T _P3 operating in the range of 0 to +40 V.

In the method of manufacturing P-channel MISFET T _P3 , as shown in FIG. 69, first, in order to form n − type well region 2I, the surface of p − type semiconductor substrate 1 is thermally oxidized to form silicon oxide film 64. Form. Next, a silicon nitride film 66 is formed thereon as a mask for heat-resistant oxidation, and ion implantation is performed using the silicon nitride film 66 as a mask for ion implantation to form an n-type well region 2I. Next, a portion of the surface of the semiconductor substrate 1 exposed from the silicon nitride film 66, that is, the n − well region 2 I is thermally oxidized to form a silicon oxide film 65 slightly thicker than the silicon oxide film 64.

As shown in FIG. 70, a silicon nitride film 66
Is removed, a new silicon nitride film is formed, and the silicon nitride film in the formation region of the n-type well region 2 is removed,
After performing ion implantation to form the n-type well region 2,
A silicon oxide film 65 is formed on the surface by thermal oxidation. Thereafter, the silicon nitride film is removed.
As shown in FIG. 6, the silicon oxide film 64 and the silicon oxide film 6
Using the film thickness difference of 5, a p-type impurity is implanted into a portion of the semiconductor substrate 1 other than the n-type well region 2I and the n-type well region 2 to form a p-type well region 3. Next, on the silicon oxide films 64 and 65, the silicon nitride film 6 is used as a thermal oxidation mask when the field insulating film 4 is formed.
8 is formed. Next, as a mask for forming the n-type channel stopper region 5I, the n-type well region 2I,
A resist film is formed on n-type well region 2 and p-type well region 3. Then, an n-type impurity is ion-implanted into the surface of the n ~ -type well region 2I to form an n-type channel stopper region 5I. After that, the resist film 68 is removed.

Next, as shown in FIG. 72, a new resist film 69 is formed, and ions are implanted into the surface of the n マ ス ク -type well region 2I by using the resist film 69 and the silicon nitride film 68 as a mask. The type semiconductor region 11I is formed. Thereafter, the resist film 69 is removed. Next, as shown in FIG. 73, a p-type impurity is ion-implanted into the surface of the p ~ -type well region 3 by utilizing the thickness difference between the silicon oxide film 64 and the silicon oxide film 65 to form a p-type channel stopper. Region 5 is formed. Thereafter, the portions of the nｎ-type well region 2I, the n ~ -type well region 2 and the p ~ -type well region 3 exposed from the silicon nitride film 68 are thermally oxidized to form the field insulating film 4. Thereafter, the EP shown in FIGS.
Memory cell Q1 of ROM 105, MISFE of peripheral circuit
TQ2, Q3, the memory MISFET Q4 of the memory cell of the EEPROM 107, and the switch M in the memory cell
N-channel MISFET Q5 for forming ISFET or peripheral circuit, P-channel MISFET for peripheral circuit
In the step of forming Q6, the gate insulating film 6, the gate electrode 7I, the insulating film 10, and the side wall 1 shown in FIG.
2. p + type semiconductor region 1 forming a part of source and drain
Form 3C. Further, a first passivation film 14, a connection hole 15, a wiring 16, a second passivation film 17, a connection hole 18, a wiring 19, and a final passivation film (not shown) are formed.

The P-channel MI shown in FIG.
The SFET may be configured using a gate insulating film 70 thicker than the gate insulating film 6, as shown in FIG.

FIG. 74 shows the P channel MI shown in FIG.
P-channel MISFET and N-channel MISF using gate insulating film 70 thicker than gate insulating film 6 of SFET
It is sectional drawing of ET.

In FIG. 74, a P-channel MISFET is formed in the left n− type well region 2I. This P
The gate insulating film 70 of the channel MISFET is made of a silicon oxide film and has a large thickness of about 1000 to 2000 °. An N-channel MISFET operating in the range of 0 to +40 V is formed in the p <-> well region 3. This N-channel MISFET has a gate insulating film 70
And a gate electrode 7J made of, for example, a polycrystalline silicon film.
And n-type semiconductor region 5I forming a part of source and drain
And an n + -type semiconductor region 13B which is a source and a drain other than the n-type semiconductor region 5I. The gate electrode 7J also extends on the field insulating film 4. The n-type semiconductor region 5I is provided below the field insulating film 4 and is provided so as to surround the n + -type semiconductor region 13B. Further, a p-type channel stopper region 5J having a higher impurity concentration than the p-type channel stopper region 5 is provided between the n-type semiconductor region 5I and the n-type well region 2I and between the n-type semiconductor region 5I and the p-type channel stopper region 5.
Is provided.

Next, the P channel MI shown in FIG.
FIG. 7 shows a method of manufacturing an SFET and an N-channel MISFET.
5 will be described.

FIG. 75 shows the P channel MI shown in FIG.
It is sectional drawing in the manufacturing process of SFET and N channel MISFET.

In the P-channel MISFET and the N-channel MISFET shown in FIG. 75, the n-type well region 2I (and 2 ), P ~ type well region 3,
An n-type semiconductor region 5I, a p-type semiconductor region 5J, a p-type semiconductor region 11I, a p-type channel stopper region 5, and a field insulating film 4 are formed. Thereafter, a silicon nitride film 68 (FIG. 71), which is a thermal oxidation mask used when forming the field insulating film 4, and a silicon oxide film 64 thereunder,
65 is removed to expose the surfaces of the portions of the n ~ -type well region 2I (and 2) and the p ~ -type well region 3 that are not covered with the field insulating film 4. Then, the exposed surfaces of the n ~ -type well region 2I (and 2) and the p ~ -type well region 3 are thermally oxidized to form a gate insulating film 70. After this, FIG.
P-channel MISFET and N-channel MI shown in FIG.
The gate insulating film 70 other than the region where the SFET is provided is removed by etching using a resist film. Then, after removing the resist film, the n-type well region 2I is again formed.
(And 2) and thermally oxidize the surface of the p ~ type well region 3,
For example, the gate insulating film 6 of the MISFET operating in the range of 0 to 5 V is formed.

Thereafter, the memory cell Q1 of the EPROM 105 and the MI of the peripheral circuit shown in FIGS.
SFETs Q2 and Q3, a memory MISFET Q4 of a memory cell of the EEPROM 107, an N-channel MISFET Q5 which is a switch MISFET in the memory cell,
In the step of forming the P-channel MISFET Q6 of the peripheral circuit, the gate electrodes 7I and 7J, the insulating film 10, the sidewall 12, the n + -type semiconductor region 13B which is a part of the source and drain of the N-channel MISFET, and the P-channel MIS
P + -type semiconductor region 13C that is a part of the source and drain of the FET, passivation film 14, connection hole 15, wiring 16, passivation film 17, connection hole 18, and wiring 19
Then, a final passivation film (not shown) is formed.

As described above, the microcomputer of the present embodiment employs the M
Gate electrode 7B of ISFET Q2, Q3, EEPROM
The gate electrodes 7B of the MISFETs Q5 and Q6 of the peripheral circuit 107 are formed using the first-layer polycrystalline silicon film. However, with the miniaturization of the semiconductor integrated circuit device, the first-layer polycrystalline silicon film is formed. The thickness of the silicon film is reduced. Also,
The thickness of the silicon oxide film 10 on the surface of the gate insulating film 6 and the gate electrode 7B is also reduced. For this reason, at the time of ion implantation for forming the source and the drain, impurity ions are added to the silicon oxide film 10, the gate electrode 7, the gate insulating film 6
Leaks into the channel region through the
The threshold values of ISFETs Q2, Q3, Q5, and Q6 may deviate from predetermined values. To solve this,
If a thick silicon oxide film is formed on the first polycrystalline silicon film by, for example, CVD or the like, and then the silicon oxide film and the polycrystalline silicon film are patterned to form a gate electrode 7B, the gate electrode 7B Since there is a thick silicon oxide film thereon, it is possible to prevent impurity ions from leaking into the channel region during the ion implantation.
However, as described above, the first-layer polycrystalline silicon film is formed of the floating gate electrode 7A of the memory cell Q1 of the EPROM 105 or the floating gate electrode 7 of the memory MISFET Q4 of the memory cell of the EEPROM 107.
Since the second gate insulating films 8A and 8C made of a thin silicon oxide film have to be formed thereon, as described above, a thick oxide film is simply formed on the polycrystalline silicon film by CVD or the like. There is a problem that a silicon film cannot be formed.

Therefore, a method of forming a source and a drain in a MISFET in which a gate electrode 7B is formed of a first-layer polycrystalline silicon film without leaking impurity ions into a channel region will be described.

FIGS. 76 to 81 show MISFETs in which a gate electrode is formed of a first conductive film, for example, a polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region. It is a figure for explaining a manufacturing method. 76 to 81, the area indicated by Q1 is an area where the memory cells of the EPROM 105 are formed, and the area indicated by Q2 is the EP
This is an area where the N-channel MISFET of the peripheral circuit of the ROM 105 is formed.

As shown in FIG. 76, a method for forming a MISFET without leaking impurity ions into the channel region is to form a first-layer polycrystalline silicon film 7 and a predetermined impurity for lowering the resistance. After injecting, for example, C
A thick silicon oxide film 71 is formed by VD.

Next, as shown in FIG.
The silicon oxide film 71 in the region where the memory cell Q1 of 05 is formed is removed by etching using, for example, a resist film as a mask. The resist film is removed after the silicon oxide film 71 is selectively removed. Next, the polycrystalline silicon film 7 is patterned by etching using a resist film (not shown) as a mask, and as shown in FIG.
The floating gate electrode 7A of the memory cell Q1 of the OM 105 and the gate electrode 7B of the MISFET Q2 are formed. The resist mask is removed after patterning. Gate electrode 7B of N-channel MISFET Q2
On top of this is a thick silicon oxide film 71.

Next, as shown in FIG. 79, the surface of floating gate electrode 7A is thermally oxidized to form second gate insulating film 8A. Next, as shown in FIG. 80, a second-layer conductive film is formed on the semiconductor substrate (chip) 1 and patterned to form a control gate electrode (word line) 9A of the EPROM 105. Next, as shown in FIG. 81, the n-type semiconductor region 11A forming a part of the source and the drain of the memory cell Q1, the MISFET of the peripheral circuit
N ~ type semiconductor region 11B forming part of the source and drain of Q2, memory cell Q1, and MISFET Q of the peripheral circuit
The n + -type semiconductor regions 13A and 13B, which constitute the other portions of the source and drain of No. 2, are formed.

As described above, the N-channel MISFET
If the source and drain of Q2 are formed, the thick silicon oxide film 71 is on the gate electrode 7B, so that impurities for forming the source and drain can be prevented from leaking to the channel region.

As described above, according to the present embodiment, the following effects can be obtained.

(1) In a semiconductor integrated circuit device constituting a microcomputer having a central processing unit and a nonvolatile memory for storing program data and dictionary data of the central processing unit on one semiconductor chip, The nonvolatile memory electrically performs writing of information,
A first nonvolatile memory (EPROM 105) for erasing the written information by irradiating ultraviolet rays, and a second nonvolatile memory (EEPROM 107) for electrically writing the information and electrically erasing the information.
, A large capacity and rewritable R
An OM can be obtained, and an electrically rewritable ROM can be obtained on the system.

(2) From the above (1), an EPROM is used to store data that requires a large capacity but a small number of rewrites.
The EEPROM 107 is used to store data that requires a large number of rewrites but can be stored in a small capacity or that needs to be stored even after the power is turned off. It is possible to obtain a semiconductor integrated circuit device composed of a macro computer provided with a ROM having a high degree of freedom, which compensates for the disadvantage that it cannot be replaced and the disadvantage that the memory capacity of the EEPROM 107 is small.

That is, program data and dictionary data that require a large storage capacity are stored in the EPROM 105, and are stored even when the data content changes over time and the power is turned off, such as control data for feedback control. The control data that needs to be stored is EEPROM
Since the data can be stored in the memory 107, the function of the semiconductor integrated circuit device including the one-chip microcomputer can be improved.

(3) A nonvolatile RAM can be obtained from the EEPROM 107 of the above (1).

(4) Since the SRAM is provided as the first RAM of the one-chip microcomputer, a RAM capable of performing high-speed data transfer can be obtained.

(5) Since a DRAM is provided as the second RAM of the one-chip microcomputer, a large-capacity RA
M can be obtained.

(6) From the above (4) and (5), it is not necessary to perform high-speed data transfer by using an SRAM for storing data that requires a small capacity but requires high-speed data transfer. D for storing data that requires a large storage capacity
By using a RAM, it is possible to obtain a RAM that compensates for the disadvantage that the capacity of the SRAM cannot be increased and the disadvantage that the transfer speed of the DRAM is low.

(7) EPRO is applied to the first region of the semiconductor substrate 1.
Forming a memory cell Q1 of M105;
Of the EEPROM 107 in a second area different from the first area.
Forming a memory MISFET Q4 in the memory cell of
A switch MIS in a memory cell of the EEPROM 107 is provided in a third region of the semiconductor 1 adjacent to the second region.
In a method of manufacturing a semiconductor integrated circuit device constituting a microcomputer including a step of forming an FET Q5,
Forming a first gate insulating film 6 on the surface of the first, second and third regions of the semiconductor substrate 1, respectively;
Forming a source and a drain 20 at predetermined portions of the first and second regions below the first gate insulating film 6; and forming floating gate electrodes 7A and 7A on the first gate insulating film 6 of the first and second regions. 7C and the first region of the third region.
Forming a gate electrode 7B on the gate insulating film 6, forming second gate insulating films 8A and 8C on the surfaces of the floating gate electrodes 7A and 7C in the first region and the second region, Forming control gate electrodes 9A and 9C on the second gate insulating films 8A and 8C in the first and second regions, respectively; 11A,
13A, a step of forming the n-type semiconductor region 20 serving as a source and a drain of the EEPROM 107 in the step of forming the EPROM 105 by performing the above-described steps in the order described above.
The EEPROM 107 can be formed only by adding a step of forming the tunnel insulating film 22 on the above.

(8) Memory cell Q1 of EPROM 105
Floating gate electrode 7A and the EEPROM 10
7 is connected to the first conductive layer (polycrystalline silicon film) of the floating gate electrode 7C of the storage element Q4 in the memory cell Q7.
The first gate insulating film 6 of each of the devices Q1 and Q4 is formed in the same step, and the second gate insulating films 8A and 8A on the floating gate electrodes 7A and 7C of the devices Q1 and Q4 are formed. By forming 8C in the same step, each memory cell of EPROM 105 and EEPROM 107 can be obtained with a small number of manufacturing steps.

(9) The gate insulating films 6 of the MISFETs Q2 and Q3 constituting the peripheral circuit of the EPROM 105 and the MISFETs Q5 and Q6 constituting the peripheral circuit of the EEPROM 107 are connected to the first memory cell Q1 of the EPROM 105.
Since the gate insulating film 6 and the first gate insulating film 6 of the memory MISFET Q4 in the memory cell of the EEPROM 107 are formed in the same process, the MISFETs of those peripheral circuits are formed.
The thickness of the gate insulating film 6 of Q2, Q3, Q5, Q6 is increased, and the withstand voltage can be improved.

(10) CPU (Logic Unit) 100 and I / O
The first gate insulating film 6D of the memory cell Q1 of the EPROM 105 and the first gate insulating film 6 of the memory MISFET Q4 in the memory cell of the EEPROM 107
Therefore, the thickness of the gate insulating film 8D and the thickness of the gate insulating film 6 can be independently set to optimal values.

(11) CPU (logic unit) 100 and I / O
Since the gate electrodes 9D of the MISFETs Q7 to Q9 for forming the O102 are formed of a second conductive layer, that is, a two-layer film in which a silicide film is laminated on a polycrystalline silicon film, for example, the gate electrode 9D is low. Resistance can be achieved.

(12) From the above (8) to (11), the EPROM 105 including peripheral circuits and the EEPROM
Voltage applied to MISFET of M107 and CPU
(Logic unit) 100 and M for configuring the I / O 102
Since the voltage applied to ISFET can be set independently,
The structure of each element can be set independently.

(13) The DRAM 109 is replaced with the EEPROM 1
07 or almost the same process.

(14) Because of the above (12), DRA
The dielectric film 22 of the capacitance element C of the memory cell of M109 is
Tunnel insulating film 22 of memory cell of EEPROM 107
Since the capacitor C is formed very thin, the capacitance of the capacitor C can be increased.

(15) A large capacity DRAM can be obtained from the above (14), and a large capacity RAM can be obtained from this.

(16) The resistance element R constituting the analog circuit is replaced with a memory cell of the EPROM 105 or an EEPROM.
It can be formed in the same step or almost the same step as the floating gate electrodes 7A and 7C of the memory MISFET Q4 in the memory cell of M107.
It can be formed in the same process as the memory cells of the PROM 105 or the EEPROM 107.

(17) Since the resistance element R and the capacitance element C are covered with the insulating film 10, stable resistance and capacitance values can be obtained during operation of the circuit.

(18) Since the well region below the resistance element R and the capacitance element C is electrically fixed, a stable resistance value and capacitance value can be obtained during operation of the circuit.

(19) Since the upper part of the resistance element R is covered with the conductive layer 19 at a fixed potential, another signal wiring can be extended on the conductive layer 19.

(20) From the above (16) to (19),
It is possible to easily obtain stable resistance elements R and capacitance elements C required for processing an analog quantity of a one-chip microcomputer.

(21) EPROM 105, EEPROM
A high-breakdown-voltage MISFET can be formed in substantially the same process as the process of forming the DRAM 107 and the DRAM 109.

(22) Since the gate electrode 7I of the high-breakdown-voltage MISFET extends over the field insulating film 4 so that its end is on the field insulating film 4,
The withstand voltage between the gate electrode 7I and the semiconductor substrate 1 can be improved.

(23) By enclosing the high impurity concentration semiconductor region which is a part of the source and drain of the high withstand voltage MISFET with a low impurity concentration semiconductor region, the withstand voltage of the source and drain can be improved. it can.

(24) From the above (21) to (23), a high-breakdown-voltage MISFET used for the I / O 102 of the one-chip microcomputer can be easily obtained.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it can be said that various modifications can be made without departing from the gist of the present invention. Not even.

For example, the microcomputer shown in FIG. 1 includes the SRAM 108 and the DRAM 109 as the RAM, but either the SRAM 108 or the DRAM 109 may be used.

[0166]

The effects of typical inventions among the inventions disclosed by the present application will be briefly described as follows.

Source of MISFET in CPU and I / O
・ Low-concentration and high-concentration semiconductor regions in the drain region respectively
And a low-concentration semiconductor region of the MISFET in the I / O
Higher than that in the CPU,
MISFET is destroyed when voltage is applied.
Can be prevented. MISFE in the peripheral circuit
Make the gate insulating film of T thicker than that in the CPU
Thereby, the withstand voltage can be improved .

[0168]

[0169]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a memory cell of an SRAM 108 included in the microcomputer shown in FIG.

FIG. 3 is a diagram showing an E mounted on the microcomputer.
FIG. 2 is an equivalent circuit diagram showing a schematic configuration of a PROM 105.

FIG. 4 shows an E mounted on the microcomputer.
FIG. 2 is an equivalent circuit diagram showing a schematic configuration of an EPROM 107.

FIG. 5 shows EPROM and EE of the microcomputer.
MISFET which constitutes the logic part such as PROM and CPU
It is sectional drawing in the manufacturing process.

FIG. 6 shows EPROM and EE of the microcomputer.
MISFET which constitutes the logic part such as PROM and CPU
It is sectional drawing in the manufacturing process.

FIG. 7 shows the EPROM and EE of the microcomputer.
MISFET which constitutes the logic part such as PROM and CPU
It is sectional drawing in the manufacturing process.

FIG. 8 shows EPROM and EE of the microcomputer.
MISFET which constitutes the logic part such as PROM and CPU
It is sectional drawing in the manufacturing process.

FIG. 9 shows the EPROM and EE of the microcomputer.
MISFET which constitutes the logic part such as PROM and CPU
It is sectional drawing in the manufacturing process.

FIG. 10 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 11 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 12 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 13 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 14 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 15 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 16 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 17 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 18 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 19 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 20 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 21 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 22 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 23 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 24 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 25 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 26 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 27 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 28 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 29 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 30 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 31 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 32 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 33 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 34 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 35 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 36 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 37 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 38 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 39 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 40 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 41 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 42 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 43 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 44 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 45 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 46 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 47 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 48 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 49 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 50 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 51 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 52 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 53 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 54 shows EPROM and E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 55 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 56 shows an EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 57 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 58 shows EPROM, E of the microcomputer.
MISFE that constitutes a logic unit such as an EPROM and a CPU
It is sectional drawing in the manufacturing process of T.

FIG. 59 is a sectional view of a DRAM memory cell provided in the microcomputer in a manufacturing step;

FIG. 60 is a sectional view of a DRAM memory cell provided in the microcomputer in a manufacturing step;

FIG. 61 is a sectional view of a DRAM memory cell provided in the microcomputer in a manufacturing step;

FIG. 62 is a cross-sectional view in a manufacturing step of a memory cell of the DRAM provided in the microcomputer.

FIG. 63 is a cross-sectional view of a capacitive element and a resistive element in the operational amplifier, analog / digital converter, and digital / analog converter provided in the microcomputer.

64 is a cross-sectional view in a manufacturing step of the capacitor and the resistor shown in FIG. 63.

FIG. 65 is a cross-sectional view in a manufacturing step of the capacitor and the resistor shown in FIG. 63;

FIG. 66 is a sectional view in a manufacturing step of the capacitor and the resistor shown in FIG. 63;

FIG. 67 is an equivalent circuit diagram showing one I / O cell in the I / O of the microcomputer shown in FIG. 1;

FIG. 68 is a sectional view of the P-channel MISFET shown in FIG. 67;

69 is a cross-sectional view in a manufacturing step of the P-channel MISFET T _P3 shown in FIG. 68.

It is a cross-sectional view in the manufacturing process of FIG. 70 P-channel MISFETT _P3 shown in FIG. 68.

FIG. 71 is a cross-sectional view in a manufacturing step of the P-channel MISFET T _P3 shown in FIG. 68.

FIG. 72 is a cross-sectional view in a manufacturing step of the P-channel MISFET T _P3 shown in FIG. 68.

73 is a cross-sectional view in a manufacturing step of the P-channel MISFET T _P3 shown in FIG. 68.

74 is a cross-sectional view of a P-channel MISFET and an N-channel MISFET using a gate insulating film 70 thicker than the gate insulating film 6 of the P-channel MISFET shown in FIG.

75 shows the P-channel MISFET and N shown in FIG. 74.
FIG. 10 is a cross-sectional view in a manufacturing step of the channel MISFET.

FIG. 76 shows an MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing an FET.

FIG. 77: MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions to a channel region
FIG. 3 is a cross-sectional view illustrating a method for manufacturing an FET.

FIG. 78 illustrates a MIS in which a gate electrode is formed using a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing an FET.

FIG. 79: MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions to a channel region.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing an FET.

FIG. 80: MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film, and a source and a drain can be formed without leaking impurity ions into a channel region
FIG. 3 is a cross-sectional view illustrating a method for manufacturing an FET.

FIG. 81: MIS in which a gate electrode is formed of a first-layer polycrystalline silicon film and a source and a drain can be formed without leaking impurity ions to a channel region
FIG. 3 is a cross-sectional view illustrating a method for manufacturing an FET.

[Explanation of symbols]

1. Semiconductor chip (microcomputer), 100 ...
CPU, 101 ... OSC, 102 ... I / O, 103 ... S
I, 104: TIMER, 105: EPROM, 106
... voltage control circuit, 107 ... EEPROM, 108 ... SR
AM, 109 ... DRAM, 110 ... I / OBUS, Q1
... EPROM memory cells, Q2, Q3.
ISFET, Q4... Storage elements in EEPROM memory cells, Q5, Q6.
FET, Q7, Q9 ... MISFET of CPU, Q8 ... M
ISFET, 6 ... first gate insulating film, 7A, 7B, 7C
... Gate electrodes made of first conductive film, 8A, 8C ...
A second gate insulating film on the floating gate electrode, 8
D: first gate insulating film of CPU and I / O area, 9A,
9C, 9D: gate electrodes made of a second conductive film, 1
0: thin silicon oxide film; 11A, 11B, 11C: low concentration layers of source and drain; 12: sidewalls;
3A, 13B, 13C: high concentration layers of source and drain,
20: n-type source and drain of EEPROM; 21: thick gate insulating film; 22: tunnel insulating film.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/788 29/792

Claims (4)

(57) [Claims] A plurality of data lines and a plurality of word lines provided at intersections between the plurality of data lines and a plurality of word lines, the plurality of data lines being electrically writable and erasable ;
A memory array having a non-volatile memory cells, a memory unit and a peripheral circuit which controls the plurality of nonvolatile memory cells are connected to the memory unit via an internal bus, a CPU that operates at a power supply voltage, I / O and write or erase operation to the nonvolatile memory cell
For Nau, the power supply and a voltage control circuit for generating a voltage higher than the voltage built on the same semiconductor chip, the peripheral circuit and operating power and a voltage generated by the voltage control circuit and the power supply voltage, the film thickness of the gate insulating film of the 1MISFET in the peripheral circuit greatly than the film thickness of the gate insulating film of the 2MISFET in the CPU, the source and drain regions of said first 2MISFET it
A first semiconductor region and an impurity concentration higher than that of the first semiconductor region.
The second MISFET in the I / O.
The regions are respectively the third semiconductor region and the third semiconductor region.
A fourth semiconductor region having a high impurity concentration, wherein the second and third MISFETs have the same conductivity type MISFE.
T, wherein the impurity concentration of the third semiconductor region is equal to that of the first semiconductor region.
Semiconductor integrated circuit device having a higher impurity concentration 2. The semiconductor chip further comprises a RAM.
However, the data input from the I / O is controlled by the CPU.
Write to the nonvolatile memory cell via the RAM.
The semiconductor integrated circuit device according to claim 1, characterized in that it is written come. 3. The gate insulating film of the first MISFET
The thickness is larger than the thickness of the tunnel insulating film in the memory cell.
Any of claims 1 to 2, characterized in that heard
3. The semiconductor integrated circuit device according to 1. 4. The device according to claim 1, wherein the peripheral circuit includes a data input / output circuit coupled to the plurality of data lines and having a latch circuit, and an address decoder.
The semiconductor integrated circuit device according to claim 3.